JPS6142183Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is an arithmetic checking circuit, especially when performing error checking using a residual (hereinafter referred to as "residue").
The present invention relates to an arithmetic check circuit in which a recipe for a set of data is created by a set of recipe generating circuits and the recipe is checked.

As an arithmetic check circuit, an error check circuit using a recipe is well known. FIG. 1 shows a conventional example of a recipe check circuit for a multiplier. In Figure 1, 1 is the multiplicand register, 2 is the multiplier register, and 3 is the multiplicand register.
For example, is a selection circuit that divides and supplies a 56-bit multiplier into 7 groups of 8 bits each, 4 is a register, 5 is a multiplier, 6 is a sum register, 7 is a carry register, and 8 and 9 are recipe generation circuits. ,1
0 and 11 are registers, 12 is a recipe addition circuit, 13 is a comparison circuit, 14 and 15 are recipe generation circuits, 16 and 17 are registers, 18 is a recipe addition circuit, 19 is a register, 20 and 21 are recipe generation circuits, 22 and 23 are registers, and 24 is a recipe multiplication circuit.

Multiplier 5 is composed of a carry save adder,
The calculation result is stored in register 7 in the form of carry C and sum S.
(C-Reg) and register 6 (S-Reg).

When multiplying a 56-bit multiplicand by a 56-bit multiplier, the multiplier is divided into seven groups of 8 bits each, and the lowest group is multiplied by the multiplicand in the first cycle. In the second cycle, the next upper group 8 bits are multiplied by the multiplicand, and the first
The result obtained in the cycle is shifted by 8 bits and added to the multiplication result. In this way, when the multiplication for 7 cycles is completed, the register (C-Reg) and register 6 (S-Reg), which are the results of the multiplication, are
-Reg) is supplied to a carry propagation adder (not shown) and added to obtain the final multiplication result. The recipe check circuit in such a multiplier is described in detail in, for example, Japanese Patent Publication No. 53-5095, so a description of the operating principle etc. will be omitted here.

As shown in FIG. 1, the conventional recipe check circuit includes recipe generation circuits 20 and 20, respectively, which generate recipes for the multiplicand (CAND) and multiplier (IER) that are input to the multiplier 5 in the relevant cycle.
21, and each recipe generation circuit 1 that generates Sam and Carrie's recipes up to one cycle before.
4 and 15, and recipe generation circuits 8 and 9 for generating sum and carry recipes of the calculation results up to the relevant cycle.

The output RCAND of register 22 and the output RIER of register 23 are multiplied, and the multiplication result is further multiplied by the output RPPS of register 16 and the output of register 17.
RPPC is added and one receipt Ri is obtained. Then, add the output RSUM of register 10 and the output RCRY of register 11 to obtain the other recipe.
Ro is obtained, Ri and Ro are compared, and if there is a mismatch, an error signal is generated.

According to the above configuration, of the multiplication device including the error check circuit, the error check circuit is
This amounted to about 30%, which posed the problem of requiring a large amount of hardware for the error check circuit.

The purpose of the present invention is to solve the above problems and reduce the amount of hardware required for the error check circuit. Therefore, the present invention aims to solve the above-mentioned problems and reduce the amount of hardware required for the error check circuit. Therefore, the present invention aims to solve the above problems and reduce the amount of hardware required for the error check circuit. a first register for temporarily holding the output of the above-mentioned residue generation circuit; , second and third registers are provided corresponding to the two sets of data and hold the recipes obtained by the recipe generation circuit, and in the first half of one cycle, the two sets of data are stored by the recipe generation circuit. A recipe for one of the two sets of data is created and held in the first register, and in the second half of the cycle, the recipe generating circuit generates a recipe for the other data of the two sets of data and the recipe is stored in the second register. and a predetermined one of the third registers, and the output of the first register is set to a predetermined other register of the second and third registers. .

The present invention will be explained below with reference to the drawings.

FIG. 2a shows a part of a recipe test circuit according to an embodiment of the present invention, and FIG. 2b shows a time chart of the circuit shown in FIG. 2a.

In Figure 2a, the same numbers as in Figure 1 are the same, 30 is a recipe generation circuit, 31 and 32
3 is an input gate circuit that controls the sending of input data to the recipe generation circuit 30; 33 is an OR circuit;
Reference numeral 4 denotes a register that temporarily holds the recipe obtained when the recipe of the data in register 6 (S-Reg) is created.

As is clear from the time chart in FIG. 2b, the input gate 31 opens in the first half of one cycle.
The data in the register 6 (S-Reg) is input as SIN to the recipe generation circuit 30 through the OR circuit 33. And the created recipe is 1/2
It is set in register 34 at the time of the cycle.
Next, in the latter half of one cycle, the input gate 32 opens, and the data in the register 7 (C-Reg) passes through the blue circuit 33 as CIN to the recipe generation circuit 30.
is input. The created recipe is set in the register 11 at the end of one cycle. Note that at the end of one cycle, register 3 is
The contents of 4 are set in register 10. Then, in the next cycle, the contents of register 10 and register 11 are added in the recipe addition circuit 12, and the addition result Ro and register 1 shown in FIG.
9 is compared with the recipe Ri in the comparator circuit 13.

Similarly, the recipe generation circuits 14 and 15 and the recipe generation circuits 20 and 21 shown in FIG.
can each be replaced with a single recipe generation circuit.

As described above, according to the present invention, when generating a recipe for two sets of data, one set of recipe generation circuits is shared, the recipe for one data is generated in the first half of one cycle, and the recipe for the other data is generated in the second half. Since this method is made, the amount of hardware for the arithmetic and test circuit can be greatly reduced, resulting in an excellent effect of improving economic efficiency.

Although the above embodiment shows a recipe check circuit for multiplication processing, it is clear that the present invention is not limited to multiplication processing.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example of a recipe test circuit for a multiplier, FIG. 2 a shows a part of a recipe test circuit according to an embodiment of the present invention, and FIG. be. In the figure, 1 is the multiplicand register, 2 is the multiplier register, 5 is the multiplier, 6 is the sum register, 7 is the carry register, 8, 9, 14, 15, 20, 21
and 30 are recipe generation circuits, 12 and 18 are recipe addition circuits, 13 is a comparison circuit, 24 is a recipe multiplication circuit, 31 and 32 are input gate circuits, and 10, 11 and 34 are registers.

Claims (1)

[Claims for Utility Model Registration] When generating two sets of data recipes in an arithmetic inspection circuit that performs a recipe check of an arithmetic processing circuit, one set of recipe generation circuits and one of the two sets of data a gate means for selectively inputting the input to the recipe generation circuit; a first register for timing waiting that temporarily holds the output of the recipe generation circuit;
A second and a third register are provided corresponding to the set of data and hold the recipe obtained by the recipe generation circuit, and one of the two sets of data is generated by the recipe generation circuit in the first half of one cycle. A recipe of data is generated and held in the first register, and in the second half of the cycle, a recipe of the other data of the two sets of data is generated by the recipe generating circuit and the recipe is transferred to the second and third registers. an arithmetic test characterized by setting the output of the first register to a predetermined one of the registers, and simultaneously setting the output of the first register to a predetermined other register of the second and third registers. circuit.