JPH0439726A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To reduce the number of adders by providing a partial product generating part for generating a partial product of a multiplier bit and a multiplicand, a carry holding part for holding a carry generated by addition and a holding part of a result of addition. CONSTITUTION:In the case of a simple multiplier, the product of a first bit from the lower side of a shift register 12 and the contents of a shift register 11 is derived by a partial product generating part 14, and it is stored in a flip- flop 17. Subsequently, the shift registers 11, 12 are bit-shifted, the product of all bits of a multiplier and a multiplicant is derived, addition of a result of addition until the previous time and a carry is executed, and its result is fetched through a register 19 from the flip-flop 17. In such a way, multiplication is executed by using repeatedly a hardware, therefore, however the multiplication bits increase, the hardware scale is not increased.

Description

[Detailed Description of the Invention] [Summary of the Invention] This invention relates to a multiplication circuit, particularly in arithmetic processing units such as microprocessors and DSPs, which is effective in executing multiplication instructions in which the word length of the multiplier and multiplicand is 8 to 32 bytes. , aims to provide a multiplier that can reduce the number of adders and has a small amount of hardware, and includes a first shift register to which a multiplicand is set, a second shift register to which a multiplier is set, and a multiplier bit. and a partial product generator that generates a partial product between and the multiplicand, and
．． The first . of the multiplier is obtained by generating partial products while shifting the second shift register. 2nd, . . . the first . . . of the bit and the multiplicand. 2nd degree: an adder that adds the partial product and each output of the holding unit for the sum of partial products up to the previous time and the carry holding unit; and the carry holding unit that holds the carry generated by the above addition. and a holding unit for addition results, and a first shift register in which a multiplicand is set and shifts 2 bits at a time, and a second shift register in which a multiplier is set and shifts 2 bits at a time. and take in each 3 bits from the second shift register,
a decoder that generates an operation instruction output according to the second-order Booth's algorithm; a partial product generator that performs an operation on the multiplicand according to the output of the decoder; A partial product is generated by shifting the second shift register by 2 bits, and the first . 2nd °...
... an adder that adds the partial product and each output of the holding unit for the sum of partial products up to the previous time and the carry holding unit; the carry holding unit that holds the carry generated by the addition and the holding unit for the addition result; be configured to have the following.

[Industrial Application Field] The present invention is applicable to multiplication circuits, especially microprocessors and DSPs.
In an arithmetic processing unit such as, the word length of the multiplier and multiplicand is 8
This invention relates to a multiplication circuit that is effective in executing multiplication instructions as long as ~32 bytes.

With the recent advances in LSI technology and the demand for faster computer systems, it has become necessary to perform multiplication in parallel operations with long word lengths, but this requires a huge amount of hardware, so it is necessary to reduce the number of adders. be.

[Conventional technology]

FIG. 8 shows the basic configuration circuit of a conventional multiplier.

This is given by the m-bit multiplicand A and the n-bit multiplier B (m
+n) This is a multiplication circuit that calculates the product of bits. In the figure, l
is the multiplicand register, 2 is the multiplier register, 3 is the decoder,
4 is a partial product generation circuit, and 5 is an adder.

Multiplication on a computer is similar to manual calculation, where each bit of the multiplicand and multiplier are multiplied to calculate partial products, and these are added to form a product. However, since the numbers handled are binary numbers, the partial products are If the bit is 1, it is the multiplicand itself, and if the bit of the multiplier is 0, it is all 0. Since this is nothing but AND logic, the partial product generating circuit 4 is specifically an AND gate.

In simple multiplication, when the multiplier is n bits, there are n partial products,
Therefore, n stages of partial product generating circuits 4 and adders 5 are provided, with each row of adders 5 serving as one stage.

An improvement on this is the second-order Booth algorithm, which calculates the partial product of each 2-bit multiplier, so only n / 2 stages are required. This process is performed by the decoder 3. be. That is, let the multiplier B be B=B, l B, . . . Bt B+, and write this in two's complement form as B=-B, l 211-1 + Σ B positive 2m-1. However, the number of bits (n) of multiplier B is an even number, and B.

= 0, the above formula is B = 'i: "-" (B t= + B t=.+
2Bzi, z)・2h, and the partial product Pp is Pr=(Bit ten Bz+.128zt, i)・A・22
Since the numbers in parentheses in the above equation are the three adjacent pintos of the multiplier B, the partial product will be as shown in the following table depending on this value (1 or O). However, in this table, 22" is divided (.

Table 1 This is the second-order Booth algorithm, and the decoder 3
is applied to the partial product circuit according to the value of the adjacent 3 bits of multiplier B.
Calculate ±A and ±2A. For details, if 0, O1+A
Then, 1+2A indicates a 1-bit left shift, -2A indicates a 1-bit left shift and complement operation, and -A indicates a complement operation.

[Problem to be solved by the invention]

Thus, in a multiplier, if the multiplier is n bits, n stages or n/2 stages of partial product and adder circuits are required, and this increases two-dimensionally as the number of bits of the multiplicand and multiplier increases. If an attempt is made to configure a multiplier with a long word length on one chip using this conventional method, there will be considerable restrictions on mounting other macro cells such as RAM and ROM on the same chip.

It is an object of the present invention to improve these points and provide a multiplier that can reduce the number of adders and has a small amount of hardware.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention. 11 is a shift register that stores the multiplicand A, 2 is a shift register that stores the multiplier B, and 13 is a Booth decoder. Further, 14 is a partial product generating section, and 16 is an adder column that adds the carry and the result of the previous round of addition. Further, 17 is a flip-flop that holds the addition result from the previous round, 8 is a flip-flop that holds carry, 19 is a shift register that stores product output data, and 20 is a shift register 11.19 and a flip-flop 17.18. This is a circuit that controls the

For simple multiplications that do not follow Booth's algorithm,
The decoder 13 is not necessary, and since the shift register 19 is for output and the same contents are in the flip-flop 17, this is also not necessarily necessary.

[Effect]

In multiplication, partial products are created between each 1 bit or 2 bits of the multiplier and the multiplicand, and the resulting partial products are added to obtain the product. In the present invention, this can be done by repeatedly using the same hardware. Execute.

That is, in the case of simple multiplication, the product of the first bit of the shift register 12 from the lower side and the contents of the shift register 11 is obtained by the partial product generating section 14, and this product is stored in the flip-flop 17. Next, shift registers 11 and 12 by one bit, calculate the product of the second bit from the lower side of the multiplier and the contents of shift register 11, and multiply this by the contents of flip-flop 1.
The adder 16 calculates the sum with the contents of 7. The carry generated at this time is stored in the flip-flop 18, and the addition result is stored in the flip-flop 17.

Next, shift registers 11 and 12 by one bit again, and shift the third bit from the lower side of the multiplier and shift register 11.
Find the product of this and the contents of the flip-flop 17.1
The adder 16 calculates the sum with the contents of 8. The carry generated at this time is stored in the flip-flop 18, and the addition result is stored in the flip-flop 17.

The same applies below. Once all the bits of the multiplier and the multiplicand have been multiplied, and the previous addition results and carries have been added, the multiplication is complete. The result is in flip-flop 17 and is retrieved via register 19.

When following the Booth algorithm, shift register 11
．． 12 shifts are 2 bits at a time.

The decoder 13 takes out each three bits from the shift register 12 and gives an operation instruction determined by these bits to the partial product component 14. The procedure for adding each partial product to the previous one and the carry is the same as above, and the multiplication result is taken out from the register 19.

In this way, in the present invention, the same hardware is used repeatedly to execute multiplication, so no matter how many multiplier bits there are, the number of repetitions increases and the hardware scale does not increase.

〔Example〕

FIG. 2 shows an embodiment of the second invention. Since the multiplicand A is m bits and the multiplier B is n bits, the shift register 11 is assumed to be m+n bits. Also, the shift register 12 is n+1
The B-t bits are set to 0, and the bits are shifted 2 bits at a time. Further, each of the partial product generation circuits 14 generates the corresponding bit A i (i*11+ 1+ !+
”' 1llill-1) and its one digit lower bit A
, -7 (this is used for left shift), and the 3 bits of multiplication B from decoder 13 (B z=*t+ B !i+l+
Using instructions according to Table 1 by Bzt), generate partial products according to the second-order Booth algorithm. Further, the adder group 16 includes a half adder HA and a full adder F as shown in the figure.
A, the relevant partial product bit and that of the previous time (
− cycle addition result) and carry are added. - The result of the previous addition is in flip-flop 17 and the carry is in flip-flop 18. The multiplication result is stored in the shift register 19.

Next, A=B=5.Multiply 0101 in binary D-AXB=2
5. Using 00011001 in binary as an example, the operation of this circuit will be explained in detail with reference to FIGS. 2 to 7.

When the multiplicand A1 and the multiplier B are as described above, 0 and 1 are stored in the shift registers 11 and 12 as shown in FIG.

The decoder 13 takes in B, B, B- of the multiplier B, and instructs the partial product circuit 14 to perform shift and complement operations according to Table 1 above. In this example, the partial product circuit is B□, 2Bat-+
Since Btt=010, +A therefore 0000010
yields 1. This is shown in FIG. Since the adder 16 currently has no carry or the addition result from the previous round, it produces the same addition result as the partial product.

The result of this addition is input to the flip-flop 17.

This state is shown in FIG. Shift registers 11 and 12 shift by 2 bits, so the contents become as shown in FIG. The bit positions vacated by this shift are filled with O's.

The decoder 13 outputs B as B, , *, B*i*+E3zi.
s Bt B+-010 and issues an instruction according to Table 1, and the partial product circuit 14 follows this to +A in this example.
=OOO10100. This time, since there is the addition result from the previous round, the adder 16 adds this to the partial product to produce the result shown (16 is 00010001, carry is output at the third bit from the right).

This partial product 00010001 and carry l are set in flip-flops 17 and 18 as shown in FIG.

Further, 2-bit shifts of shift registers 11 and 12 are performed, and their contents become as shown in the figure. Since all bits of the multiplier are 0, the partial products are all O's. This partial product is added to the contents of flip-flops 17 and 18, and the contents of adder 16 become <00011001 as shown. Carrie doesn't appear.

This addition result is set in the flip-flop 17, loaded into the shift register 19, and becomes the product output of D=AXB. Shift registers 11,12 are again shifted 2 bits. This state is shown in FIG. Since all bits of the multiplier are O, the partial product is all 0, and this is added to the contents of the flip-flops 17 and 18, and the addition result becomes 00011001 as shown (no change).

Since multiplier B is 4 bits, shift register 11.12
2-bit shift twice (if B is n bits, then n/2
Therefore, it is not necessary to shift the shift registers 11 and 12 by 2 bits in FIGS. 6 and 7.
However, the process of adding the carry generated in FIG. 5 in FIG. 6 and the process of transferring the addition result to the register 19 through the flip-flop 17 in FIG. 7 are necessary.

When the operation is stopped due to the completion of the calculation, the number of calculation steps can be determined by the number of bits of the 0 multiplier when the clock is stopped, so when the number of steps is reached, the clock supply is stopped. Therefore, control is easier if the shift registers 11 and 12 are shifted as many times as the required number of steps as in the illustrated embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, multi-bit multiplier multiplication can be performed with a small amount of hardware, especially partial product circuits and the number of adders, and it can be installed in a device with limited space such as an L-chip processor. It is extremely effective.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Figs. 3 to 7 are diagrams explaining the operation of Fig. 2, and Fig. 8 shows a conventional example. It is a block diagram. In FIG. 1, A is a multiplicand, B is a multiplier, 11.12 is a shift register, 14 is a partial product generator, 16 is an adder column, 17.
18 is a flip-flop.

Claims (1)

[Claims] 1. A first shift register (11) in which the multiplicand (A) is set, and a second shift register (12) in which the multiplier (B) is set.
), a partial product generation unit (14) that generates a partial product of the multiplier bits and the multiplicand, and a first, Holding unit (17) for the first, second, ... partial products of the second, ... bit and the multiplicand, and the sum of partial products up to the previous time, and a carry holding unit (18)
); an adder (16) for adding the respective outputs of the above-described additions; a carry holding section (18) for holding a carry generated in the addition; and an addition result holding section (17). 2. A first shift register (11) in which the multiplicand (A) is set and shifts 2 bits at a time, and a multiplier (B)
is set, and a second shift register (12) performs a two-bit shift, and a decoder (13) takes in each three bits from the second shift register and generates an operation instruction output according to the second-order Booth algorithm. , a partial product generation unit that performs an operation on the multiplicand according to the output of the decoder, and a partial product generation unit that generates a partial product while shifting the first and second shift registers by 2 bits, and generates a partial product between each 2 bits of the multiplier and the multiplicand. Adders that add the first, second, ... partial products and the respective outputs of the holding section (17) for the sum of partial products up to the previous time and the carry holding section (18), and holding the carry generated by the above addition. A multiplication circuit comprising: the carry holding section (18) for holding the addition result; and the addition result holding section (17).