JPH05224889A - Multiplier - Google Patents

Abstract

PURPOSE:To accelerate the arithmetic speed of a multiplier for successively adding partial products without increasing the number of adders. CONSTITUTION:By using a partial product circuit 105 for inputting a value shifting a multiplicand to a high order by one bit when the two bits of a multiplier are '10' for outputting the multiplicand when the two bits of the multiplier are '01' or '11' and for outputting '0' when the two bits of the multiplier are '00', a variable shifter 109 for selectably shifting the shift amount of one bit or two bits, sum of products register 107 for selecting the shift amount of one bit or two bits and AND circuit 110 for judging whether the two bits of the multiplier are '11' or not, a partial product is processed for the unit of one bit when the two bits of the multiplier are '11', and the partial product is processed for the unit of two bits when the two bits of the multiplier are '00', '10' or '01'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a cryptographic communication device. In particular, it relates to a multiplication device adopted in this device.

[0002]

2. Description of the Related Art In a cryptographic communication device using RSA encryption or the like, since four arithmetic operations such as multiplication are performed for encryption and decryption, it is necessary to execute integer multiplication at high speed by a small-scale circuit. There are various methods of multiplication, but in the cryptographic communication device, for example, since it is necessary to multiply an integer of 512 bits or 1024 bits, a partial product of 1 bit of the multiplier and the multiplicand is sequentially obtained, It is common to find the sum. It should be noted that when a partial product is obtained and multiplied in 1-bit units, an L-bit multiplier X = (X _L-1 , X _L-2 ,
, X ₁ , X ₀ ) and multiplicand Y = (Y _L-1 , Y _L-2 , ...,
Y ₁ , Y ₀ ) multiplication result Z = (Z _2L-1 , Z _2L-2 , ...,
Z ₁ , Z ₀ ) is obtained by the operation of the following equation.

[0003]

[Equation 1] However, in the above formula, * represents an integer multiplication. Since doubling a binary integer is nothing more than shifting the integer by 1 bit toward the upper bits, the operation of the above equation can be rewritten as a sequential operation such as the following equation. In the following equation, A >> B means that A is shifted by B bits toward the lower bit, and the operation is repeated from j = 0 to j = L−1 with the initial state of Z being “0”. To do. In addition, the addition of partial products is performed by using the upper bit (Z
_2L-1, ..., shall be made with respect to Z _L).

In the case of X _j = 0: Z = Z >> 1 In the case of X _j = 1: Z = (Z >> 1) + Y As shown in the above equation, partial products are obtained bit by bit and the sum thereof is obtained. Since multiplication requires only addition and shift, it is easy to implement as a device.

FIG. 5 is a functional block diagram showing a conventional multiplication device. As shown in the figure, the multiplier is input from the input terminal 501 and held in the multiplier register 502. The lower 1 bit of the multiplier held in the multiplier register 502 is supplied to the AND circuit 505, and the multiplier held in the multiplier register 502 is shifted by 1 bit in the lower direction each time the operation proceeds by one step. The multiplicand is supplied from the input terminal 503 and held in the multiplicand register 504, and the multiplicand held in the multiplicand register 504 is the AND circuit 505.
Is supplied to. The AND circuit 505 is a multiplicand register 50.
The logical product of each bit of the multiplicand supplied from 4 and 1 bit of the multiplier supplied from the multiplier register 502 is calculated, and the result is output. Sum of products register 5
Reference numeral 07 is a register for holding the multiplication result, the held contents are supplied to the 1-bit shifter 509, the outputs of the 1-bit shifter 509 and the logical product circuit 505 are added by the adder 506, and the addition result is stored in the product-sum register 507. Is being supplied. The product-sum register 507 records the addition result supplied from the adder 106 every time the multiplication proceeds by one step, and is shifted in the lower direction. Then, the multiplication result obtained in the product sum register 507 is output from the output terminal 508. The control circuit 511 outputs the control signals necessary for executing the above operations to the multiplier register 502, the multiplicand register 504, the sum of products register 507, and the input terminal 5.
01, 503 and the output terminal 508,
For example, it can be realized by sequentially reading the contents of the read-only memory in which the pattern of the control signal is written in advance by the counter.

[0006] Incidentally, the cryptographic communication system such as the RSA cryptosystem is
This is a method of encrypting information by four arithmetic operations, for example, 14 of bit 23, No. 10, issued in 1991.
Okamoto, “Cryptographic Technologies Aiming at Realization of a Bright Information Society,” from 23 to 1432 Cryptographic Algorithms (2)-
Asymmetric (public key) cryptographic algorithms "and so on.

[0007]

However, the sequential multiplication performed in the conventional example has a drawback that the operation speed is slow because the partial product is obtained bit by bit.

An object of the present invention is to provide a multiplication device which has the same number of adders as the conventional multiplication device and is faster than the conventional multiplication device.

[0009]

According to the present invention, there is provided a multiplication device comprising a multiplier register for holding a multiplier, a multiplicand register for holding a multiplicand, and an output terminal through which a multiplication result of the multiplicand and the multiplier passes. When the lower 2 bits of the multiplier held in the multiplier register are [10], a value obtained by shifting the multiplicand held in the multiplicand register by 1 bit to the upper side is output, and the lower 2 bits of the multiplier are [01 ] Or [11], this multiplicand is output, and when the lower 2 bits of this multiplier are [00], a partial product circuit and the lower of the multiplier held in the multiplier register are output. An AND circuit that determines whether or not 2 bits are [11], and a value that is supplied is shifted by 1 bit or 2 bits in accordance with the output of the AND circuit, and is retained, and the retained value is retained. A sum-of-products register to be supplied to the output terminal, a variable shifter for shifting the value supplied from the sum-of-products register by 1 bit or 2 bits according to the output of the AND circuit, and an output of the variable shifter. And an adder for adding the output of the partial product circuit and supplying the result to the product-sum register.

Here, in the partial product circuit, the 1-bit shifter connected to the output of the multiplicand register and the upper bit of the 2 bits of the multiplier held by the multiplier register are connected to one input of the multiplier. A first AND circuit having an inverted output of the lower bit of the two bits connected to the other input; a second AND circuit for receiving the output of the 1-bit shifter and the output of the first AND circuit; A third AND circuit for inputting the output of the multiplicand register and the lower bit of the 2 bits of the multiplier held by the multiplier register, the output of the second AND circuit and the output of the third AND circuit An OR circuit that inputs and outputs the output to the variable shifter may be provided.

[0011]

The present invention improves the operation speed by obtaining the partial product in units of 2 bits instead of in units of 1 bit. Here, when the partial product is calculated in units of 2 bits and multiplied, the L-bit multiplier X = (X _L-1 , X _L-2 , ..., X ₁ , X ₀ ) and the multiplicand Y = (Y _L-1 , Y _L-2 , ..., Y ₁ , Y ₀ ) and the multiplication result Z = (Z _2L-1 , Z _2L-2 , ..., Z ₁ , Z ₀ ) are calculated by the following formula. is there. However, in the following equation, [X
_{2j + 1} X _2j ] is a 2-bit integer configured by 2j + 1th bit and 2jth bit of the multiplier X, 2 bits in total, and * represents multiplication of integers. Further, for convenience of explanation, it is assumed that L is divisible by 2.

[0012]

[Equation 2] Now, [00] * Y = 0, [01] * Y = Y,
Since [10] * Y is nothing more than shifting the multiplier Y to the upper bit by one bit, the operation of the above equation can be rewritten as a sequential operation such as the following equation. In the following equation, A << B means that A is shifted to the upper B bits by A
>> B means that A is shifted to the lower B bits, respectively, and the initial state of Z is "0", and j = 0 to j = L /
The operation is repeated up to 2-1. Further, the addition of partial products shall be performed on the upper bits of Z (Z _2L-1 , ..., Z _L ).

When [X _{2j + 1} X _2j ] = 00: Z = Z >> 2 When [X _{2j + 1} X _2j ] = 01: Z = (Z >> 2) + Y [X _{2j + 1} X _2j ] = 10: Z = (Z >> 2) +
(Y << ₁ ) [X _{2j + 1} X _2j ] = 11: Z = (Z >> 2) +
(Y << 1) + Y However, the calculation speed cannot be improved by simply obtaining the partial product for each 2 bits. That is, as shown in the above equation, when both 2 bits of the multiplier are "1", two additions are required, but if this is processed using two adders, it becomes 1
The processing time per step is approximately doubled.

Therefore, in the present invention, the partial product is not calculated for each 2 bits, but the partial product is processed for each 1 bit when both 2 bits of the multiplier are "1", and otherwise. Process partial products by 2 bits. That is, multiplication is performed in the following procedure. In the following equation, it is assumed that the initial state of Z is “0” and the operation is repeated from j = 0 to j = L / 2−1. Further, the addition of partial products shall be performed on the upper bits (2 _2L-1 , ..., Z _L ) of Z.

When [X _{2j + 1} X _2j ] = 00: Z = Z >> 2 When [X _{2j + 1} X _2j ] = 01: Z = (Z >> 2) + Y [X _{2j + 1} X _2j ] = 10: Z = (Z >> 2) +
(Y << ₁ ) [X _{2j + 1} X _2j ] = 11: Z = (Z >> 1) + Y
Is executed twice, that is, when 2 bits of the multiplier are [11], the process is divided into two steps. In the procedure like the above equation, since the number of times of addition is 1 in every step, the time required for the processing of one step is 2 steps to calculate the partial product of 2 bits in the method of obtaining the partial product in 1-bit units. Whereas required, the procedure in the above equation requires only (1 + 1 + 1 + 2) /4=1.25 steps on average. Therefore, the operation speed of the multiplication device of the present invention based on the above equation is 2 / 1.25 = 1.6 times faster on average than the conventional method of obtaining the partial product bit by bit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram showing this embodiment.
In this embodiment, as shown in FIG. 1, a multiplier register 102 holding a multiplier and a multiplicand register 1 holding a multiplicand.
04, and an output terminal 108 through which the multiplication result of this multiplicand and this multiplier passes. Furthermore, as a feature of the present invention, the lower 2 bits of the multiplier held in the multiplier register 102 are [10]. Multiplicand register 10
A value obtained by shifting the multiplicand held in 4 to the upper bit by 1 bit is output, and the lower 2 bits of this multiplier are [01] or [1
1], the multiplicand is output, and when the lower 2 bits of this multiplier are [00], the partial product circuit 105 and the lower 2 bits of the multiplier held in the multiplier register 102 are output. AND circuit 110 that determines whether or not is [11], and the supplied value is the above-mentioned AND circuit 110.
1-bit or 2-bit after being shifted according to the output of the above, and the held value is supplied to the output terminal 108, and the value supplied from this product-sum register 107 Variable shifter 10 that shifts by 1 bit or 2 bits according to the output of 110 and outputs the result.
9, the output of the variable shifter 109 and the partial product circuit 105
And the output of the adder 106 and add the result to the sum of products register 107.

Next, the operation of this embodiment will be described. The multiplier is input from the input terminal 101 and held in the multiplier register 102. Of the multipliers held in the multiplier register 102, the lower 2 bits are the logical product circuit 110 and the partial product circuit 105.
And the multiplier held in the multiplier register 102 is shifted by 2 bits in the lower direction every time the processing of 2 bits of the multiplier is completed. The multiplicand is supplied from the input terminal 103 and held in the multiplicand register 104, and the multiplicand held in the multiplicand register 104 is supplied to the partial product circuit 105. The partial product circuit 105 calculates a partial product of the multiplicand supplied from the multiplicand register 104 and 2 bits of the multiplier supplied from the multiplier register 102, and outputs the result. However, as described above, since the partial product is processed bit by bit when 2 bits of the multiplier are [11], the partial product is processed by 2 bits otherwise, so the partial product circuit 105 Is "00 ... 0" when 2 bits of the multiplier is [00], a value obtained by shifting the input by 1 bit in the upper direction when 2 bits of the multiplier is [10], and 2 bits of the multiplier is [01 ] Or [11], the input values are output respectively. The product-sum register 107 is a register for holding the multiplication result, the held contents are supplied to the variable shifter 109, the outputs of the variable shifter 109 and the partial product circuit 105 are added by the adder 106, and the addition result is multiplied. It is supplied to the sum register 107. The product-sum register 107 is provided with an adder 10 for each multiplication step.
The addition result supplied from 6 is recorded and is shifted in the lower direction. Then, the multiplication result obtained in the product-sum register 107 is output from the output terminal 108. In addition,
As described above, when the 2 bits of the multiplier are [11], the partial product is processed bit by bit, and otherwise, 2 is used.
Since the partial product is processed bit by bit, the variable shifter 109
Outputs a value obtained by shifting the input by 2 bits in the upper direction when the 2 bits of the multiplier are [00], [01], and [10], and outputs 1 when the 2 bits of the multiplier is [11].
It is necessary to output a value shifted in the upper direction by bits, and the product-sum register 107 outputs 2 bits in the lower direction for each step when the 2 bits of the multiplier are [00], [01], and [10]. When the 2 bits of the multiplier are [11], it is necessary to shift one bit in the lower direction for each step. Therefore, the output of the AND circuit 110 is the sum of products register 107 and the variable shifter 10.
When the output of the AND circuit 110 is "0", the variable shifter 109 outputs a value obtained by shifting the input by 2 bits in the upper direction, and the output of the AND circuit 110 is "1". In the case of, a value obtained by shifting the input by 1 bit in the upper direction is output, and the product-sum register 107 outputs the logical product circuit 1
When the output of 10 is "0", it is shifted by 2 bits in the lower direction for each step, and when the output of the AND circuit 110 is "1", it is shifted by 1 bit in the lower direction for each step. .. The control circuit 111 selects "1" or "2" as the number of control signals to be supplied to the sum-of-products register 107 according to the output of the AND circuit 110 and that the number of generated control signals is different. Is different from the control circuit 511 used in the conventional multiplier, and the other functions are the same as those of the control circuit 511 used in the conventional multiplier, and the control signal necessary for executing the above operation is multiplied by the multiplier. Register 102, multiplicand register 104, sum of products register 10
7, the input terminals 101 and 103, and the output terminal 108.

FIG. 2 is a functional block diagram showing the basic configuration of the partial product circuit 105 used in the multiplication device of FIG. As shown in the figure, from the input terminal 201, the multiplicand register 1
The multiplicand held in 04 is input, and the 1-bit shifter 2
02 and the AND circuit 204. Input terminal 20
The higher-order bit of 2 bits of the multiplier output from the multiplier register 102 is input from 7 and the AND circuit 208
Is supplied to. Multiplier register 10 from input terminal 210
The lower bit of the 2 bits of the multiplier output from 2 is input and supplied to the NOT circuit 209 and the AND circuit 204. The output of the NOT circuit 209 is supplied to the AND circuit 208. The logical product circuit 208 calculates the logical product of the output of the NOT circuit 209 and 1 bit of the multiplier supplied from the input terminal 207, and supplies the result to the logical product circuit 203.
The 1-bit shifter 202 shifts the input numerical value in the upper direction by 1 bit and outputs it, and is actually realized by wiring and does not require a logic circuit. The logical product circuit 203 calculates the logical product of each bit of the output of the 1-bit shifter 202 and the output of the logical product circuit 208, and supplies the result to the logical sum circuit 205. The logical product circuit 204 calculates the logical product of each bit of the multiplicand supplied from the input terminal 201 and 1 bit of the multiplier supplied from the input terminal 210, and supplies the result to the logical sum circuit 205. The logical sum circuit 205 calculates the logical sum for each bit of the outputs of the logical product circuit 203 and the logical product circuit 204, and outputs the result from the output terminal 206. The output of the logical product circuit 208 becomes "1" only when the multiplier supplied from the input terminals 207 and 210 is [10]. Therefore, the partial product circuit of FIG.
When the multiplier is [10], a value obtained by shifting the multiplicand supplied to the input terminal 201 by 1 bit in the upper direction is output from the output terminal 206, and when the multiplier is [00], it is "0".
0 ... 0 ”is output from the output terminal 206, and in other cases, the input multiplicand is output as it is. Incidentally, in the method of always processing the partial product by 2 bits, the partial product circuit needs the adder, but in the present invention, the partial product is processed by 1 bit when the multiplier is [11]. Moreover, a partial product circuit can be realized without using an adder.

FIG. 3 is a functional block diagram showing the basic structure of the variable shifter 109 used in the multiplication device of FIG. As shown in FIG.
It is input from 01 and supplied to the 2-bit shifter 302 and the 1-bit shifter 303, respectively. Input terminal 30
The output of the AND circuit 110 is input from 6 and supplied to the selector 304. The 2-bit shifter 302 shifts the input numerical value by 2 bits in the upper direction and outputs it, and is actually realized by wiring and does not require a logic circuit. The 1-bit shifter 303 shifts the input numerical value by 1 bit in the upper direction and outputs it, and is actually realized by wiring and does not require a logic circuit. The selector 304 outputs the output of the 1-bit shifter from the output terminal 305 if the output of the AND circuit 110 is “1”, and the 2-bit shifter 3 if the output of the AND circuit 110 is “0”.
02 is output from the output terminal 305.

The multiplication device shown in FIG. 1 may hold all intermediate results of operations, that is, all Z values in the product-sum register 107. However, in order to save the circuit scale of the product-sum register 107, the output Sum-of-products register 10 from terminal 108
The contents of 7 may be output in order from the lower bit, and the operation result may be transferred to an external storage device while performing the operation. However, in this embodiment, since the partial product is processed in units of 2 bits or 1 bit in accordance with the value of the multiplier, it is not possible to simply output the lower 2 bits of the product sum register 107 from the output terminal 108 to the storage device. Can't transfer correctly.

FIG. 4 is a function showing a basic configuration of an interface circuit for adjusting data signals and control signals between the multiplication device and the storage device of FIG. 1 in order to transfer the operation result to the storage device while performing the operation. It is a block diagram. As shown in the figure, the value of the least significant bit of the product sum register 107 is input from the input terminal 402 and supplied to the delay circuit 405, the selector 408 and the selector 409, and the value of the second least significant bit of the product sum register 107 is set. It is input from the input terminal 401 and supplied to the selector 408. The control signal of the control circuit 111 is input from the input terminal 403 and supplied to the delay circuits 405 and 406 and the logical sum circuit 410. This control signal is also supplied to the sum-of-products register 107, and is normally "1". When the contents of the sum-of-products register 107 are shifted, a pulse is generated which becomes "0" and returns to "1" again. .. When the output of the logical product circuit 110 is "0", one pulse is generated to process the 2-bit multiplier, and when the output of the logical product circuit 110 is "1", a pulse of 2 bits is generated. Two pulses are generated to process the multiplier. The output of the logical product circuit 110 is input from the input terminal 404 and supplied to the delay circuit 406, the selector 408, the selector 409, and the logical product circuit 411. If the value of the AND circuit 110 supplied from the input terminal 404 is “0”, the selector 408 selects the value supplied from the input terminal 401 as its output, and if the value of the AND circuit 110 is “1”. For example, the value supplied from the input terminal 402 is selected as the output, and the output of the selector 408 is output from the output terminal 412. If the value of the AND circuit 110 supplied from the input terminal 404 is “0”, the selector 409 selects the value supplied from the input terminal 402 as its output, and if the value of the AND circuit 110 is “1”. For example, the output of the delay circuit 405 is selected as the output, and the output of the selector 409 is the output terminal 4
It is output from 13. The delay circuit 405 has an input terminal 40.
Each time a pulse is supplied from 3, the value of the input terminal 402 is held as its output. Output terminal 412 and output terminal 4
13 is connected to the output terminal 108. In this way, when the output of the AND circuit 110 is “0”, the lower 2 bits of the product-sum register 107 are directly output from the output terminal 108, while the output of the AND circuit 110 is “1”.
In the case of 1, the lower 2 bits of the product-sum register 107 are output to the output terminal 108 after one pulse is input from the input terminal 403.

Next, pulse control for controlling writing in the memory device connected to the output terminal 108 will be described. In the interface circuit shown in FIG. 4, the delay circuit 4
Each time a pulse is input from the input terminal 403 to 06, the output of the AND circuit 110 supplied from the input terminal 404 is held as the output of the delay circuit 406. Then, the output of the delay circuit 406 is inverted by the negation circuit 407, and the negation circuit 4
A logical product circuit 411 obtains a logical product of the output of 07 and the output of the logical product circuit 110 supplied from the input terminal 404. The output of the AND circuit 411 is "1" immediately after the output of the AND circuit 110 becomes "1" until a pulse is input from the input terminal 403, and is "0" otherwise. Then, the logical sum of the control signal supplied from the input terminal 403 and the output of the logical product circuit 411 is the logical sum circuit 410.
And the result is output from the output terminal 414. Therefore, when the output of the AND circuit 110 is "1", the input terminal 403 is used to process the 2-bit multiplier.
There are two pulses from, but the first pulse is output terminal 41.
Only the second pulse is output without being output from 4.
Therefore, if the output terminal 414 is input to the write control terminal of the storage device, the lower 2 bits of the sum-of-products register 107 are correctly transferred to the storage device.

In the multiplication device shown in FIG. 1, data transfer from the input terminal 101 to the multiplier register 102, data transfer from the input terminal 103 to the multiplicand register 104, and data transfer from the sum-of-products register 107 to the output terminal 108. Although the transfer is performed serially, the data transfer speed can be improved by dividing each register into a plurality of blocks and performing serial data transfer to each register in parallel. Further, the multiplication device shown in FIG. 1 has a built-in multiplier register 102, but the multiplier register 102 is not necessary if 2 bits of the multiplier are read from an external storage device and supplied to the AND circuit 110 and the partial product circuit 105. become. Any adder can be used as the adder 106.

[0024]

As described above, the present invention has the effect of realizing a multiplication device 1.6 times faster than the conventional multiplication device without increasing the number of adders.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a partial product circuit included in FIG.

FIG. 3 is a block configuration diagram showing a configuration of a variable shifter included in FIG. 1.

FIG. 4 is a block configuration diagram showing a configuration of an interface between the embodiment of the present invention and a storage device.

FIG. 5 is a block configuration diagram showing a configuration of a conventional example.

[Explanation of symbols]

 102 Multiplier register 104 Multiplicand register 105 Partial product circuit 106 Adder 107 Sum of products register 109 Variable shifter 110 Logical product circuit 111 Control circuit

Claims (2)

[Claims] 1. A multiplier device having a multiplier register for holding a multiplier, a multiplicand register for holding a multiplicand, and an output terminal through which a multiplication result of this multiplicand and this multiplier passes, wherein the multiplier register is held. When the lower 2 bits of the multiplier is [10], a value obtained by shifting the multiplicand held in the multiplicand register by 1 bit to the upper side is output, and when the lower 2 bits of the multiplier is [01] or [11] This multiplicand is output to and the lower 2 bits of this multiplier are [0
A partial product circuit that outputs “0” when the value is 0], an AND circuit that determines whether the lower 2 bits of the multiplier held in the multiplier register is [11], and a value that is supplied. Is shifted by 1 bit or 2 bits according to the output of the logical product circuit and held, and the held value is supplied to the output terminal, and the value supplied from the product sum register A variable shifter that shifts the output by 1 bit or 2 bits according to the output of the product circuit, and an adder that adds the output of the variable shifter and the output of the partial product circuit and supplies the result to the product-sum register. And a multiplication device. 2. The partial product circuit has a 1-bit shifter connected to the output of the multiplicand register and an upper bit of 2 bits of the multiplier held by the multiplier register connected to one input of the multiplier. A first AND circuit to which the inverted output of the lower bit of the bits is connected to the other input; a second AND circuit which inputs the output of the 1-bit shifter and the output of the first AND circuit; and the multiplicand Input the output of the register and the lower bit of the 2 bits of the multiplier held by the multiplier register, the output of the second AND circuit and the output of the third AND circuit 3. A multiplication device according to claim 1, further comprising a logical sum circuit for providing its output to the variable shifter.