JPH04148231A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce the number of operation steps at the time of accumulation, and to attain the high speed arithmetic processing by inputting the output of an arithmetic computing element to a register circuit after shifting it in a prescribed direction by a selector with a program instruction. CONSTITUTION:The output of the arithmetic computing element 27 is selected at every n-bits based on the program instruction, and the result of this selection is inputted to the prescribed input bit position of the register circuit 31. Namely, the selectors 28 to 30 are switched by the program instruction, and n-bits of the output of the arithmetic computing element 27 are inputted to the register circuit 31 after being shifted in the prescribed direction. Thus, the number of the operation steps at the time of the accumulation is reduced, and the high speed operation can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic circuit provided in a digital signal processor or the like.

(Prior art) Conventionally, as a technology in this field, for example, ANAL
OG DEVICES Catalog “ADSP-210
0 User's Manual" (1986) P, 20-
There was something described in 27.

The configuration will be explained below using figures.

FIG. 2 is a block diagram showing an example of the configuration of a conventional arithmetic circuit.

This arithmetic circuit is connected between an input data path 1.2 and an output data bus 3, and the input data buses 1, 2 include
A multiplication block consisting of a register 4.5 and a 16-bit parallel multiplier 6 is connected. This multiplication block contains
A 40-bit adder/subtractor 7 for accumulation is connected, and a 40-bit register circuit 11 is further connected to its output side via selectors 8-10. Register circuit 11
is composed of a lower 16-bit register 11-2, an upper 16-bit register 11-1, and an upper extended 8-bit register 11-0. Register circuit #111 is connected to input data bus 2 via selector 12 and output buffer 16, and is connected to output buffers 13 to 15.
It is connected to the output data bus 3 via.

In the above configuration, the input data path 1.2 to 16
The bit parallel data enters the register 4.5 and is input to the input terminals XI and YI of the multiplier 6. The 32-bit product multiplied by the multiplier 6 is output from the output terminal P, input to the adder/subtracter 7, and added to/subtracted from the data in the register circuit 11. In addition, input terminals XI and YI of the multiplier 6 are provided so that data exceeding 16 bits can be multiplied.
can accept data in two's complement or binary format. This allows two's complement multiplication, mixed binary and two's complement multiplication, and binary multiplication to be performed based on program instructions.

Here, we will consider multiplication between 32-bit lengths exceeding 16 bits. Normally, even if 32 bits are multiplied, only the upper 32 bits of the multiplication result are often needed because this operation is used for the next operation. Therefore, consider obtaining a 32-bit output by multiplying these 32 bits together.

For example, 32 bits of data X (lower 16 bits of
O, the upper 16 bits of X
), perform xxy=z.

FIG. 3 is a diagram showing a 32-bit multiplication method using a 16-bit parallel multiplier. As shown in this figure, first, the lower 16 bits of data X and Y are multiplied by xoxyo, and the result is multiplied by
Store in 2. Then, the data in the register 11-1 is transferred to the register 11-2 via the selector 12, the output buffer 16, the input data bus 2, and the selector 10,
Similarly, data in register 11-0 is transferred to register 11-1 (16-bit right shift operation).

Next, the upper bits Xi, Yl of data X, Y are multiplied by the lower bits xo, yo alternately (XIXYO).

X0XYI>, and this multiplication result and register circuit 11
The data within is accumulated by the adder/subtractor 7. Thereafter, similarly to the 16-bit right shift operation described above, the data in register 11-1 is transferred to register 11-2, and the data in register 11-0 is transferred to register 11-1. Finally, data X,
The upper bits X1 and Yl of Y are multiplied, and the result of this multiplication and the data in the register circuit 11 are accumulated by the adder/subtractor 7, and the operation is completed. This calculation result is transferred to a memory or the like via the output data bus 3.

(Problem to be Solved by the Invention) However, in the arithmetic circuit with the above configuration, when performing 32-bit multiplication using the 16-bit parallel multiplier 6,
A bit right shift operation is required, and for this operation the contents of register B11 must be moved via the input data bus 2, which increases the number of calculation steps and increases the calculation speed. It was difficult.

The present invention provides an arithmetic circuit that solves the problem of the prior art, which is that it is difficult to increase the arithmetic speed due to the increase in the number of arithmetic steps.

(Means for Solving the Problem) In order to solve the problem, the present invention provides an n×n multiplier that multiplies two pieces of input data of fixed bit length n (where n is a positive integer); An operation comprising an arithmetic operation unit provided on the output side of a multiplier and having a bit length longer than 20 bits, and a register circuit provided on the output side of the arithmetic operation unit and temporarily storing data of the same bit length as the arithmetic operation unit. The circuit is provided with a selector that selects the output of the arithmetic operation unit every n bits based on a program instruction and inputs the selection result to a predetermined input bit position of the register circuit.

(Operation) According to the present invention, since the arithmetic circuit is configured as described above, the selector is switched by a program instruction, and the output of the arithmetic operation unit is shifted by n bits in a predetermined direction and input to the register circuit. This reduces the number of calculation steps during accumulation. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration block diagram of an arithmetic circuit showing an embodiment of the present invention.

This arithmetic circuit is connected between an input data path 21.22 and an output data path 23, and is connected between the input data bus 21.22 and the output data path 23.
22 is connected to registers 24 and 25. The output terminals of registers 24 and 25 are connected to 16-bit parallel multiplier 2.
6 input terminal XI.

XI respectively, and the output terminal of the multiplier 26 is connected to one input terminal of a 40-bit arithmetic operation unit 27 for accumulation.

The arithmetic operation unit 27 is composed of an adder/subtractor or an arithmetic logic unit (ALU), and has output terminals R2, R1,
The RO is connected together with the input data bus 22 to the input terminals of the two-man power one-output selector 28 and the three-man power one-output selector 29,30. That is, the output terminal R2 is the input terminal of the selector 28, 29, and the output terminal R1 is the input terminal of the selector 29.
．． ．． The output terminal RO is connected to the input terminal of the selector 30, and the input data bus 22 is connected to the input terminal of each of the selectors 28-30.

The selectors 28 to 30 are circuits that select one of the inputs according to a program instruction, and have 40 output terminals at their output terminals.
A bit register circuit 31 is connected. The register circuit n31 is composed of a lower 16-bit register 31-2, an upper 16-bit register 31-1, and an upper extended 8-bit register 31-0. register 3
The output terminals 1-0 to 31-2 are commonly connected to the other input terminal of the arithmetic operation unit 27, and are further connected to the input data bus 32 via a selector 32 and an output buffer 36 with three outputs that are switched by a program command. and to the output data path 23 via output buffers 33, 34 and 35. Output buffers 33-36
consists of a tri-state buffer whose output is controlled by program instructions.

FIG. 4 is a circuit diagram showing an example of the configuration of the selector 28 with two human power and one output in FIG. 1, and FIG.
FIG. 3 is a circuit diagram showing a configuration example of a selector 29.30 with one output of human power.

The selector 28 in FIG. 4 includes an inverter 41.2 a manual AND gate (hereinafter referred to as an AND gate) 42.43,
and a two-person OR gate (hereinafter referred to as OR gate) 4
It is composed of 4. In this selector 28, when the control signal C is at the "H'° level, the signal at the input terminal INI is output to the output terminal OUT, and when the control signal C is at the "L°" level, the signal at the input terminal INO is output to the output terminal. Output to OUT. Selectors 29, 30 in FIG. 5 are connected to inverters 51, 52, 53, 54.
56, 57, and a three-man OR gate 58,
When the control signals C1 and C2 are at "L" level, the input terminal I
A NO signal is output to the output terminal OUT. Control signal C
When 1 = "H" level and C2 = it L e+ level, the signal of the input terminal INI is output to the output terminal OUT, and when C1 = "°L'° level" and C2 = "H" level, the signal of the input terminal IN2 is outputted to the output terminal OUT. The signal is output to the output terminal OUT.

The operation of the arithmetic circuit configured as described above will be explained using an example of multiplication between 32-bit lengths exceeding 16 bits.

For example, two data X (lower 16 bits of X
xxy=z by the upper 16 bits of Y
I do.

As shown in FIG. 3, first, the lower 16 bits xo and yo of data X and Y are stored from the input data bus 21.22 to the register 24.25. and both registers 24
．． The output from 25 is input to a multiplier 26, and the multiplier 26
Multiply by . This multiplication result passes through the arithmetic operator 27 and is sent to the selectors 28-30. At this time, the selector 2 is controlled by the control signals C1 and C2 based on the program command.
9. The signal output from the output terminal R1 of the arithmetic operation unit 27 is input to the register 31-2 through the 9°30, and the signal output from the output terminal R2 is input to the register 31-1.
Store (16-bit right shift operation).

Next, the upper 16 bits X1 of data X and the lower 16 bits YO of data Y are stored from the input data bus 21.degree. 22 into registers 24.25. And both registers 24.2
5 is multiplied by the multiplier 26, and the arithmetic operation unit 27 accumulates the contents of the registers 310 to 31-2 and the multiplication result. In the arithmetic operation unit 27, the output signal from the output terminal RO is sent to the register 31-2 via the selector 30.
The output signal from the output terminal R1 is stored in the register 31-1 via the selector 29, and the output signal from the output terminal R2 is stored in the register 31-0 via the selector 28.

The lower 16 bits XO of data X and the upper 16 bits Y1 of data Y are transferred from the input data path 21.
4.25. The outputs from both registers 24 and 25 are multiplied by a multiplier 26, and an arithmetic operator 27 accumulates the multiplication results and the contents of registers 31-0 to 31-2.

The selectors 29 and 30 are switched by control signals C1 and C2 based on the instruction program, and the output signal from the output terminal R1 of the arithmetic operation unit 27 is sent to the register 31-2, and the output signal from the output terminal R2 is sent to the register 31-1. , respectively (16-bit right shift operation).

After the 16-bit right shift operation, the upper 16 bits X1 of data X and the upper bit Y1 of data Y are input to data path 21.
．． 22 to registers 24 and 25. Then, the multiplier 26 multiplies the outputs from both registers 24 and 25, and the arithmetic operator 27 multiplies the outputs from the registers 31-0 to 31-0.
Accumulate the contents of 1-2 and the multiplication results. The output signal from the output terminal RO of the arithmetic operator 27 is sent to the register 31-2 via the selector 30, the output signal from the output terminal R1 is sent to the register 31-1 via the selector 29, and the output signal from the output terminal R2 is sent to the register 31-2. is the register 31-0 via the selector 28.
are stored respectively. This completes the calculation, and the result of the calculation is transferred to a memory or the like via the output buffers 33 to 35 and the output data path 23.

In this way, in this embodiment, when performing a 16-bit right shift operation, the control signals C1 and C2 based on the instruction program are
As a result, the output of the arithmetic operator 27 can be shifted to the right by 16 bits via the selectors 29 and 30, so the number of calculation steps can be reduced, thereby speeding up the calculation process.

Note that the present invention is not limited to the above-mentioned embodiments, and the number of bits to be processed by an operation may be set to a number other than 16 bits, and the number of bits processed by the multiplier 26, the arithmetic operator 27, etc. may be changed accordingly, or the number of bits processed by the selector 28 may be changed accordingly. Various modifications are possible, such as configuring 30 with circuits other than those shown in FIGS. 4 and 5.

(Effects of the Invention) As described in detail above, according to the present invention, the output of the arithmetic operation unit is shifted by n bits in a predetermined direction using a selector according to a program instruction, and is input to the register circuit. The number of calculation steps can be reduced during accumulation,
Computation processing can be accelerated. Furthermore, if double-precision arithmetic operations used in audio processing and the like are executed using the present invention, it is expected that the number of arithmetic steps will be reduced and the processing speed will be increased thereby.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of an arithmetic circuit showing an embodiment of the present invention, FIG. 2 is a configuration block diagram of a conventional arithmetic circuit, and FIG. 3 is a diagram explaining a 32-bit multiplication method using a 16-bit parallel multiplier. FIG. 4 is a circuit diagram of the two-man power one output selector shown in FIG. 1, and FIG. 5 is a circuit diagram of the three-man power one output selector shown in FIG. 26... Multiplier, 27... Arithmetic operator. 28...
2 human power 1 output selector, 29. 30... 3 human power 1 output selector, 31... register circuit, 31-0 to 3
1-2...Register.

Claims (1)

[Claims] An n×n multiplier that multiplies two input data of fixed bit length n (where n is a positive integer), and a multiplier provided on the output side of the multiplier that has a bit length longer than 2n bits. an arithmetic operator;
In an arithmetic circuit that is provided on the output side of the arithmetic operator and includes a register circuit that temporarily stores data of the same bit length as the arithmetic operator, the output of the arithmetic operator is selected every n bits based on a program instruction. An arithmetic circuit comprising a selector for inputting the selection result to a predetermined input bit position of the register circuit.