JPS58115544A - Arithmetic device - Google Patents

Abstract

PURPOSE:To prevent the inversion of the sign of a maximum value and to resolve the hunting or the like, by storing the maximum value having a proper sign in an independent register on a basis of signs and types of data in two registers when the overflow is generated in an operation. CONSTITUTION:When the overflow due to the operation is generated, signals indicating signs of data in a register A1 3 and a register B1 4 and a signal indicating the type of the operation from an instruction decoder 2 are inputted to a discriminator 6. A signal indicating that the signal of the operation result is a positive or negative number is outputted to an excess value controlling circuit 51, and a positive or negative maximum value setting signal is outputted to an operator 1, and an internal overflow flag register is set. The operator 1 stores a positive or negative maximum value in a register A0 on a basis of the positive or negative maximum value setting signal from the excess value controlling circuit 51. Consequently, when data in registers 3 and 4 are positive together and the operation command from the instruction decoder 2 indicates addition and the overflow is generated, the positive maximum value is stored in the register A0 of the operator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic device that automatically corrects an arithmetic result to an appropriate value when an overflow occurs in an arithmetic unit.

A conventional device of this type is shown in FIG. In the figure, (1) is an arithmetic unit, (2) is an instruction decoder that gives arithmetic instructions (addition, multiplication, division, etc.) to the arithmetic unit (1),
(3) is a register that takes in the operation result (hereinafter referred to as register ~ data) of arithmetic unit (1)! % (4) is a register Bl that takes in an input from the outside (hereinafter referred to as source S data), and (51 is an overflow flag register that stores the occurrence of overflow due to an operation of the arithmetic unit (1)).

Next, before the 6 arithmetic unit (1) starts calculation, the register A, +3) stores the data of the register ~ inside the arithmetic unit (1), and similarly register B1 (4)
1 stores data of source S.

Arithmetic unit (1) receives data from register AL(3) and register B, +41 according to the arithmetic command from instruction decoder (2I).
Arithmetic operations such as addition, subtraction, multiplication, and division are performed using the data as input data, and the arithmetic results are stored in the register width inside the arithmetic unit (1). If an overflow occurs during execution of this operation, the arithmetic unit (1) sets an overflow flag register (5).

For example, in the case of the most significant signed 4-bit operation, Figure 8.
b) will be explained. If the most significant sign bit is 0, it is a positive number, and if it is l, it is a negative number. Now, register Ayu (3) is 01
01 (+5 binary number), 0111 in register Bl (4)
(+7 binary number) data is stored and the instruction decoder (
Assume that 2) generates an addition operation command. Arithmetic unit (1) performs addition of input data and produces an arithmetic result 110.
Q (binary number -4) is calculated and stored in the internal register. Further, in this case, since an overflow occurs, the flag of the overflow flag register (5) is set.

, since the conventional arithmetic unit is configured as above,
When an overflow occurs, the overflow operation result is stored in a register. For this reason, for example, if the data in register Am (3) and register Aki (4) are positive numbers and an overflow occurs during addition, a negative number tends to be stored in the registers.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and when over 7O-d1 occurs due to an operation, the sign of each data in register At (3) and register Aki (4) and the operation result are changed. It is an object of the present invention to provide a device that stores the maximum value of a proper sign as an operation result in a register based on the type of operation.

An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, (6) is register ALC3), register B
The positive and negative signs of the data in the register l(4), (2
bυ is a discriminator that determines the positive or negative sign of the operation result according to the operation format of arithmetic unit (1). ) is an excessive value control circuit which outputs a signal for setting the maximum value having the sign of a code signal and includes an overflow flag register (5).

Next, the operation will be explained. Arithmetic unit (1) is register A
The series of operations of using the data in register Bl (41) as input data, performing arithmetic operations in accordance with the arithmetic instructions of the instruction decoder (2), and storing the results in registers are the same as in the conventional device.

In the present invention, when an overflow occurs due to an operation,
The discriminator (6) uses register A1 (3), register (
4) A signal indicating whether the data is a positive number or a negative number and the type of operation (addition, subtraction,
Excess value control circuit II
Output to. The excess value control circuit 1li11 is a discriminator (6)
In response to the signal and the overflow generation signal of the arithmetic unit (1), a maximum positive value or a maximum negative value setting signal is output to the arithmetic unit (1), and an internal overflow flag register is set.

Next, the operation n(t) stores a positive or negative maximum value in the register 1 in accordance with the positive static value or negative maximum value setting signal from the excess value control circuit 1.

For example, as shown in Figure 8 10), register A1 (3
), the data in register B1 (4) are both positive numbers, and if an overflow occurs when the calculation command from the instruction decoder (2) is addition, the maximum positive value is stored in the register of the calculation unit (1). 0111 (binary number +7) is stored.

In the above embodiment, the instruction decoder (2) outputs the signal to the discriminator (6) during addition, subtraction, multiplication, and division, but depending on the instruction system of the arithmetic unit, it may also output signals during other operations. It's okay. Also, from the discriminator (6) to the arithmetic unit (1)
A switch may be provided for the signal to make it selectable as necessary.

As described above, according to the present invention, it is possible to prevent the inconvenience caused by the inversion of the maximum value sign of the correct sign as a calculation result when an overflow occurs, and to obtain the value closest to the true value. For example, if the output of the register ~ is used as the speed reference of the motor, when an overflow occurs during calculation with forward rotation data (positive number), the calculation result will be a negative number and the motor will not rotate in reverse, and the maximum speed will be maintained. Since the motor rotates in the normal direction, abnormal movement (hunting, etc.) of the motor and machine can be eliminated.

[Brief explanation of the drawing]

Reference numeral 111 is a circuit diagram of a conventional arithmetic device, and FIG. 2 is a circuit diagram of an arithmetic device that automatically corrects overflow according to an embodiment of the present invention. Moreover, FIG. 8 is an explanatory diagram of an example of calculation. In the figure, (1) is an arithmetic unit, (2) is an instruction decoder,
(3) is a register, (4) is a register A%FD is an excess value control circuit, and (6) is a discriminator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2 Figure 13 (a) (0) Kashitako (7) B] H mouth (7)

Claims (1)

[Claims] an arithmetic unit that calculates an operand value and an addition value; a discriminator that determines the sign of the operation result based on the sign of the operand value and the addition value and the type of operation; and when the arithmetic unit overflows, and an excessive value control circuit that sets the maximum value having the sign determined by the discriminator as the calculation result of the calculation unit.