JPS6244657B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an arithmetic processing device that controls arithmetic operations of an arithmetic logic circuit in a microprogram-controlled data processing device. Conventionally, this type of arithmetic processing device has a data register that stores two operands, a register that specifies the arithmetic operation of the operand, an arithmetic logic circuit (ALU) that performs the arithmetic operation of the operand, and an arithmetic logic circuit (ALU) that stores the result of the operation. It consists of registers for storing data. Now, when trying to find the absolute value of fixed-point data, "0" data is set in one of the two registers that store the operand, and the fixed-point data is set in the other. Next, the leftmost bit of the fixed-point data is checked to determine whether the data is positive or negative. If the data is non-negative (positive or zero), an arithmetic mode for addition is set in the mode register specifying the arithmetic mode;
If the data is negative, a mode for subtraction is set in the mode register specifying the operation data. Finally, the output of the arithmetic logic circuit is set in a register that stores the arithmetic result. Therefore, if such an operation is to be achieved by controlling it with a microprogram, four steps are required. SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic processing device that can reduce the number of steps in a microprogram for determining the absolute value of fixed-point data. The device of the present invention is a microprogram-controlled information processing device that includes an arithmetic logic circuit that performs arithmetic operations instructed by a microprogram, and an arithmetic mode switching circuit that selects an arithmetic mode according to conditions of input data of the arithmetic logic circuit. and the arithmetic operation of the arithmetic logic circuit is controlled by the output of the arithmetic mode switching circuit. Next, the present invention will be explained in detail with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes 4-byte data registers 1 and 2 for storing two operands, a mode register 4 for storing the operation mode of the operands, and a control register for instructing absolute value calculation. A register 5, an AND gate 7 which takes the AND of the absolute value operation instruction 2a and the leftmost bit 1a of the data register 2, an operation mode switching circuit 6 which switches the operation mode based on the output 3a of the AND gate, and the operation It consists of an arithmetic logic circuit (ALU) 8 that performs arithmetic operations on the two operands in the arithmetic mode instructed by the mode switching circuit 6, and a 4-byte result register 3 that stores the arithmetic results of the circuit 8. Next, the operation of this embodiment will be explained in detail with reference to FIG. 1, Tables 1 and 2. Referring to Table 1, the calculation modes Mo-M ₄ are (1, 0, 1, 1, 0) and (1, 1, 0), respectively.
0, 0, 1), the subtraction and addition operations will be explained in detail below. Note that Table 2 shows how the outputs (So, S ₁ , S ₂ , S ₃ , S ₄ , C ₀ ) of the mode register 4 are changed by the operation mode switching circuit 6. As is clear from Table 2, the calculation mode does not change when there is no absolute value calculation instruction, but the calculation mode changes when there is an absolute value calculation instruction and the sign is negative.

【table】

【table】

[Table] For example, to find the absolute value of 4-byte fixed-point data X, the first
In the step, the data registers 1 and 2 are set to "0" and the data X, and the mode register 4 is set to the addition mode (S ₀ , S ₁
S ₂ , S ₃ , S ₄ , C ₀ ) = (1, 1, 0, 0, 1, 0)
is set, and "1" is set in the control register 5 as an instruction to perform absolute value calculation.
At that time, the AND gate 7 is opened and the operation mode is switched according to the sign bit of the data X as shown in Table 2. If _{the value of data}
The arithmetic mode (1, 1, 0, 0, 1, 1, 0) set in the register 4 as CIN) directly controls the arithmetic logic circuit 8. According to this control, "0+X" is calculated and the data X is output as is. However _{, when the value of} ,
CIN)=(1, 0, 1, 1, 0, 1), and the arithmetic logic circuit 8 performs subtraction, so that the two's complement of the data X, "-X", is output. Therefore,
The absolute value |X| of the data X is determined. In the next step, the absolute value |X| of the data X is set in the result register 3. This can be done in two steps in the microprogram as shown in FIG. Similarly, the mode register 4 is set to (S ₀ , S ₁ ,
S ₂ , S ₃ , S ₄ , C ₀ )=(1, 0, 1, 1, 0, 1),
That is, it is possible to set the subtraction mode and calculate the negative absolute value "-|X|" of the data X. The present invention has the advantage that the number of microprogram steps can be reduced when determining the absolute value of fixed-point data.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the flow of a microprogram when calculating an absolute value using a conventional arithmetic logic circuit, and FIG. FIG. 3 is a diagram showing the flow of a microprogram when calculating an absolute value in one embodiment of the present invention. In Figures 1 to 3, 1...operand 1
2...Data register of operand 2, 3...Arithmetic result register, 4...Mode register, 5...Control register, 6...Arithmetic mode switching circuit, 7...And gate, 8... Arithmetic logic circuit.

Claims (1)

[Claims] 1. In a microprogram-controlled information processing device, first and second data storage means for storing first and second calculation data, respectively; calculation mode storage means for storing calculation mode information;
instruction information storage means for storing absolute value instruction information for instructing absolute value calculation; and when the absolute value instruction information is supplied, a sign bit of the second calculation data indicates that the data is a positive number or zero. When the sign bit indicates that this data is a negative number, the arithmetic mode information stored in the arithmetic mode storage means is outputted, and when the sign bit indicates that this data is a negative number, it is stored in the arithmetic mode storage means. a switching control means for converting and outputting the calculation mode information instructing a subtraction operation into information instructing a subtraction operation; arithmetic means for performing an arithmetic operation; information for instructing the arithmetic mode storage means, the instruction information storage means, the first data storage means and the second data storage means to perform an addition operation; the absolute value instruction information; 1. An arithmetic processing device comprising a storage means storing a microprogram including a microinstruction for simultaneously storing data whose value is zero and data which should take an absolute value.