JPS5971542A - Arithmetic processor - Google Patents
Arithmetic processorInfo
- Publication number
- JPS5971542A JPS5971542A JP57182330A JP18233082A JPS5971542A JP S5971542 A JPS5971542 A JP S5971542A JP 57182330 A JP57182330 A JP 57182330A JP 18233082 A JP18233082 A JP 18233082A JP S5971542 A JPS5971542 A JP S5971542A
- Authority
- JP
- Japan
- Prior art keywords
- register
- instruction
- general
- arithmetic
- zero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術公約０詩勢手
本発明はデータ処理装置に於ける演算処理装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic processing device in a data processing device.
従来、この種の演算制御装置は演算部の入力データとな
る汎用レジスタの出力データを判定して、特定の値を検
出する検出回路を有し、この検出回路の出力を参照して
制御部は指定された演算の実行方式を決定していた。従
って指定された演算の実行方式は指定された汎用レジス
タ内のデータを読み出さなければ決定できなかった。Conventionally, this type of arithmetic control device has a detection circuit that detects a specific value by determining the output data of a general-purpose register that is the input data of the arithmetic unit. The execution method for the specified operation was determined. Therefore, the execution method of a specified operation could not be determined without reading the data in the specified general-purpose register.
本発明の目的は、汎用レジスタに対応してフラグレジス
タを設け、汎用レジスタを用いる演算において汎用レジ
スタの値が特定の値の場合の演算を高速に容易に実行す
ることを可能とする演算処理装置を提供することにある
。An object of the present invention is to provide an arithmetic processing device that provides a flag register corresponding to a general-purpose register, and enables high-speed and easy execution of an operation when the value of the general-purpose register is a specific value in an operation using the general-purpose register. Our goal is to provide the following.
本発明は複数の汎用レジスタを用いた演算命令を実行す
る情報処理装置に於いて、前記汎用レジスタへの書込み
データを判定して特定の値であることを検出する検出回
路と、前記汎用レジスタに対応して設けられ前記検出回
路の出力を記憶する複数のフラグレジスタと、前記汎用
レジスタを用いた演算の実行に際し対応する前記フラグ
レジスタの内容を参照して指定された演算の実行方式を
決定する制御回路とを含んで構成される。The present invention provides an information processing device that executes arithmetic instructions using a plurality of general-purpose registers, including a detection circuit that determines data written to the general-purpose register and detects that the data is a specific value; A plurality of flag registers are provided correspondingly to store the output of the detection circuit, and when executing an operation using the general-purpose register, the execution method of the specified operation is determined by referring to the contents of the corresponding flag register. and a control circuit.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
本発明の実施例な示す第１図において、本発明の演算処
理装置は制御部１と、演算部２と、汎用レジスタ群３と
、該汎用レジスタ群３の書き込みデータである演算部２
の出力の値を判定して零を検出する検出回路４と、汎用
レジスタ３に対応して存在し検出回路４の出力を記憶す
るフラグレジスタ群５より構成される。In FIG. 1, which shows an embodiment of the present invention, the arithmetic processing device of the present invention includes a control section 1, an arithmetic section 2, a general-purpose register group 3, and an arithmetic section 2 which is the write data of the general-purpose register group 3.
The detection circuit 4 includes a detection circuit 4 that determines the value of the output of and detects zero, and a flag register group 5 that is present in correspondence with the general-purpose register 3 and stores the output of the detection circuit 4.
汎用レジスタ３を用いる演算命令において、制御部１け
命令を解読した情報と、指定された汎用レジスタ３に対
応したフラグレジスタ５の内容により命令を実行する。In an arithmetic instruction using the general-purpose register 3, the instruction is executed based on the information obtained by decoding the 1-digit instruction by the control unit and the contents of the flag register 5 corresponding to the specified general-purpose register 3.
制御部１は演算部２に必要に応じてオペランドを供給し
、演算部２は制御部１より与えられる制御情報に従って
演算を実行する。演算部２で出力される演算結果は、汎
用レジスタあるいは主記憶装置へ格納される。演算結果
が汎用レジスタ３へ格納される場合、検出回路４は演算
結果の値を判定し零か否か検出し、その出力が汎用レジ
スタ３０更新タイミングに更新される汎用レジスタに対
応するフラグレジスタに格納される。The control unit 1 supplies operands to the calculation unit 2 as necessary, and the calculation unit 2 executes calculations according to control information provided by the control unit 1. The calculation results output by the calculation unit 2 are stored in a general-purpose register or main memory. When the calculation result is stored in the general-purpose register 3, the detection circuit 4 judges the value of the calculation result, detects whether it is zero, and stores the output in the flag register corresponding to the general-purpose register to be updated at the general-purpose register 30 update timing. Stored.
次に２つのオペランドが汎用レジスタを用いる乗算にお
いてオペランド２が零の場合を例にと９１動作を説明す
る。制御部１は命令を解読した情報に従ってオペランド
１お工びオペランド２に対応する汎用レジスタ３とフラ
グレジスタ５を読み出す。オペランド２に対応するフラ
グレジスタ５の内容よりオペランド２が零であることを
知ると、制御部１は演算部２に対し乗算の指示は行なわ
ず、積すなわち演算結果が零になることにより演算部２
に対して演算結果を零として出力するよう指示する。演
算部２より出力される演算結果は命令で指定されたとこ
ろへ格納されて乗算命令が終了する。Next, the operation of 91 will be described using as an example the case where operand 2 is zero in multiplication using general-purpose registers as two operands. The control unit 1 reads out the general-purpose register 3 and flag register 5 corresponding to the operand 1 and operand 2 according to the information obtained by decoding the instruction. When the control unit 1 learns that operand 2 is zero from the contents of the flag register 5 corresponding to operand 2, it does not instruct the calculation unit 2 to multiply. 2
Instructs to output the operation result as zero. The calculation result output from the calculation unit 2 is stored in the location specified by the instruction, and the multiplication instruction ends.
本発明は以上説明したように、汎用レジスタ対応にフラ
グレジスタを持つことにより、指定された汎用レジスタ
内のデータが特定の値の場合の演算を高速処理できると
いう効果がある。As described above, the present invention has the effect that by providing a flag register corresponding to a general-purpose register, calculations can be performed at high speed when data in a designated general-purpose register has a specific value.
第１図は本発明の一実施例のブロック構成図である０
１・・・・・・制御部、２・・・・・・演算部、３・・
・・・・汎用レジスタ群、４・・・・・・検出回路、５
・・・・・・フラグレ・ジスタ生記すｔ＃、ｔ
主意こ４１．１１幣１ 図FIG. 1 is a block configuration diagram of an embodiment of the present invention.
...General-purpose register group, 4...Detection circuit, 5
・・・・・・Fragregist recording t#, t
Main meaning 41.11 coin 1 figure
Claims (1)
理装置に於いて、前記汎用レジスタへの書込みデータを
判定して特定の値であることを検出する検出回路と、前
記汎用１／ジスタに対応して設けられ前記検出回路の出
力を記憶する複数のフラグレジスタと、前記汎用レジス
タを用いた演算の実行に際し対応する前記フラグレジス
タの内容を参照して指定された演算の実行方式を決定す
る制御回路とを含むことを特徴とする演算処理装置。In an information processing device that executes arithmetic instructions using a plurality of general-purpose registers, a detection circuit that determines write data to the general-purpose register and detects that it is a specific value, and corresponds to the general-purpose 1/register. a plurality of flag registers that are provided to store outputs of the detection circuit, and a control that determines an execution method of a specified operation by referring to the contents of the corresponding flag register when executing an operation using the general-purpose register. An arithmetic processing device comprising a circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57182330A JPS5971542A (en) | 1982-10-18 | 1982-10-18 | Arithmetic processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57182330A JPS5971542A (en) | 1982-10-18 | 1982-10-18 | Arithmetic processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5971542A true JPS5971542A (en) | 1984-04-23 |
Family
ID=16116415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57182330A Pending JPS5971542A (en) | 1982-10-18 | 1982-10-18 | Arithmetic processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5971542A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6282558B1 (en) | 1997-12-19 | 2001-08-28 | Matsushita Electric Industrial Co., Ltd. | Data processing system and register file |
| WO2006006842A2 (en) * | 2004-07-12 | 2006-01-19 | Halil Kilic | Digital processor and method of processing digital data |
-
1982
- 1982-10-18 JP JP57182330A patent/JPS5971542A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6282558B1 (en) | 1997-12-19 | 2001-08-28 | Matsushita Electric Industrial Co., Ltd. | Data processing system and register file |
| US6334135B2 (en) | 1997-12-19 | 2001-12-25 | Matsushita Electric Industrial Co., Ltd. | Data processing system and register file |
| WO2006006842A2 (en) * | 2004-07-12 | 2006-01-19 | Halil Kilic | Digital processor and method of processing digital data |
| WO2006006842A3 (en) * | 2004-07-12 | 2006-06-01 | Halil Kilic | Digital processor and method of processing digital data |
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