JPS6389930A - Microprogram controller - Google Patents

Abstract

PURPOSE:To process at high speed without invalidating instruction read before and without interrupting execution of the instruction by providing a means that fetches next microinstruction according to genuineness of the result of conditional calculation of arithmetic logical unit in case of condition branching instruction. CONSTITUTION:In case of condition branching instruction, an address in case of the result of condition calculation is true is generated by a sequencer 11a while an arithmetic logical unit ALU 15 is executing condition calculation, and at the same time, an address in case of the result is false is generated by a sequencer 11b, and next instruction is fetched. Then, registers 13a, 13b latches microinstructions in case of truth and falsehood, and at the same time, a flag register 16 latches the result of condition calculation of ALU 15. A control logic 17 outputs selection signals of next microinstruction to each selector according to the latched content of the register 16, and selectors 14a, 14b, 14c select next microinstruction. As microinstructions in case of the result is true and false is fetched during condition calculation of ALU 15, execution of calculation and fetch of instruction can be processed in parallel, and processing can be made at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprogram control device, and more particularly to instruction prefetch control of a microprogram control device in a data processing device or the like.

BACKGROUND ART 2 As shown in FIG. 2, in a conventional microprogram control device, when a sequencer 1 generates an address for a microprogram memory 2, the microprogram memory 2 executes a microinstruction corresponding to that address. register 3 latches the microinstruction.

Next, the sequencer 1 executes an arithmetic logic unit (ALU) operated by the next address control instruction part of the microinstruction and the ALU control instruction part of the microinstruction.
The next address of the microprogram memory 20 is generated by the flag of the etic Logic Unit.

Problems to be Solved by the Invention However, in such a configuration, since the microinstructions are latched by one register 3, it is not possible to perform pipeline processing to process program instructions at a higher speed. There is.

On the other hand, in order to solve the above problems, a method is known in which a register 3 is arranged between the sequencer 1 and the micro program memory 2, and the address of the micro 3 vane program memory 2 from the sequencer 1 is latched. However, in this case, if there is a conditional branch instruction, the instruction is executed and the address cannot be determined until the result is determined, so there is a problem that even if the instruction is prefetched, it becomes invalid.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a microprogram control device that can process instructions at high speed without invalidating prefetched instructions and without temporarily interrupting instruction execution.

Means for Solving the Problems In order to solve the above problems, the present invention provides means for fetching the next microinstruction when the conditional calculation result of the arithmetic logic unit is true in the case of a conditional branch instruction, and means for fetching the next micro-instruction when the condition is true or false, and means for selecting the next micro-instruction when the condition is true or false according to the condition calculation result of the arithmetic and logic unit; It is characterized by being configured to output.

Effect: With the above configuration, the present invention selects the next microinstruction according to the result of conditional calculation of the arithmetic logic unit, so that instruction fetch and instruction execution can be processed in parallel, thus enabling high-speed processing. .

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a microprogram control device according to the present invention.

This device, as shown in FIG.
Sequencer 1 generates addresses a and 12b, respectively.
1a and llb, memo IJ12a and 12b in which microprograms are respectively stored, and memories 12a and 12b.
registers 13a and 13b that each latch a microinstruction (instruction) from , and a selector 14 that selects the next microinstruction depending on the state of a flag, which will be described later.
a, 14b, and 14c.

This device also has an arithmetic logic unit (ALU: A
15
, a flag register 16 that latches the result of a total of 5 page calculations in ALU 15, and a control logic 17 that determines the selection signal for the next microinstruction based on the state of the flag register 16.

Next, the operation of the embodiment according to the above configuration will be explained.

First, if it is not a conditional branch instruction, the sequencers 11a and llb generate the same address, and the memories 12a and 12
A microinstruction is output from b.

Next, registers 13a and 13b are respectively stored in memory 1.
The microinstructions from 2a and 12b are latched, and the sequencers lla and llb generate the next address and store it in memory 12.
ALU15 fetches the microinstructions of a and 12b, and executes the instructions.

On the other hand, in the case of a conditional branch instruction, while ALU 1,5 is executing conditional calculation, sequencer ll& generates an address when the conditional calculation result is true, and sequencer 11b generates an address when the conditional calculation result is false, and the next Perform instruction fetch.

Next, when registers 13a and 13b respectively latch the microinstructions for true and false, flag register 6 simultaneously latches the condition calculation result of ALU15, and control logic 17 uses the result of flag register 16 to A selection signal for the next microinstruction is output to selectors 14a, 14b, and 14c, and selector 14a
, 14b, 14e select the next microinstruction.

That is, according to the above embodiment, since the microinstructions for when the condition result is true and when the condition result is false are fetched during the execution of conditional calculation in ALU15, calculation execution and instruction fetch can always be processed in parallel, and therefore high speed processing becomes possible.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention provides a means for fetching the next microinstruction when the conditional calculation result of the arithmetic logic unit is true in the case of a conditional branch instruction, and a means for fetching the next microinstruction when the conditional calculation result of the arithmetic logic unit is false. The present invention is configured to include means for fetching and means for selecting the next microinstruction when the condition is true or false based on the result of conditional calculation by the arithmetic and logic unit, and is configured to output the selected microinstruction to the arithmetic and logic unit. Arithmetic theory 7
The next microinstruction is selected according to the result of conditional calculation by the page ring unit, so that instruction fetch and instruction execution can be processed in parallel, making high-speed processing possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram control device according to the present invention, and FIG. 2 is a block diagram showing a conventional example. 11a, 1lb-... sequencer, 12a, 12b...
...Memory, 1.3a, 13b...Register, 14
a...14b, 14c...Selector, 15...Logic operation unit (ALU), 16...Flag register, 17...Control logic. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
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Claims (1)

[Claims] an arithmetic logic unit, means for latching a conditional calculation result of said arithmetic and logic unit, means for fetching a next microinstruction when the conditional calculation result of said arithmetic and logic unit is true in the case of a conditional branch instruction; means for fetching the next micro-instruction when the condition is true or false, and means for selecting the next micro-instruction when the condition is true or false based on the conditional calculation result of the arithmetic logic unit, and parallel processing of instruction fetch and instruction execution is provided. A microprogram control device characterized by: