JPH06124205A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To provide an instruction prefetching device capable of prefetching instruction data at the time of materializing conditions and at the time of not materializing the conditions in the case of executing a condition branching instruction at the time of executing a single task and prefetching the instruction data of the task being executed at present and the instruction data of the task to be executed next at the time of a multi-task processing. CONSTITUTION:Since the instruction data of a branching destination can be prefetched at the time of executing the condition branching instruction and also the instruction data of the task to be executed next can be prefetched at the time of the multi-task processing by providing a first instruction prefetching execution part 9 and a second instruction prefetching execution part 10, unrequired cycles for prefetching the instruction data and supplying the instruction data to an instruction data decoder 11 are reduced and the instruction can be executed at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention pre-fetches instruction data when a branch condition is not satisfied and when the branch condition is satisfied when executing a conditional branch instruction. The present invention relates to an instruction prefetch device capable of prefetching instruction data of a task to be executed.

[0002]

2. Description of the Related Art Conventionally, when prefetching instruction data at the time of execution of a conditional branch instruction, only one set of instruction prefetch queues for prefetching and storing the instruction data has been provided. Since only the instruction data of (1) can be prefetched, the prefetched instruction data can be used when the branch condition is not satisfied, but when the branch condition is satisfied, it is necessary to store the instruction data when the branch condition is satisfied again.

Although it is possible to prefetch the instruction data of the task currently being executed, it is executed in order to re-execute the task that was executed by interrupting at the time of task switching when performing multitask processing. It is necessary to save the pointer of the instruction data at the time of re-execution of the task in the storage device, and then store the start address and the instruction data of the task to be executed next, resulting in a large overhead.

[0004]

However, in the above-described conventional configuration, when the conditional branch instruction is executed, the instruction data of the branch destination cannot be prefetched, and when the conditional branch instruction is executed, the condition is satisfied and the branch is executed. It is necessary to restore the instruction data.

During multitask processing, an interrupt is issued at the time of task switching, the pointer of the instruction data at the time of re-execution of the task being executed is saved in the storage device, and then the instruction data of the task to be executed next is stored. Must be,
Since the instruction data of the task to be executed next cannot be prefetched, there is an unnecessary empty cycle for supplying the instruction data to the instruction decoding device when the task is switched.

The present invention solves the above-mentioned conventional problems. When conditional branch instructions are executed, instruction data can be prefetched when a branch occurs and when a branch does not occur. Further, during multitask processing, the instruction data of a task currently being executed and An object of the present invention is to provide an instruction prefetch device capable of prefetching instruction data to be executed next.

[0007]

In order to achieve this object, an instruction prefetch apparatus of the present invention comprises two sets of instruction prefetch queues for storing prefetched instruction data. Two sets of first means for instructing a write address to the prefetch queue, second means for instructing a read address to the instruction prefetch queue, and two third means for indicating the effective number of bytes of the instruction prefetch queue are provided. (1) When executing a conditional branch instruction during single task execution, one of the instruction prefetch queues prefetches instruction data when the branch condition is not satisfied, that is, when branching is not performed, and when the branch condition is satisfied, that is, when branching to the other instruction prefetch queue. Prefetch the instruction data of.

(2) During multitask processing, it is possible to prefetch one instruction prefetch queue with the instruction data of the task being executed and the other instruction prefetch queue with the instruction data of the task to be executed next. It is configured as follows.

[0009]

With this configuration, when a conditional branch instruction is executed,
The instruction data at the branch destination can be prefetched, and the instruction data for the task to be executed next can be prefetched during multitask processing, so there is no unnecessary space for supplying instruction data to the conventional instruction decoding device. The cycle is gone.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an instruction prefetch device and an instruction data decoding device according to an embodiment of the present invention.

In FIG. 1, reference numerals 1 and 2 denote a first instruction prefetch queue and a second instruction prefetch queue for storing instruction data prefetched from a storage device (not shown).
Addresses 1 and 3 of the instruction data to be prefetched to the storage device
02, and at the same time, the write address 103 of the first instruction prefetch queue 1 and the write address 104 of the second instruction prefetch queue 2 (the write addresses 103 and 104 are the first instruction prefetch queue 1 and the second instruction prefetch queue 1, respectively). Each instruction prefetch queue 2 of 8 bytes is composed of 8 bytes.
0, 101 (using the lower 3 bits of 0, 101) and a second write address counter, 5 and 6 indicate the pointer of the instruction currently being executed, and at the same time, the first instruction prefetch queue 1 read address 125 and read address 126 of the second instruction prefetch queue 2 (read addresses 125, 1
The first instruction prefetch queue 1 and the second instruction prefetch queue 2 are each composed of 8 bytes.
If the address is 1 byte, the lower 3 bits of the pointers 113 and 114 of the instruction currently being executed are used), 7 and 8 are the effective byte number 105 of the first instruction prefetch queue 1 and the second instruction prefetch queue 2, respectively. 106, a write enable signal to the first instruction prefetch queue 1 and the second instruction prefetch queue 2, and an address output to the storage device to the first write address counter 3 and the second write address counter 4. A first valid byte number counter that outputs permission signals 107 and 108, a second valid byte number counter, and 9 are the first instruction prefetch queue 1, the first write address counter 3, and the first read address counter. 5, a first instruction prefetch execution unit composed of a first valid byte number counter 7, 10 is the second instruction prefetch queue 2, a second instruction prefetch queue Can included the address counter 4, a second read address counter 6, a second instruction prefetch execution unit composed of a second active byte counter 8.

Reference numeral 11 is an instruction decoding device (not included in the instruction prefetch device) for decoding instruction data and outputting a decoding information signal, and 12 is an address 109 output by the first write address counter 3 and the second Of the write address counter 4 and a multiplexer 13 for selecting the address 110 output from the write address counter 4, and the number 13 of valid bytes output from the first valid byte number counter 7 and the second valid byte number counter 8 A multiplexer for selecting 112 and a pointer 14 for an executing instruction output by the first read address counter 5 and a pointer 114 for an executing instruction output by the second read address counter 6. The multiplexer to select, 15 is the first instruction prefetch queue 1
For selecting the instruction data 115 output by the second instruction prefetch queue 2 and the instruction data 116 output by the second instruction prefetch queue 2, 16 indicates the address 10 output by the first write address counter 3 to the storage device.
0 is a multiplexer for selecting 0 and the address 101 output to the storage device by the second write address counter 4, 17 is an output 1 of the multiplexer 12.
17 is an adder for adding the byte number 118 of the prefetched instruction data, and the output 119 of the adder 17
Thus, the first write address counter 3 or the second write address counter 4 is updated. 1
Reference numeral 8 denotes a subtracter for subtracting the output 120 of the multiplexer 13 and the byte number 127 of the decoded instruction,
Reference numeral 19 denotes an adder for adding the output 121 of the subtracter and the byte number 118 of the prefetched instruction data, and the output 122 of the adder 19 causes the first valid byte counter 7 or the second valid byte to be added. The number counter 8 is updated.

Reference numeral 20 denotes an output 1 of the multiplexer 14.
23 is an adder for adding the number of bytes 127 of the instruction which has been decoded and 127, and the first read address counter 5 or the second read address counter 6 is updated by the output 124 of the adder 20. Reference numeral 21 is an instruction prefetch control device for controlling the multiplexers 12, 13, 14, 15, 16 and providing inputs to the adders 17, 19, 20 and subtractor 18.

With respect to the instruction prefetch device of the present embodiment configured as described above, hereinafter, (1) execution of instructions other than conditional branch instructions during single task processing, (2) execution of conditional branch instructions during single task processing At this time, the operation will be described in three cases (3) multitask processing.

(1) Prefetching of instructions other than conditional branch instructions and multitask processing will be described.

In this case, the second instruction prefetch execution unit 1
Since 0 is not used and the first instruction prefetch execution unit 9 is used, the instruction prefetch control device 21 causes the multiplexers 12, 13, 14, 15, 16 to execute the first instruction prefetch execution unit 9 of the first instruction prefetch execution unit 9. The select signal 128 is output so as to select the data to be output, and the adders 17 and 1
It is assumed that the outputs of 9 and 20 update the first write address counter 3, the first valid byte number counter 7, and the first read address counter 5.

The condition for outputting 107, which is a write permission signal to the first instruction prefetch queue 1 and an address output permission signal to the storage device (hereinafter, instruction prefetch permission condition), is The number of bytes of the instruction prefetch queue 1 minus the first valid byte number counter 7 ≧ the number of bytes of instruction data to be prefetched.

First, at the start of an instruction, the first valid byte counter 7 is zero, so the write enable signal and the address output enable signal 107 are output, and the first write address counter 3 is output. And a start address 129 is stored in the first read address counter 5 from the storage device, and the first write address counter 3 stores the address 100 (start address 1
The same as 29) is output to indicate the address 102 of the instruction data to be prefetched to the storage device, and the instruction data 130 to the first instruction prefetch queue 1 according to the write address 103 indicated by the first write address counter. Is stored, the instruction prefetch control device is
The number of bytes 118 of the prefetched instruction data is output, and the address (the same as the start address 129) 109 output from the first write address counter 3, that is, the output 117 of the multiplexer is added by the adder 17, and the first write is performed. The address counter 3 is updated, and similarly, the first valid byte number counter 7 is also updated by the output of the adder 19. Then, by outputting the instruction data 115 according to the read address 125 designated by the first read address counter 5, the instruction data decoding device 11 receives the instruction data 119, starts decoding the instruction, and finishes decoding the instruction. For data, a signal 131 indicating the number of bytes is sent to the instruction prefetch control device 2
The instruction prefetch control device 21 outputs the byte number 128 of the decoded instruction data to the adder 20 and the subtractor 18 by sending the data to the first read address counter 5, that is, the current read address counter 5. The pointer of the instruction being executed is updated, and the first valid byte number counter 7 is also updated. Then, when the decoding and execution of one instruction are completed, the instruction decoding end signal 132
Is output, the instruction prefetch control device 21 instructs the instruction data read enable signal 133 to the first instruction prefetch queue 1 to read the instruction data according to the read address 125. Further, the instruction data can be prefetched whenever the instruction prefetch permission condition is satisfied.

As described above, the instruction can be prefetched efficiently by writing and reading the first instruction prefetch queue 1.

(2) Next, the prefetching of instruction data when the condition is satisfied and when the condition is not satisfied when the conditional branch instruction is executed will be described.

Since the first instruction prefetch execution unit 9 and the second instruction prefetch execution unit 10 have exactly the same functions,
Details of the instruction prefetch in the second instruction prefetch execution unit 10 will be omitted. The instruction before the conditional branch instruction is executed is prefetched and read by using the first instruction prefetch execution unit 9 as described in (1) above, and when the conditional branch instruction is executed, the condition is not satisfied. That is, when the instruction data in the case of not branching is prefetched to the second instruction prefetch queue 2 and the condition is satisfied, that is, in the case of branching, if the instruction data decoded by the instruction data decoding device 11 is judged to be a conditional branch instruction, the branch destination Address 134 of the instruction data is output by decoding, and the branch destination address 1 is sent to the second write address counter 4 and the second read address counter 6.
34 is stored, and instruction data 135 is stored in the second instruction prefetch queue 2 from the storage device in the same manner as the first instruction prefetch execution unit. After the execution of the conditional branch instruction, the instruction data decoding device 11 outputs the result flag 136 to the instruction prefetch control device, and when the condition is not satisfied, the instruction prefetch execution unit 9 is continuously used to If the condition is satisfied, the instruction prefetch control device 21 outputs the select signal 128 so as to select the data output from the second instruction prefetch execution unit 10.

Prefetching of instruction data subsequent to branching is executed by using the second instruction prefetching execution unit 10. If a conditional branch instruction is further executed, prefetching of instruction data when not branching is performed as described above. Second instruction prefetch execution unit 10
The first instruction prefetch execution unit 9 is used for prefetching instruction data when a branch occurs.

(3) Instruction prefetching during multitask processing will be described. First, the task to be executed first performs instruction prefetching using the first instruction prefetching execution unit 9 as in (1) above, and prefetching the instruction data of the task to be executed next is Before switching between the two, the start address 137 of the next task to be executed is stored in the second write address counter 4 and the second read address counter 6, and the instruction data 135 is stored in the second instruction prefetch queue 2.
In advance. When switching the task, the instruction prefetch control device 21 switches the selector signal 128, the output data of the second instruction prefetch execution unit 10 is selected, and execution of the next task starts. When prefetching the instruction data of the next task, the first instruction prefetch execution unit 9 is used.

As described above, also in the case of multitask processing, the first instruction prefetch execution section and the second instruction execution section are alternately used.

[0026]

According to the present invention, by providing two sets of the instruction prefetch queue and the first, second and third means, the instruction data when the condition is satisfied and the instruction data when the condition is not satisfied at the time of executing the conditional branch instruction. It is possible to realize an excellent instruction prefetch device capable of prefetching and prefetching instruction data of a task to be executed next at the time of multitask processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an instruction prefetch device according to an embodiment of the present invention.

[Explanation of symbols]

 1 1st instruction prefetch queue 2 2nd instruction prefetch queue 3 1st write address counter 4 2nd write address counter 5 1st read address counter 6 2nd read address counter 7 1st effective byte number counter 8 Second Effective Byte Count Counter 9 First Instruction Prefetch Execution Unit 10 Second Instruction Prefetch Execution Unit 11 Instruction Data Decoding Device 12-16 Multiplexer 17, 19, 20 Adder 18 Subtractor 21 Instruction Prefetch Control Device

Claims (1)

[Claims] 1. A set of two instruction prefetch queues for prefetching and storing instruction data from a storage device, corresponding to the address of the prefetched instruction data, and at the same time a write address of the instruction prefetch queue. First means for indicating, a pointer for instruction data currently being executed, second means for indicating a read address of the instruction prefetch queue at the same time, and first means for indicating the number of bytes of valid instruction data in the instruction prefetch queue When two sets of three means are provided and a conditional branch instruction is executed during single task execution,
Two sets of the instruction prefetch queues, the first, second, and third means are used at the same time, and the instruction data when the condition is not satisfied is the instruction prefetch used when the instruction before executing the conditional branch instruction is prefetched. By prefetching to the queue and prefetching the instruction data when the branch condition is satisfied to the other instruction prefetch queue, if the branch condition is not satisfied after executing the conditional branch instruction, the instruction before executing the conditional branch instruction is prefetched. Select the instruction data prefetched to the instruction prefetch queue that was used when doing, and if the branch condition is satisfied, select the instruction data prefetched to the other instruction prefetch queue and proceed with the execution of the instruction. When continuously performing multi-task processing, two sets of instruction prefetch queues, first, second, and third means are used at the same time, and the currently executing task is used by the currently executing task. The instruction data of the task to be executed next is prefetched to the other instruction prefetch queue before switching the task, and the instruction data of the task to be executed next is prefetched when the task is switched. An instruction prefetch device characterized by selecting instruction data in the instruction prefetch queue of one of the stored instruction prefetch queues, advancing instruction execution, and prefetching instruction data in two sets of instruction prefetch queues alternately when switching tasks.