JPH065507B2 - Inference calculator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inference computer, and more particularly to a tag-based inference computer suitable for increasing the execution speed of unification processing.

[Prior art]

In conventional unification processing, IPSJ 3rd
Proceedings of the 0th Annual Convention (1985) "Process Internal Representation in Parallel Inference Machine PIM-R" (6C-7,
P. As shown in 197), a tag portion is provided in the data representing the arguments on the goal side and the close side, and the type of argument is identified by the tag to determine the next processing. However, the process of extracting the tag portion from the data is described in a program, and is performed by masking the data and shifting the bits.

[Problems to be Solved by the Invention] In this method, a large number of steps, that is, time is required even for the process of extracting the tag portion from the data, and the same process is performed for the arguments on the calling side and the closing side. is necessary. Therefore, each time a unification process is performed once, the same process must be repeated twice to find out the combination of arguments on the goal side and the close side.

Therefore, considering a series of processes such as the identification of the argument by the tag and the determination of the next processing routine based on the combination of the arguments and the branch to that, "the branch of the processing according to the combination of the arguments" which is the preprocessing of unification. The process was complicated and time consuming. As described above, in the conventional unification processing as shown in the above-mentioned document, there is a problem in that the processing of the above-described example, that is, the processing of the entire unification is speeded up.

An object of the present invention is to provide a data processing device using a tag, which has a small processing procedure (the number of steps) and therefore has a short processing time, which is faster and more efficient.

[Means for solving problems]

The main process in the prolog execution is the unification process. The process is
Comparing and writing the arguments on the goal side and the close side in the corresponding predicate. This process depends on the type of argument processed. The type of this argument is generally indicated in the tag section in the data. Therefore, the comparison and writing processes of the arguments are performed by taking out the tag portion in the data and transferring the control to the corresponding routine according to the contents of the tag.

In the above process, the tag part is taken out, the corresponding routine is identified, and the control is transferred. Conventionally, this processing is described by a program, data is masked, the tag portion is taken out, and control is transferred to a routine corresponding to the type of the argument depending on the content of the tag. This process has a large number of processing steps (number of execution steps), and is divided into two times, a goal argument and a tag argument, and the same processing is performed. In other words, it takes twice as many processing steps before the unified goal and the closing argument are passed to the corresponding processing routine.

If both the goal side and the close side can perform this processing at the same time, the unification processing can be speeded up. For that purpose, 1) Extract the tag part from the data.

2) The tag determines the address of the branch destination routine.

3) Branch of processing according to the address.

It is necessary to have a device that can execute such a series of processing at the same time on both the goal side and the close side with one instruction. Therefore, the present invention aims to realize the above-described object of speeding up by providing a hardware device having the above-mentioned function.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, FIG. 2 is a flow chart of processing in one embodiment of the "data processing device using tags" according to the present invention. Here, from the point where the tag part of the operand is taken out to the point where the program branches.

FIG. 3 is a diagram showing a schematic configuration of one embodiment represented by the flow chart of FIG. 1 is operation
An instruction fetch register that stores three codes and operands (actually addresses), 2 is a main memory unit that stores programs and data, and 3 is an address fetch that fetches (fetches) data etc. by accessing the main memory unit 2. Circuit 4 is an operation in the instruction word register
An instruction control circuit 5 for controlling the flow of data, timing, etc. by code is an arithmetic unit for adding a calculation to the tag portion of the operand to generate a branch destination address. As shown in FIG. 1, five data registers and 1 bit each
It consists of a shifter and an adder.

The instruction is sent from the main memory unit 2 to the instruction word register 1 via the address fetch circuit 3. The address fetch circuit 3 fetches the operand from the main storage unit 2 according to the address code of the operand in the operand, and sends the operand to the address calculator 5 via the address fetch circuit 3. From the operation code in the instruction word register 1, a signal is sent to the instruction control circuit 4, and from there, a control signal is sent to the address fetch circuit 3 and the address calculator 5.

With the schematic configuration as described above, the branch destination address is obtained, and the control of the program shifts there.

FIG. 1 is a diagram showing the detailed configuration of FIG. With the configuration of this figure, the process proceeds according to the flow of FIG. It will be described below with reference to the drawings.

First, the instruction (INST) 21 is fetched from the program of the main memory (MS) 2 or more, and the instruction word register (I
R) 1 through the address fetch circuit (AFC) 3. Operation code (OC) of the instruction
11 to the instruction control circuit (ICC) 4 from the control signal 200
Is sent, and control of the process as shown in FIG. 2 is started based on that. From the first operand address (first OPA) 12 and the second operand address (second OPA) 13 of IR1, the first operand (first OP) 22 and the second operand (second OP) 23 are fetched via AFC3, It is sent to the data register (DR1) 51 and the data register (DR2) 52 via the AFC3. At this time, the data of the goal side argument is stored in the DR1 51, and the data of the close side argument is stored in the DR2 52. DR1 51 tag section (T) 511
And the upper 3 bits from the tag portion (T) 521 of the DR2 52, respectively, and sent to the data register 3 (DR3) 53 through the data lines 107 and 108. The data format in this register is shown in FIG.
The high-order 3 bits (B1) 531 in the bit data are formed by the goal side, and the low-order 3 bits (B2) 532 are formed by the bit group of the tag on the close side.

The 6-bit data that has exited here is sent to the 2-bit bit shifter (BS) 54 through the data line 109. In this BS 54, 6-bit data is shifted to the left by 2 bits and 0 is substituted for the rightmost 2 bits to be converted into 8-bit data.

This 8-bit data is input to the address adder (ADDER) 56 through the data line 110. ADDE
The other input of R56 is fetched from the third OPA 14 of IR1 through AFC3 and is input from the data register (DR4) 55 through the data line 111 to the third O3.
P24, which is the origin (RATO) of the routine address table (RAT) 25 shown in FIG.
It is an address indicating 26. (The two inputs of ADDER 56 are added together to store the above RAT stored in MS2 via data register 57 and AFC3.
This is an address pointing to the entry 27 of 25. That is, the 8-bit data output from the BS 54 represents the displacement 28 of the entry 27 from the RATO 26. In this entry 27, a branch destination address (BDA: branch destination address) 27 'is stored.

Since the branch destination address has been obtained by the tags in the argument data on the goal side and the close side, the program is branched to the routine indicated by BDA27 'under the control of ICC4 according to OC11 in IR1. Incidentally, B
DA27 'is an address on the MS2 where a processing routine corresponding to a combination of arguments is stored.

As described above, in the configuration of FIG. 1, according to the flow of FIG. 2, branching is performed by an argument with only one instruction.

The individual commands, data, and tables in FIG. 1 will be described below with reference to the drawings.

First, FIG. 4 shows the format of the instruction word in IR1. From the left, the operation code 11 of the dedicated instruction, the first operand address 12 indicating the address where the goal side argument data is stored, the second operand address 13 indicating the address where the close side argument data is stored, It is a third operand address that represents the origin (start address) of the routine address table (table on main memory in which branch destination addresses are stored). 1
From 1 to 12, the control signal 200 to the instruction control circuit 4, 12,
From 13 and 14, data signals (1021, 1022 and 1023, respectively) are output to the address fetch circuit 3.

FIG. 5 shows the first and second operand addresses 12, 13
And fetched by the address fetch circuit 3. This indicates the data format of the first and second operands.
This is also the content of the data registers 51, 52 of FIG. The data format is the same for both the goal side and the close side, and the length of the entire data including the tag part is 4 bytes (32
Bit), of which the upper 1 byte (8 bits) is the tag part 5
11, the remaining lower 3 bytes are the data portion 512. In the present embodiment, only the upper 3 bits of the 8-bit tag are used to identify the type of argument for branching. In the case of the data stored in the data registers 1 and 51, the upper 3 bits are taken out as the data signal 107, and the upper 3 bits 531 of the data register 53 are extracted.
Will be input. Note that the number of bits (sub) of the tag (used for identifying the type of argument) to be taken out is not limited to 3 bits, and may be any number as long as it is 8 bits or less depending on the case.

FIG. 6 shows the internal format of 6-bit data in the data register 53. The high-order 3 bits 531 from bit 0 to bit 2 are created by inputting the high-order 3 bits of the tag as a data signal 107 from the data register 51 in which the argument on the goal side which is the first operand is stored.
Similarly, the lower 3 bits 532 from bit 3 to bit 5
Is generated by inputting the upper 3 bits of the tag as the data signal 108 from the data register 52 that stores the argument on the close side that is the second operand. The 6-bit data thus created is sent to the bit shifter 54 as the data signal 109.

FIG. 7 shows a routine address table 25 in which the addresses of branch destination routines are stored. As described above, this table is taken in a continuous area in the main memory, and its origin 26 is indicated by the third operand. The 8-bit data produced by the tags of the first and second operand is the displacement 2 from the origin.
8 and is added to the third operand, the result is the address indicating entry 27 in the table.
The address (branch destination address 27 ') of the branch destination routine corresponding to the combination of the arguments is stored in this entry, and the program branches to this address. There are 64 entries 27, which is the number of combinations of 3 bits and 3 bits, and the contents may have the same address, and the address of the process corresponding to the combination of the arguments is arranged. See also this entry 27
Has a width of 4 bytes (32 bits), and even if the address is stored in 32-bit addressing mode, the upper 8
It may be stored in a 24-bit addressing mode in which the bit is used as some control bit. Table 2
Entry 27 of 5 exits the address adder 56 and goes through the data register 5 and the address fetch circuit 3,
It is pointed to by the data signal 106.

In the above-described embodiment, the upper bits of the tag of the reference are taken out, arranged, and then shifted to form the address. However, there are other methods for forming the address by the tag in the present invention, and a device corresponding thereto can be considered. As a second embodiment, an apparatus different from the above embodiments will be described below with reference to the drawings.

First, according to FIG. 3 which shows the schematic structure of the device, the part forming the address by the tag is a part of the address calculator 5, and the structure of the other parts is the same as that of the first embodiment. The detailed structure of the apparatus is shown in FIG. In the figure, the part surrounded by the broken line is different from the previous embodiment, and the other parts are the same as in FIG.

The signal flow will be described. First, the tag portions of the data register 51 and the data register 52 are connected to the signal line 10 respectively.
It is input to PLA (Programmable Logic Array) 58 through 7 and 108. PLA58 is ICC4
From the control signal 206. The PLA 58 selects an output corresponding to the combination of input tags. Its output is the address formed by the tag and, in the previous embodiment, the bit shifter 5 of FIG.
It corresponds to the output of 4. As mentioned above, this address is a displacement 28 from the origin 26 of the branch destination address table 25.

The subsequent processing is the same as that in FIG. 1, and the output address from the PLA 58 is transferred to the data register 5 through the data line 113.
Sent to 9. The data register 59 controlled by the control signal 207 from the ICC 4 feeds the address signal through the data line 114 as one input of the address adder 56.

After that, the configuration and the signal flow are the same as in FIG. 3, and are the same as in the previous embodiment. In this embodiment, the number of bits of the tag fetched from the data registers 1 and 2 is not limited to 3 bits as in the previous case, but can be freely selected as long as it is 8 bits or less. Also, the output address of the PLA 58 is not limited to 8 bits as in the previous time, but may be any number of bits.

〔The invention's effect〕

According to the present invention, it is described by a conventional program, requires several steps, and has two arguments in the goal side and the close side.
The process of reading the tag portion from the data in which the same process is repeated every time can be executed simultaneously in one step on the goal side and the close side, including the branching process. Since this processing is performed for each argument of the predicate and for each element of the list, the processing is performed several times during one unification of the corresponding predicates. Therefore, the number of times this process is performed during execution of Prolog is very large. Therefore, this process has a large ratio in the whole Prolog execution process. From this, the speeding up of the process of "data determination by tag, process branching" according to the present invention has a very great effect on the improvement of the execution speed of Prolog.

[Brief description of drawings]

FIG. 1 is a diagram showing a detailed configuration of the first embodiment, FIG. 2 is a flow chart of processing in the first embodiment, FIG. 3 is a diagram showing a schematic configuration of the embodiment, and FIG. 4 is an instruction. FIG. 5 shows the format of the word, FIG. 5 shows the format of the data of the first and second operands, and FIG. 6 shows the internal format of the 6-bit data in the data register (53 in FIG. 1). Figure showing,
FIG. 7 is a diagram showing a branch destination address table (routine address table), and FIG. 8 is a diagram showing a detailed configuration of the second embodiment. 5 ... Address calculator, 53 ... Data register, 54 ...
Bit shifter, 56 ... Address adder, 58 ... PL
A.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Mori 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Shuichi Sato Examiner, Central Research Laboratory, Hitachi, Ltd.

Claims (1)

[Claims] 1. An inference computer for unifying processing of an argument which is a kind and an argument which is a goal and a close argument which is provided in the data including the argument, and the goal argument and the goal argument are combined by one instruction. The argument which is closed is read, and the upper bits of the displacement from the start address of the table in which the branch destination address is stored are formed from the tag part of the argument which is the goal, and at the same time, the lower side of the displacement. Means for forming the bit group from the tag portion of the argument which is the closing, and control to the routine corresponding to the address obtained by adding the head address of the table storing the branch destination address and the formed displacement. An inference computer having means for transferring.