JPS6162141A - Logic-type information processing device - Google Patents

Abstract

PURPOSE:To realize the bidirectionality of an argument even in the four arithmetical operations which use a unidirectional built-in predicate and thus to improve performance of the device, by performing the alteration of operations by an alteration of codes and by implementing alteration in the sequence of arguments through the use of hardware. CONSTITUTION:At the first word of a register file 214, a tag B, which indicates a built-in predicate, and a code which indicates addition are set, and respective arguments are set at the 2nd-4th words. Then a code 223 of the built-in predicate, its tag 235 and tags 232-234 of the respective arguments are given as inputs to a decorder 210. When, for instance, the 1st argument is an unknown number and the 2nd and 3rd arguments are constants, a decoder 210 outputs the code of subtraction to a signal line 73 and instructs to carry out subtraction. At this time, further, selectors 211-213 are selected so that the 3rd, 2nd and 1st arguments are outputted to signal lines 74, 72, and 71 respectively through signal lines 220-222. Therefore, when the present device is given, as a target, 'Unknown number+constant 1=Constant 2,' the device executes 'Constant 2-constant 1=Unknown number.' In this way, addition can be performed, regardless of whichever of the 1st-3rd arguments may be an unknown number and thus the bi-directionality of the argument is assured.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logical language prologue (PROLOG) in which the main data to be processed is not numerical values but symbols.
), especially when executing the four arithmetic operations as predicates built into the information processing device, any two values of two operands and one result. The present invention relates to a logic type information processing device having a function of being able to perform four arithmetic operations when given.

[Background of the invention]

Prolog is a programming language that expresses relationships between things in the form of predicates. In the prologue, execution begins by giving a question to the program (a set of predicates), and the processing system automatically determines the truth or falsehood of the question without explicitly describing the procedure to obtain the answer to the question in the program. The way it is derived is very different from existing programming languages (for example, Fortran, Pascal).

For a detailed explanation of such a logical language prolog, see "programming in prolog"
,F.

C1ocksin / written by C,S, Mellish,
apringet-Verlag, 1981
, etc., so only the points related to the present invention will be explained here.

A prologue program is a collection of predicate definitions, and the predicate definitions include predicates defined by the programmer (user-defined predicates) and predicates built into the prolog processing system (built-in predicates). Built-in predicates include predicates that are difficult to define by user predicate definitions, ie, predicates related to arithmetic operations, input/output, and the like. One of the major differences between user-defined predicates and built-in predicates is that arguments of user-defined predicates are bidirectional, whereas arguments of built-in predicates are unidirectional. That is, in a user-defined predicate, there is no distinction between input and output for variables that appear as arguments, and it is not necessary that a value is already bound (bird) to the variable at the execution stage. In addition, in the built-in predicate, there is a distinction between human and mountain power because of the change that is q, and there is always a value for power change at the execution stage! , K must be bound9), However, since the argument a of the first-order predicate thesis on which Zorog and Q is based is the original unaccounted direction note, the bidirectionality of the argument also applies to the at-included predicate. It is necessary to guarantee gender. So let's take a look at addition, which is a typical introductory statement. To ensure bidirectionality of arguments, Vζ, °subprogram p as shown in Figure 1 is used.
lus 't: create. However, inLegar in the same figure
(X).

var(X), add(X, Y, Z), 1u
b(X, Y, Z) is true if X is an integer, true if X is a variable (value is not bound), true if X and Y are known and Z=X+Y, and true if X and Y are known. If 2-factor X-Y is true, these built-in predicates have no bidirectionality of arguments, and the inputs &aX and Y must be bound. However, the user-defined addition predicate plug in FIG. 1 can perform the operation even if any of the three arguments a When an integer is bound to 2((1-'s first.second pl
In the definition of g, integer(X) is false, so it is not executed, and in the third definition, tnteger(X), va
When both r (Y) and integer (Z) are true9, the variable Y is given (bound) Y=Z-X by sub (Z, X, Y), and the process ends. Similarly, when the other X or Z is a variable, the second definition or the fourth
It can be executed with the definition of , and it can be executed regardless of which variable is the output variable. We were able to define a bidirectional addition plus using a unidirectional built-in predicate. It is clear that the same applies to subtraction, 1 multiplication, and division. As described above, in order to guarantee the bidirectionality of the arguments of the four arithmetic operations, it is sufficient to create a subprogram. However, using frequently used predicates in the form of subprograms leads to a decrease in execution speed. Another problem is that the burden of creating subprograms increases on the user.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logical information processing device that allows arguments to be bidirectional even for built-in predicates of four arithmetic operations that are defined in advance and provided to the user.

[Summary of the invention]

In a logical type information processing device, the built-in predicates of the four arithmetic operations are executed in the same way as the four arithmetic operation instructions of the conventional information processing device. That is, a code corresponding to each operation is generated, input data is processed according to the code, and the result is output. Therefore, in the present invention, by changing the operation as described for the case of addition in FIG. 1 by changing the code, and by changing the order of arguments by hardware, it is possible to This method uses implicit predicates to realize bidirectionality of arguments in the four arithmetic operations.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail.

FIG. 2 is an overall configuration diagram of a logical information processing device, in which a storage device 1 stores a prologue source program converted into an internal format suitable for execution.

The identification device 2 is a device that performs unification between the target taken out from the storage device 1 via the signal line 13 and the head taken out via the signal line 14, and the arithmetic device 3 unifies the target taken out via the signal line 14. If there is, connect signal line 7 from synchronization device f2
It is a device that performs arithmetic operations on the code and argument of the built-in predicate sent via the signal line 8, and the result is transmitted to the identification device 2 via a signal line 8. The control device 4 receives information on the success or failure of the unification performed by the identification device 2 via the signal line 9, and then identifies the target and head to which unification is to be performed via the signal line 10. to device 2. The temporary storage device R5 holds the values bound to the variables by the unification performed by the identification device 2, and the information held here is given to the identification device 2 via the signal line 12. , the information to be held in the temporary storage device 5 is given by the signal lineman 1. The present invention is applied to the identification device 2 among these devices.

FIG. 3 is an internal configuration diagram of the identification device 2. The target reading device 201 is a means for retrieving the target designated by the signal line 10 from the storage device 1. If there is a variable, its value is retrieved from the temporary storage device 5. The head reading device 202 is a means for retrieving the head specified by the signal line 10 from the storage device 1. If there is a variable with a bound value in this head, the value is stored in the temporary storage. 5
) Take it out. The unification circuit 203 is a means for unifying each of the target and head arguments taken into the target and head reading devices 201 and 202. The interface 204 signals the success or failure of unification to the control device 4 based on the unification result sent via the signal line 207 or the execution result of the built-in predicate sent via the signal line 8. It is a means for notifying via a line 9 and storing the value in the temporary storage device 5 via a signal line 11 when a value is bound as a result of the 22 cation.

FIG. 4 shows an arithmetic unit 3 that executes built-in predicates for four arithmetic operations.
is shown in detail. The arithmetic circuit 301 is the operand (first
Execute one of the four arithmetic operations using the operation code obtained from the argument, second argument) and the signal line 73, and send the result to the signal line 303.
sb, the identification circuit 302 is a means for outputting to the arithmetic circuit 3.
This is a means for unifying the calculation result obtained from 02 and the third argument. The four arithmetic operations executed by this arithmetic device 3 are addition add, subtraction sub, and
Multiplication mul and division div, both of which are input X.

Let Y and output be Z. That is, the argument is unidirectional.

Table 1 FIG. 5 shows the word format used in this device.

One word consists of a tag part 20 and a data part 21. The tag part represents the word classification as shown in Table 2, and the data part shows an integer value when the tag is an integer, a variable number when the tag is a variable, When the tag is a built-in predicate, it has the code for the operation.

Table 2, FIG. 6 shows an embodiment of the present invention, and shows in detail the inside of the target reading device 201 in the identification device 2 described above. In the same figure, the register file 214
stores four words of the data or program read from the storage device 1 or the temporary storage device 5. Signal line 232,2
33, 234 and 235 output the tag part of the register file 214. Signal lines 223, 226, 227, 228
outputs the data portion of the register file 214.

The selectors 211, 212, 213 are connected to the decoder 210, the signal lines 220, 221, 222, the signal lines 226,
227 or 228, and as a result, the order of the arguments given to the arithmetic unit 3 is changed. Data 210 is four word tags 235, 234, 2 of register file 214.
33,232 and first word data (operation code) 223
Then, the selection contents of the selectors 211 to 213 are determined as shown in FIG. 7, and each argument is outputted to the arithmetic unit 3 of FIG. 4 together with the operation code 73 to be executed. The operation of the above embodiment will be explained using addition as an example. Register file 2
When the tag B indicating the built-in predicate and the data (code) indicating addition are set to the first word of 14, and each argument is set to the second to fourth words, the built-in predicate code 223 and its tag 23 are set.
5. Tags 232, 233, 234 of each argument are decoder 2
10 inputs. The decoder 210 operates as shown in FIG. 7. For example, when the first argument is an unknown number (tag is V) and the second and third arguments are constants (tag is engineering), a subtraction code sub is sent to the signal line 73. Outputs and instructs subtraction. Furthermore, at this time, the signal lines 74, 72, and 7iK are connected to the third signal lines 220, 221, and 222, respectively. Second. The selectors 211, 212, and 213 are controlled to output the Ml argument. As a result, the logical information processing device has the goal of (
When unknown number) + (constant 1) = (constant 2) is given, (constant 2) - (constant 1) = (unknown number) is executed. In this way, the first ゜second □
Even if any of the third arguments is unknown, the addition operation can be performed, and the bidirectionality of the arguments is guaranteed. This is guaranteed for all additions, subtractions, multiplications, and divisions in which the decoder 210 functions as shown in FIG. In contrast, conversion of built-in predicates and variables as shown in FIG. 8 is executed. However, in the same figure? It is assumed that n represents a variable and C1 represents a constant.

〔Effect of the invention〕

According to the present invention, in a logic type information processing device suitable for the logic board programming language Prologue, bidirectionality of arguments in four arithmetic operations can be guaranteed by hardware, so that a programmer can easily respond to four arithmetic operations. This eliminates the trouble of creating an extra subprogram to ensure bidirectionality of arguments, and there is no overhead of executing that subprogram each time the four arithmetic operations are performed, thus improving the performance of logical information processing devices. There is an effect.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a program for giving bidirectionality to the argument of a built-in predicate, Figure 2 is an overall configuration diagram of a logical information processing device, and Figure 3 is the identification device in Figure 2. 2, FIG. 4 is a block diagram of the arithmetic unit 3 that processes the built-in predicate in FIG. 2, and FIG. 5 shows the word format of the logical information processing device in FIG. 2. Identification device, 3... calculation device,
201...Target reading device, '210...Decoder,
211, 212° 213...Selector, 214...
register file.

Claims (1)

[Claims] 1. When the first and second arguments are given as constants and the operation code of the four arithmetic operations is specified, the operation result corresponding to the operation code is given to the third argument and output. However, the calculation means, the input codes for the four arithmetic operations, and the first, second, and third codes, two of which are input constants and one is an output variable.
The order of the input arguments and the above are equivalent to the algebraic relationship between the three input arguments determined by the input code when the input arguments are given, and the output variable is the third argument. 3 after changing the input code and making the change
and target reading means having a function of providing two arguments and an operation code to the arithmetic means. 2. The target reading means includes a decoder that outputs an operation code to be output and a selection signal based on the content of the input code and information on which of the three input arguments is an output variable; Claim 1 characterized in that it has a selector that selects and outputs what should be output as the first, second, and third arguments from the three input arguments.
The logical information processing device described in Section 1.