JP2714015B2 - Logic circuit synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a logic circuit synthesizer for automatically synthesizing a logic circuit, and particularly relates to a register transfer level (hereinafter referred to as “RTL”). The present invention relates to a logic circuit synthesis device that synthesizes a logic circuit including a predetermined operation based on a functional description.

(Prior Art) In recent years, with the increase in the scale of LSIs, systems for automating logic design with computer support have been developed with the aim of improving design efficiency. Generally, these design support systems automatically synthesize a logic circuit based on a hardware description language. Among them, as a hardware description method for realizing a relatively high-level interface with a designer, a logic description method is used. Methods for describing the operation and function of a circuit are known. The RTL function description is one of them.
The required logic circuit is described by describing the type of operation required, input / output terminals, state of state transition, and the like.

In a conventional logic circuit synthesizer that synthesizes a logic circuit from an RTL description, first, the description is analyzed to identify necessary operations, an operation table is created, and then the same type of operation described in a plurality of places in the description is described. On the other hand, a method has been adopted in which a logic circuit is synthesized by sharing a common input or an exclusive execution condition as a common arithmetic unit. That is, in the description using the state transition, since the two states are not taken at the same time, the execution condition of the operation described as the operation in the separate states is exclusive. For example, STATE1: C = ADD (A, B) (1) F = ADD (D, E) (2) STATE2: I = ADD (G, H) (3) Because of the transition state, the operations of (1) and (3) and the operations of (2) and (3) are operations whose execution conditions are exclusive. In such a case, either one of the operations (1) and (3) and the operations (2) and (3) can be shared. Conventionally, how this sharing is performed depends on the system. Was completely left to his judgment. Therefore, the logic circuit intended by the designer is not synthesized, which may cause confusion in the design process. That is, the designer usually describes a schematic block diagram based on empirical knowledge in design, such as the area and speed of a logic circuit, and then describes the RTL. On the other hand, the system does not consider such points and shares computations from the aspect of mere mechanical sharing. For this reason, the logic circuit synthesized from the description of the RTL differs from the block intended by the designer, and there is a problem that a logic circuit having a desired area and speed cannot be synthesized.

(Problems to be Solved by the Invention) As described above, in a conventional logic circuit synthesis apparatus that synthesizes a logic circuit by describing RTL, the operation circuit intended by the designer is not shared, and as a result, the desired logic There has been a problem that circuits cannot be synthesized.

The present invention has been made to solve the above-described problem, and has as its object to provide a logic circuit synthesis device that synthesizes a logic circuit from RTL while achieving desired sharing.

[Configuration of the Invention] (Means for Solving the Problems) The present invention extracts information on an arithmetic function from a function description of a register transfer level of a logic circuit to be synthesized, and converts the information to specify an operation to be shared. Calculation specifying means for specifying information to be shared among the extracted information on the calculation functions based on the calculation function, and a logic circuit for synthesizing a logic circuit while sharing the calculation portion based on the specification information of the calculation specification means And a synthesizing means.

(Operation) According to the present invention, an operation extracted from an RTL description is shared based on a designation from a designer or a design support system (design support system for generating an RTL structure) higher than RTL. The logic circuit is synthesized while the data is being converted. For this reason, it is possible to synthesize a logic circuit intended by the designer or a logic circuit suitable for designation of a higher-level system.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a logic circuit synthesis device according to this embodiment. This apparatus comprises an RTL description storage unit 1, an operation designation command input unit 2, and an operation designation unit 3.
And shared logic circuit synthesis means 4.

The RTL description storage means stores a description of the logic circuit to be synthesized by RTL. The example of the RTL description stored here is
Shown in the figure. The first line is the declaration section of the module name SUM,
Lines 2 and 3 are 1-bit input terminals named CLOCK,
This is a declaration section of an 8-bit input terminal named A, B, D, E, G, H. The fourth line is a declaration section of an 8-bit output terminal named CO, FO, IO. The fifth line is an 8 bit output terminal named C, F, I.
Declaration part of bit register. The sixth line is AUTOMATION
This is a declaration part of a state transition description named, indicating that the state transition is performed in synchronization with the rising timing of CLOCK. Lines 7 and 8 show the operation contents in the state named STATE1, and the input terminal named ADD
The operation of adding A and B and transferring the result to register C and input terminals D and E
Is added and the operation of transferring the result to the register F is performed. The ninth line also indicates that an operation of adding the input terminals G and H and transferring the result to the register I is performed in a state named STATE2, similarly to the seventh and eighth lines. Also, 11-15
The line indicates the operation that is always executed regardless of the state, and indicates that the contents of the registers C, F, and I are always output to the output terminals CO, FO, and IO, respectively.

The operation specification specifying means 3 first analyzes the RTL description as described above, identifies necessary operation units, and creates an operation table as shown in FIG. 3, for example. This operation table includes operation identification numbers assigned in the order in which the operations are described,
4 is a table describing types of operations appearing in the description, input / output data of the operations, and execution conditions of the operations.

The operation designation command input means 2 is an input means such as a keyboard, for example, for designating an operation which the designer wants to share with reference to the operation table as described above. This designation is made by, for example, an MRG (merge) command specifying one or a plurality of operation identification numbers in the operation table, as shown in FIG. Here, when one operation is specified by the command, the specified operation is generated as one arithmetic unit. For example, the command in FIG. 4 indicates that the operation of the operation identification number 1 and the operations of the operation identification numbers 2 and 3 are each realized by one adder.

The operation specifying means 3 creates a command storage table as shown in FIG. 5 from the operation table shown in FIG. 3 based on the specification of such sharing of the operation. This command storage table is a table that stores a command number j, the number of operation identification numbers included in the command (the number of identification numbers) CSUM, and an operation identification number included in the command. Here, the command number j indicates that the command is the j-th input command.

The shared logic circuit synthesizing unit 4 performs a sixth operation on the operation table and the command storage table created by the operation designating unit 3.
The processing as shown in the figure is executed.

That is, the number of commands (CNUM
= 2) (S1), and initialize the internal variables i, j to 1 (S1).
2, S3). Next, the identification number CSUM of the command number j (= 1) is obtained from the command storage table of FIG. 5 (S4), and the adder j
Is generated (S5). Here, if CSUM is 1, the process of step S16 is performed, and if CSUM is 2 or more, the process of step S7 is performed. In command number 1, since CSUM = 1, step S16 is executed. That is, after calculating the operation identification number 1 stored in the command number 1, the third
The output data and the input data 1 and 2 of the addition of the operation identification number 1 are obtained as C, A, and B from the operation table shown in the figure, and the output of the adder 1 is C, the input 1 is A, and the input 2 is B Connecting. Thus, an adder 1 (11) shown in FIG. 7A is generated.

Next, since j <CNUM (S14), j is incremented to j = 2 (S15). Then, the process returns to step S3, where i is initialized to 1 and the command number 2 in the command table is set.
The number CSUM (= 2) of the identification numbers is obtained (S4), and FIG. 7 (a)
Is generated (S5). Here, CS
Since UM = 2, two inputs of selectors 1 (13) and 2 (14) are connected to each input of the adder 2 (S7). Subsequently, 2 which is the operation identification number of j = 2 and i = 1 is obtained from the command storage table of FIG. 5 (S8), and the output data and the input data of the addition of the operation identification number 2 are obtained from the operation table of FIG. 1, 2 are obtained as F, D, E, respectively, and F is connected to the output of the adder 2 (S
9), each input D1 of the two selectors generated in step S7
Are connected to D and E respectively (S10). Next, operation identification number 2
STATE1, which is the execution condition of the addition of the SEL, is obtained from the operation table of FIG. 3, and the signal STATE1 corresponding to the execution condition is connected to the select terminals C1 of the two selectors (S1).
1). Subsequently, i is set to 2 in steps S12 and S13, and step
The processing of S8 to S11 is performed in the same manner as described above, and I is output to the output of the adder 2 and the two selectors 1, 2 generated in step S7
G and H are connected to the input D2, respectively, and the signal STATE2 is connected to the select terminals C2 of the selectors 1 and 2, respectively. Further, the processing ends through steps S12 to S14.

As a result of the above processing, a logic circuit as shown in FIG. 7A is synthesized.

The above is an example in which the operation identification numbers 2 and 3 are shared by the same operation unit. However, when the sharing of the operation identification numbers 1 and 3 is specified, the logic as shown in FIG. The circuit is synthesized.

As described above, when synthesizing a logic circuit that realizes its function from the RTL description, it becomes possible for the designer to specify the assignment of arithmetic units for the synthesis system of the logic circuit, and the logic circuit intended by the designer Can be accurately synthesized.

The present invention is not limited to the embodiments described above. In the above embodiment, the sharing of the operation was designated by inputting a command specifying the type of the computing unit and the identification number. However, this sharing instruction is described, for example, as shown in FIG. The operation may be performed by adding a subscript of the operation. In this case, since there is no need to input a command, the burden on the designer is reduced.

In the above embodiment, the operation to be shared is specified in the form of a command input by the designer or added to the description of the RTL. However, this specification is applied to a design support system (an RTL structure higher than RTL is generated). (A design support system). For example, in the upstream system,
If it is possible to obtain information that it is appropriate to merge which operations, this information can be effectively used.

In the present invention, it goes without saying that the type of operation, the number of input / output terminals, and the number of selectors used are not limited to the examples described above. When instructions for all the operations are not required, an instruction for sharing may be issued only for a specific operation, and the same combination processing as that of the related art may be performed for other operations. For example, all of the identification numbers used in the command storage table are stored, and when the processing of the present invention for the specified arithmetic unit is completed, the row of the previously stored identification number is deleted from the operation table. The conventional technology may be applied to the RTL description after this.

[Effects of the Invention] As described above, according to the present invention, an operation to be shared can be specified for a functional description of an RTL, and a logic circuit intended by a designer or a higher-level system can be synthesized. Effective design support can be provided.

[Brief description of the drawings]

1 to 7 are diagrams for explaining a logic circuit synthesis device according to an embodiment of the present invention. FIG. 1 is a block diagram of the device, and FIG. 2 is stored in RTL description storage means. FIG. 3 is a diagram showing an RTL description, FIG. 3 is a diagram showing an operation table created by an operation designation unit, FIG. 4 is a diagram showing an example of a command input by an operation designation command input unit, and FIG. FIG. 6 is a flowchart showing a processing procedure in the shared logic synthesizing means, FIG. 7 is a diagram showing an example of a logic circuit synthesized by this apparatus, and FIG. FIG. 11 is a diagram illustrating an RTL description in a logic circuit synthesis device according to another embodiment of the present invention. 1 ... RTL description storage means, 2 ... calculation designation command input means, 3 ... calculation designation means, 4 ... shared logic circuit synthesis means.

Claims (1)

(57) [Claims] 1. A method for extracting information relating to an arithmetic function from a function description of a register transfer level of a logic circuit to be synthesized, and for sharing information among the extracted information relating to an arithmetic function based on information designating an operation to be shared. A logic circuit comprising: an operation designating unit for specifying information to be processed; and a logic circuit synthesizing unit for synthesizing a logic circuit while sharing the operation part based on the specification information of the operation designating unit. Synthesizer.