SU805322A1 - System for automatic design and control of technological processes in microelectronics - Google Patents

Description

mi This system allows the automatic design of integrated circuits according to predetermined models and the management of photomask manufacturing processes or directly the components of circuits, for example, using the 2j electronic lithography method.

The inability to perform an automated synthesis of a model from fragments and fixing this model in a structure is a disadvantage of the known system, leading to a decrease in its efficiency, especially when used in a collective use system.

The purpose of the invention is to increase the efficiency and expand the functionality by implementing the mode of forming a model from fragments and fixing this model in the structure.

The goal is achieved by the fact that a digital structure adjustment code converter is connected in two-way communication with the central processor and connected to the control input of a block of models and constants, and a model synthesis device, the first input and output of which are connected to the corresponding output and the input of the central processor, the second input of the model synthesis device is connected to the output of the block of models and constants, and the second output is connected to the input of the converter codes for setting the digital structure urs.

In addition, in the system, the model synthesis device contains a control unit connected by two-way communication with comparison, character storage, storage of mnemonic signs, disjunction formation, conjunction formation, combinational circuit optimization, and with a memory block that is connected by two-way communication by the formation of a conjunction, the formation of a conjunction, the storage of a mnemonic sign and the block of optimization of combinational circuits, the outputs of which are connected respectively to the first inputs of the formation of the dis of the function and the conjunction shaping unit, the second inputs of which are connected to the second input of the device, the first input of which is connected to the first inputs of the control and memory units, the first inputs of which are connected to the first output of the device, the second output of the memory unit is connected to the second output of the device, the output of the storage units signs and storage of mnemonic signs are connected to the inputs of the comparison unit.

FIG. 1 is a schematic of the system; Figure 2 shows an example of the implementation of a model synthesis device.

The structure of the device includes: central processor 1, block 2 models and constants, block 3 of logical modeling, block 4 of design of topology, block 5 of analysis and modeling of circuits, device 6 for synthesis of models, converter 7 kOds for adjusting the digital structure, device 8 for input- output terminal 9.

The device 6 for synthesis of models consists of a control unit 10, a memory unit 11, a storage unit 12 for pseudo-symbolic characters, a comparison unit 13, a feature storage unit 14, a conjunction formation unit 15, a disjunction generation unit 16, an combinational circuit optimization unit 17, numerals 18 and 19 denote the first input and output of the device, numeral 20 - the second output of the device and numeral 21 - the second input of the device.

The central processor 1 controls the operation of the system in the time division mode. Unit 2 of models and constants is intended for storing descriptions of models and constants of approved solutions of design problems. Unit 3 checks the operability of the designed functional diagrams. Block 4 of the design topology solves the problem of locating elements of the LSI, tracing interconnects, and also provides control information for the terminal devices 9. Block 5 checks the operability of the Topology analogues designed by the system. Device 6 synthesizes logical, topological and circuit models of the developed computer node. Converter 7 generates control signals for rearranging the digital structure of the block 2 models and constants. The input-output device 8 provides for the exchange of information between the central processor 1 and the terminal devices with the implementation of parallel operation of a variable set of subscriber equipment. Terminal devices 9 are designed for individual work of developers with the system. As part of any of the devices 9, an executive processor is required.

Block 10 controls the operation of the model synthesis device. The memory unit 11 is intended for storing a task for a projected scheme for storing intermediate data of model synthesis. Block 12 is designed for the operational storage of decrypted mnemonic characters describing the designed scheme. Block 14 is designed to store a set of character codes of the alphabet description of the scheme. Comparison unit 13 checks the coincidence of the contents of block 12 and

block 14. The conjunction shaping unit 15 and the disjunction shaping unit 16 fix the dimensions of the conjunction and disjunction, respectively, taken as a result of the decryption of the design scheme description, analyze for the presence in the unit

2 models and constants of elements, reusable conjunctions and disjunctions, as well as the synthesis of multi-input conjunctions and disjunctions from elements stored in a block

2 models and constants. Combination circuit optimization unit 17 is designed to synthesize circuits of an acceptable order on existing or possible physical elements.

The system works as follows, i

A program containing a description of the functional LSI, the most important temporal relations of the system of test parameters, electrical requirements for individual nodes and elements, some technological features and topological restrictions, data on the geometric dimensions of the crystal, as well as indications of the most specific circuit-related structural characteristics of the LSI designed for the implementation of a full cycle of design-manufacture, and to perform a partial cycle, which is necessary for the operation vnogo selection opti-mal circuits designed for this

The central processor 1 initiates an input operation with a command that accesses the device 8 i.vodood output. The latter transmits, from the devices 9, information for designing the LSI to the central processor 1, which uses the system of priorities to determine the sequence of solving the incoming tasks. Then, the initial data of the LSI design tasks are translated into the operational data of the system blocks.

Upon completion of this operation, the CPU 1 transmits the control information and the translated source data of the first task to the block.

3 logical modeling. The latter selects the logical element models in block 2 and makes a logical model out of them corresponding to the designed circuit, and then block 3 performs a simulation consisting in determining the output states of the elements depending on the input signals, taking into account the special requirements of the time ratios.

At the end of the logical simulation, the results obtained are automatically brought to the standard form and sent through the central processor 1, the input device 8, the water to the terminal device 9

appropriate developer. After that, the central processor; 1 starts block 4 of the design of the topology and transfers to it the initial data for the design of the topology of the developed .SI.

At the same time, the central processor unit 1 starts the logical modeling unit 3 and transmits to it the input data of the next priority design task.

Q

In the absence of a model of an element of the designed circuit in block 2, the logic simulation block 3 generates a request signal to the central processor 1. The device starts up the model 6 synthesis model 6 and transmits to it all the input information about the designed LSI.

Up to the initial data on the projected LSI received from the central processor 1, as well as information

0 blocks 2. models and constants, device b synthesizes logic, topological and circuit models missing in block 2.

At the end of the synthesis of models, device 6 transmits information on new models to the converter 7. The latter produces a system, up. equalizing signals for rebuilding certain arrays of digital

0 of the block 2 structure. After fixing the synthesized models in the block 2 structure, the converter 7 transfers control to the central processor 1, which at the time of release

5 of the logical modeling unit 3, in accordance with the priority, restores the initial assignment and performs the final logical modeling in accordance with the newly synthesized models.

When the central processing unit 1 transfers the design to the topology design unit 4, the latter requests from the central processing unit 1

5 information necessary for the design of the topology (description of the scheme, the geometric dimensions of the crystal, an indication of the technology of the scheme). After deciphering the information, block 4 notes in block 2 models and constants the topological structures required by the description of the scheme and taking into account the schematic and structural-technological-. These restrictions imposed by the features of the designed circuits and the technological base of production, carries out their placement and routing of interconnects on a chip of a given geometrical dimensions. When designing a topology,

0, if necessary, the developer has the opportunity to adjust it with the help of interactive tools included in the composition of the terminal devices 9, thus achieving an optical

Maximum placement of components and interconnects on a chip.

The signal about the completion of designing the topological layers of the combined photomasks LSI is transmitted from block 4 to the central processor 1 which starts the block 5 for analyzing and modeling the circuits and transmits to it the initial program data (restrictions on the main functional parameters of the circuit: static noise immunity, power consumption, delay times, load capacity, supply voltage ranges of operating temperatures, special electrical requirements, yield percentage, type of technology).

Unit 5 in accordance with the logical structure of the LSI and the actual topological placement of its elements simulates a circuit diagram without its physical implementation. Analysis of this model provides static and dynamic characteristics of the designed LSI.

The resulting functional characteristics of the LSI unit 5 compares with the characteristics required by the developers in the original program. In case of unsatisfactory comparison results, analysis and modeling circuit 5 performs deterministic optimization of the circuit, the result of which is an electrical basic circuit of an LSI with corrected nominal values of its components.

Upon completion of the deterministic optimization, the analysis and modeling circuit 5 performs the calculation of the circuit in order to provide the required yield. The solution to this problem is carried out by statistical modeling. If a certain percentage of usable output satisfies the required, block 5 transfers control to central processor 1, which in turn outputs the results of operation of block 5 (output performance graphs, quality tables, test tables1 for yield estimates, etc.). through the input-output device 8 to the terminal set of the consumer and transfers control to the topology design unit 4. Otherwise, the circuit analysis and simulation unit 5 performs statistical optimization of the electrical LIS circuit diagram in order to obtain such a set of optimal component widths that would provide the required percentage output suitable schemes.

According to the control signal received from the central processor unit 1, block 4 of the topology design, jointly with block 2, corrects the designed topology in accordance with the results of the work of analysis and modeling circuit 5, making changes to the LSI topology model.

The system operation is repeated from the topology design stage.

Such an iterative cycle of topology design - analysis and modeling of electrical concepts is carried out until a circuit is obtained that satisfies the developer for the required & d functional parameters of the LSI and the percentage of usable products. After receiving positive results, the central processor issues signals to blocks 4 and 5, according to which the latter edits the results of the design of the topology and the electrical schematic diagram (a combined topological drawing, drawings of the templates, the description of the electrical schematic diagram, its modes, characteristics, etc.) required by GOST on documentation. At the same time, the topology design unit 4 prepares control information for the manufacture of BIS photo masks, after which the central processor 1 outputs a description of the documentation and control information for the production of a set of photo masks through the input-output device 8 to the terminal devices 9.

In constructing the device, the synthesis of models took into account some features arising from the automation of designing large integrated circuits, namely, the possibility of changing the method. presentation and storage of LSI models; the need to implement in the .block of synthesis models of the algorithm for the synthesis of LIS models; the need for special means of making changes in the representation of models.

The LSI model appears in connection with the need for computer-aided design and technological production of the LSI. As technology improves, there are changes in them that lead to a corresponding change.

Suppose at some moment that the designer works with models M |, M, ..., Mj. In the proposed system, the presentation of these models should be implemented. There may be two ways to implement models, Perviy consists in storing descriptions of all specific models of M., HQt ... t. In other words, in block 2, the divisions and constants of the system have K entries, with each entry corresponding to a description of a particular model. When using any model, the designer o6patasaeTCH to the appropriate description. In another way of presenting models, some blanks (fragments of descriptions) and their KONmoHOBK algorithm are stored in the system. When using models, the designer should describe the layout scheme of the models from the fragments, then run the synthesis algorithm, in pesyjtbTaTe of which the corresponding model will be built.

According to the trigger signal received from the CPU 1, the block

10 control rewrites block

11 from the array of circuit descriptions to the array of decrypted codes, the code of the first character and gives it the sign of logical negation. After that, the signals from the control block 10 of the second character code from the description of the circuit is read into block 12.

The read code is compared in block 13 of comparison with the code of the bracket, which has a logical expression received from block 14. If the codes match, then the sign of the logical variable is entered into the array of decrypted codes. After the E-EOGO, the code is read from the description of the circuit in block 12. the next character of the description and, in the case of the preceding character, the bracket, under the action of signals from the control unit, from the feature storage unit 14, a logical negative code is supplied to the comparison unit 13. If the codes in block 13 of the match I match, the control block 10 records in the array of decoded codes a sign of logical negative, after which the operation of the device is repeated. If in block 13 the codes do not match, the attribute of a logical variable is recorded in the array of decrypted codes. In the case of fixing a logical variable, the next step in the operation of the device is to read the next character of the description from block 11 of memory 12 and alternately analyze it in block 13 comparing for signs of logical negation, logical disjunction, bracket, closing logical expression, sign, end description of the projected scheme. This analysis is carried out by the action of control signals from the control unit, which are fed to the blocks 12, 13, 14

If the comparison block fixes the match of the analyzed sign with the negative sign, then the control block fixes the logical negative attribute in memory block 11, rewrites the next character of the description of the processed circuit into the array of decoded codes with the logical variable sign and fixes the dimension of the received conjunction in the conjunction formation block 15. Thereafter, in block 12 of block 11, the next character of the description of the designed circuit is read out and the analysis is carried out as follows.

in the case of fixation of the logical transient.

When the block 13 compares the comparison of the analysis of a single sign with a sign of logical disjunction, the control unit fixes the dimension of the received disjunction in the disjunction generation unit 16, as well as by means of the central processor 1, analyzes the block 2 models and constants for the element in its library that implements the logical conjunction , the dimension obtained in the previous stages of operation of the device b and fixed in the conjunction formation block 15. To do this, all possible input coefficients of the AND logic elements are read into the conjunction formation block 15 from the block 2 models and constants, and the order of the implemented circuit is calculated for each conjunction of the obtained dimension.

If any calculated value is equal to one, this indicates the presence of 2 models in the block

and constants of the logical element AND, which allows to realize the logical conjunction of the required dimension. The calculated information is recorded in block 11. The operation of the device is repeated from reading to the analysis of the next character of the description of the circuit.

If the comparison unit 13 fixes the match of the analyzed character with the sign of the bracket closing the logical expression, e, then the control unit 10 by means of the central processor 1 analyzes the unit 2 models and constants for the presence in its library of the element implementing the logical conjunction of the dimension the previous stages of operation of the device 6 and the conjunction formation fixed in the block 15. The set of values of the order of the implemented scheme for obtaining a conjunction is calculated and analyzed, and the calculated information is recorded in block 11.

After this, the control unit 10 by means of the central processor 1 analyzes the unit 2 models and constants for the presence in its library of an element implementing a logical disjunction, the dimension of which is obtained at the previous stages of operation of the device 6, is fixed in the disjunction generation unit 16.

Claims (1)

1. Tabarny v.G. Automated system for designing integrated circuits. Lime universities of the USSR, sir. Radio electronics, t. XU1, 1973. I b. 2 ,. USSR Author's Certificate in Application No. 1993565 / 18-24, cl. G 06 F 15/20, 1974.