JP2829043B2 - Method and circuit for determining transfer word number - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology Conventional transfer word number determination circuit (FIG. 7) Problems to be solved by the invention Means for solving the problem Principle of the present invention Explanatory drawing (FIG. 1) Action Embodiment One embodiment of the first invention (FIG. 3) One embodiment of the second invention (FIG. 4) Effects of the Invention [Outline] First byte address and number of transfer bytes , A transfer word number output control display value, which relates to a method for determining the number of transfer words and a circuit using the word number display value in the transfer byte number for each of the number of transfer bits determined by the bit configuration of the transfer word number. , And for the purpose of shortening the signal propagation delay time while reducing the number of circuit elements by using the word number display value, and following or simultaneously with the command word having the number of bytes to be transferred. Is In a data transfer system for transferring a required number of words for data after transferring an address word having a leading byte address of the data to be read, the word count value included in the received byte count, the word count display value +1 and the word number display value +2, and the word number display value and the word number display value + in response to the received byte number and the transfer word number output control display value included in the first byte address.
1 and a signal for selecting any one of the word number display value +2, selecting one of the three values with the output signal, and transmitting the selected value to the data transfer system. And the number of words received via the.

[Industrial applications]

The present invention relates to a transfer word number determination method and circuit for using a transfer byte number and a transfer word number output control value in a start byte address, and a word number display value in a transfer byte number for setting the transfer word number.

In the information processing apparatus, a plurality of interface modules are connected to the synchronous data bus, and a plurality of types of data are transmitted and received between the interface module and the central processing unit via the synchronous data bus. This is to reduce the number of signal lines. In one cycle, the synchronous data bus is used to transfer data for one module, and in another cycle, the synchronous data bus is used for transmitting and receiving data for another module. Thereby, the throughput of the synchronous data bus can be improved.

In such data transfer, it is necessary for the receiving bus interface module to know the end of the received data.

In order to know the end of the received data, at the start of data transfer, "head display" is first performed (refer to ST in (1) of FIG. 5), and at the same time, a command word including data byte number information "BCT" is transferred. Then, an address word (see (2) in FIG. 5) for the head byte address is transferred.
The data words for the required number of data (see (3), (4) and (5) in FIG. 5) are sequentially transferred.
If the data always contains data bytes from the first byte insertion position of the data word, the transfer end clock cycle of the received data can be easily determined from the data byte number information. If the data byte does not enter from the first byte insertion position (see FIG. 6), the transfer end clock cycle of the received data cannot be easily determined from the head byte address and the data byte number information. Therefore, even if the data does not include a data byte from the first byte insertion position of the data word, the transfer byte which can determine the transfer end clock cycle of the received data using the above-mentioned first byte address and the data byte number information. A number determination circuit is used.

[Conventional technology]

The conventional transfer byte number determination circuit has the configuration shown in FIG. The number of bytes (word position indicating bit and byte position indicating bit) from the synchronous data bus is set in the byte number register 2, and the address (word position indicating bit and byte position indicating word in word) from the synchronous data bus is set in the address register 4. Bit) is set. Note that the byte number register 2 and the address register 4
Shows an example in which an 8-bit byte number and an 8-bit head byte address are respectively set. The word has a 4-byte structure. Each output bit from the byte number register 2 and the address register 4 stores its bit digit position and is input to the addend input and the addition input of the adder circuit 20. The addition circuit 20 has a -1 subtraction input. Similarly to the address register 4, the output value from the adder circuit 20 also indicates the word position indicating bit and the byte position indicating bit in the address. The subtraction circuit 22 subtracts the word position indication bit of the adder 20 from the word position indication bit of the address register 4.
The subtraction circuit 22 has a +1 addition input. Subtraction circuit 22
Is set in the transfer word number (transfer count) register 6 and its value is used to know the clock cycle at the end of the transfer of the received data.

[Problems to be solved by the invention]

As is clear from the above description, the signal is
Since the transfer circuit is obtained only when the signal is sequentially propagated through the circuit 20 and the subtraction circuit 22, the signal transmission delay time increases. This causes a limitation on the data transfer cycle time. Further, the number of circuits for obtaining the number of transfers also increases.

The present invention has been created in view of such problems,
It is an object of the present invention to provide a method for determining the number of transfer words that can reduce the signal propagation delay time while reducing the number of circuit elements, and a circuit therefor.

[Means for solving the problem]

The present invention, as shown in FIG. 1, is applicable to the case where the first byte address is set to a value indicating any byte insertion position in a word, and the number of bytes is set to any number in FIG. As shown in A), (B), (C) and (D), based on the knowledge that the number of transfer words can be determined to be either (BCT) + (BCT) +1 or (BCT) +2. It was done. FIG. 1 (A),
The following table summarizes the relationships shown in (B), (C) and (D). For the sake of simplicity, in the following description, one word is composed of 4 bytes.

Note that (BCT) is a value represented by upper bits excluding the lower two bits in the byte number register (hereinafter, referred to as a word number display value).

A first invention is a data transfer system for transferring a required number of words for data after transferring a word having a leading byte address of data to be transferred, following a word having a number of bytes to be transferred, First, a word number display value included in the received byte number, the word number display value + 1 and the word number display value + 2 are output. The word number display value, the word number display value + 1 and the word number display value + in response to the received byte number and the transfer word number output control determination value included in the first byte address.
A signal for selecting one of the two is output. Then, one of the three values is selected from the output signal, and the selected value is used as the number of words received via the data transfer system. According to a second aspect of the present invention, as shown in FIG. 2 (part 1), a byte number register 2 for setting the number of bytes of a command word received prior to data word reception, and a command word received following the command word. Number of transfer words provided in a data transfer system having an address register 4 for setting the address of an address word and a transfer word number register 6 for setting the number of transfer data words obtained from the values set in the registers 2 and 4 The determination circuit responds to the number of bytes set in the byte number register 2 and the address register 4 and the transfer word number output control determination value included in the first byte address, and displays the word number display value of the byte number register 2 in response to the determination value. A first transfer word output control signal for output control and a second transfer word output control signal for output control of the word number display value +2. A determination circuit 8 outputs a transfer word output control signals, a first adder circuit 10 for adding 1 to the number of words displayed value of the byte number register 2, the byte number register 2
A second adding circuit 12 for adding 2 to the word number display value of
In response to the first transfer word output control signal and the second transfer word output control signal, one of the word number display value, the word number display value + 1, or the word number display value + 2 is transferred. A selection circuit 14 for outputting the number of words to the transfer word number register 6;
According to a third aspect of the present invention, as shown in FIG. 2 (part 2), a byte number register 2 for setting the number of bytes of a command word received prior to data word reception, and a command word received following the command word. An address register 4 for setting the address of the address word;
In a transfer word number determination circuit provided in a data transfer system having a transfer word number register 6 for setting the number of transfer data words obtained from the value set to 4, the transfer word number is set in the byte number register 2 and the address register 4. A first transfer word output control signal for controlling output of a word number display value of the byte number register 2 in response to a byte number and a transfer word number output control value included in the first byte address, and the word number A determining circuit 8 for outputting a second transfer word output control signal for controlling the output of the display value +2, one adding circuit 16 receiving the word number display value at the input to be added, and an output from the determining circuit 8 And a selection circuit 18 for outputting 0, 1, or 2 to the addition input of the addition circuit 16 in accordance with both transfer word output control signals.

(Operation)

The number of bytes received via the data transfer system is set in the byte number register 2, and the first byte address is set in the address register 4. These two registers 2, 4
The first transfer word output control signal for controlling the output of the word number display value of the byte number register 2 and the output control of the word number display value + 2 are used by the transfer word number output control determination value of Is output from the determination circuit 8 for the second transfer word output control signal. This judgment circuit 8
Indicates one of the means for outputting a signal for selecting one of the word number display value, the word number display value + 1 and the word number display value + 2 in the present invention.

In the second invention, both of these transfer word output control signals are one of the word number display value of the byte number register 2, the word number display value of the adder circuit +1 or the word number display value of the adder circuit +2. Selector 14 to output one
Used in In the third aspect, the addition circuit 16
Selection circuit 16 to supply 0, 1, or 2 to the
Used in

In this way, the selected value is set in the transfer word number register 6 as the transfer word number, and is used to know the clock cycle at the end of the transfer.

〔Example〕

FIG. 3 shows an embodiment of the first invention. In this figure, the byte number register 2 and the address register 4 are the same as those described in FIG. The determination circuit 8 receives the byte number display bit output of the address register 4 and the byte number display bit output of the byte number register 2, and outputs a transfer word number output control signal (hereinafter referred to as a transfer number gate signal) 0W.
And 2W. The transfer number gate signal 0W is output from the NAND circuit 30 receiving the byte number display byte output of the address register 4 and the byte number display bit output of the byte number register 2. The transfer number gate signal 2W is output from the AND circuit 32. The AND circuit 32 outputs the output of the OR circuit 34 of the byte number display bit output a of the address register 4 and the byte number display bit output c of the byte number register 2, the byte number display bit output b of the address register 4 and the byte number display bit It receives the byte number indicating bit output d. Here, the lower two bits of each register 2 and 4 are used, and in each register 2 and 4, a and c are the lower bits and b and
d is the upper bit. Adder circuit 10 and adder circuit 12
Receives the word number indicating bit output of the byte number register 2 at its input A, and the addition input B of the adding circuit 10.
, A value of 2 is input to the addition input B of the addition circuit 12. AND gate 36, AND gate 3
8. The AND gate 40 is an AND gate, and its gated input receives the word number display bit output of the byte number register 2, the output of the adder circuit 10, and the output of the adder circuit 12, respectively. The transfer count gate signal 0W is supplied to the gate control input of the AND gate 36.
The transfer control gate signal 0W and the transfer control gate signal 2W are supplied to a gate control input (inverted AND input) of 38, and the transfer control gate signal 2W is supplied to the gate control input of the AND gate 40. The outputs of the AND gate 36, AND gate 38 and AND gate 40 are input to the transfer word number (transfer count) register 6 via the OR circuit 42. AND gate 36, AND gate 38 and AND gate
40 and the OR circuit 42 correspond to the selection circuit 14 in FIG.

 The operation of the circuit of the present invention will be described below.

Regardless of the start byte address is set to a value indicating any byte insertion position in a word, and the number of bytes BCT is set to any number, as is clear from the above description of the principle of the present invention, Either the word number display bit of the number register 2, a value obtained by adding 1 thereto, or a value obtained by adding 2 to the word number display bit of the byte number register 2 represents the number of transfers in the data transfer. The value obtained by adding 1 to the word number indicating bit of the byte number register 2 or the value obtained by adding 2 to the word number indicating bit of the byte number register 2 is output from the adding circuit 10 or 12. Is done. The number-of-transfers gate signals 0W and 2W for gating whether the value is any of the above values are respectively set to the number of bytes in the command word in the byte number register 2, and the first byte address in the subsequently received address word is set. Is output from the NAND circuit 30 and the AND circuit 32 of the determination circuit 8 each time is set (ie, at the start of data transfer).

Therefore, when the data transfer is started, the three transfer count candidate values to be selected are the AND gate 36 and the AND gate 36.
38, while being supplied to each gated input of the AND gate 40, the transfer number gate signals 0W and 2W are output from the determination circuit 8. The transfer number candidate values from the byte number register 2, the adder circuit 10, or the adder circuit 12 determined according to the transfer number gate signals 0W and 2W are AND gates 36 and AND gates.
38, or output via an AND gate 40, and an OR circuit 42
And is set in the transfer word number (transfer count) register 6 via the control register and is used to determine a clock cycle for ending data transfer (end of received information).

Since the number of circuits through which a signal must propagate to the set number of transfers is small, the signal propagation delay time required to set the number of transfers is short. Also, their circuit scale is small.

FIG. 4 shows another embodiment of the present invention. In this embodiment, the number of adders is one, and the number of words indicating the number of words of the byte number register 2 in the embodiment of FIG.
And outputs a value obtained by adding 2 to the number-of-words indicating bit. For this purpose, the AND gate 44, the AND gate 46 and the AND gate 48, and the OR circuit 50 are provided, and the output of the OR circuit 50 is supplied to the addition input of the adder 16. The word number indicating bit of the byte number register 2 is supplied to the adder input of the adder 16. The gated inputs of the AND gate 44, AND gate 46 and AND gate 48 include:
0 (0,0 in binary notation), 1 (0,1 in binary notation),
2 (1,0 in binary notation) is input. The transfer count gate signal 0W is applied to the gate control input of the AND gate 44, and the transfer count gate signal 0W is applied to the inverted gate control input of the AND gate 46.
And 2W, and a gate control input of the AND gate 48 is supplied with a transfer count gate signal 2W. AND gate 44,
AND gate 46 and AND gate 48, and OR circuit 50
Correspond to the selection circuit 18 of FIG. 2 (part 2). The other components that are the same as those in FIG. 3 are given the same reference numerals as those of the components in FIG. 3, and descriptions thereof are omitted. .

The operation of this embodiment is the same as that of the embodiment shown in FIG. 3, but the circuit amount can be reduced as compared with the embodiment shown in FIG.

The circuit configuration for selecting the word number display bit of the byte number register 2 in the above embodiment, a value obtained by adding 1 thereto, or a value obtained by adding 2 to the word number display bit of the byte number register 2 is selected by a selector. The present invention may be carried out under an alternative configuration. Also, generation of transfer count gate information under a high-speed CPU, addition of 1 to the word number display bit of the byte number register 2, or addition of 2 to the word number display bit of the byte number register 2 The output of the value and the selection of the three values based on the transfer number gate information may be performed by software, and the result may be set in the transfer word number (transfer number) register 6.

In the above description, an example is shown in which the leading byte address is transferred following the command as shown in FIG. 5, but the present invention is similarly realized even when these are transferred simultaneously. Also, although 4 bytes are described as 1 word,
The same can be realized whether one word is 8 bytes or 16 bytes.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, since the number of circuits in which a signal must propagate to a set number of transfer times is small, the signal propagation required to set the number of transfer times is reduced. The delay time is short,
Also, their circuit scale is small.

[Brief description of the drawings]

 FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is a block diagram of the principle of the present invention, FIG. 3 is a diagram showing one embodiment of the first invention, and FIG. 4 is an embodiment of the second invention. FIG. 5 is a diagram showing a format of each word to be transferred, FIG. 6 is a diagram showing an example of data transfer by misalignment, and FIG. 7 is a diagram showing a conventional transfer word number determining circuit. 2, 3 and 4, 2 is a byte number register, 4 is an address register, 6 is a transfer word number register, 8 is a decision circuit, 10, 12, and 16 are addition circuits, and 14, 18 are It is a selection circuit.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Makoto Okazaki 1015 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Katsuyuki Okada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation In-company (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 13/12

Claims (3)

(57) [Claims] Claims 1. A required number of words for data following a command word having the number of bytes to be transferred, or simultaneously with the command word, after transferring an address word having a leading byte address of the data to be transferred. In the data transfer system for transferring the number of words, the display value of the number of words included in the received number of bytes, the display value of the number of words +1 and the display value of the number of words +2 are output, and the received byte number and the head byte address are included. And outputting a signal for selecting one of the word number display value, the word number display value + 1 and the word number display value + 2 according to the transfer word number output control determination value. A transfer word, wherein one of the three values is selected by a signal, and the selected value is the number of words received via the data transfer system. How to determine the number of cards. 2. A byte number register (2) for setting the number of bytes in a command word received prior to receiving a data word, and a byte number register (2) for receiving an address word received following the command word or simultaneously with the command word. The data transfer system includes an address register (4) for setting an address and a transfer word number register (6) for setting the number of transfer data words obtained from the values set in the registers (2, 4). In the transfer word number determining circuit, the number of bytes set in the byte number register (2) and the address register (4) and the number of transfer words output control determination value included in the head byte address are determined. A first transfer word number output control signal for controlling the output of the word number display value of (2) and the word; A determination circuit (8) for outputting a second transfer word number output control signal for output control of the number display value +2, and a first addition for adding 1 to the word number display value of the byte number register (2) A second adding circuit (12) for adding 2 to the word number display value of the byte number register (2); a first transfer word output control signal and a second transfer word output control A selection circuit for outputting to the transfer word number register (6) one of the word number display value, the word number display value + 1, or the word number display value + 2 as a transfer word number in response to a signal ( 14) A transfer word number determining circuit, characterized in that: 3. A byte number register (2) for setting the number of bytes of a command word received prior to receiving a data word, and an address of an address word received following the command word or simultaneously with the command word. And a transfer word number register (6) for setting the number of transfer data words obtained from the values set in the two registers (2, 4).
A transfer word number determination circuit provided in a data transfer system having: a number of bytes set in the byte number register (2) and an address register (4); and a transfer word number output control determination included in a head byte address. A first transfer word output control signal for controlling the output of the word number display value of the byte number register (2) in response to the value, and a second transfer word output for controlling the output of the word number display value + 2 A judgment circuit (8) for outputting a control signal; and one addition circuit (1) for receiving the word number display value at the augmented input and outputting the addition result to the transfer word register (6)
6), and 0, 1, or 2 in response to both transfer word output control signals output from the determination circuit (8).
And a selection circuit (18) for outputting to the addition input of (1).