JPH0353322A - Information processor - Google Patents

Abstract

PURPOSE:To execute an instruction at high speed by providing the 1st and 2nd microinstruction registers and an address register which holds the address of a jump goal when the instruction of the 2nd microinstruction register is equal to a jump instruction and this instruction is satisfied. CONSTITUTION:When the instruction held by a 2nd microinstruction register 2 is equal to a jump instruction, this instruction is decoded by a jump instruction decoder 4. Then a 1st address arithmetic circuit 8 computes a jump address when the jump conditions of the jump instruction are satisfied. The computed jump address is sent to a 1st address register 6 and held there at the rise of a clock. At the same time, the address value following an instruction under execution is held by a 2nd address register 7. Then a jump instruction is held by a 1st microinstruction register 1 and executed. Thus the data on the register 6 and the contents of the register 7 are sent to a 1st address line 10 when the jump conditions are satisfied and not satisfied respectively. The instruction to be carried out next is sent out of a microinstruction storage part 5. As a result, the executing cycles of instructions are accelerated.

Description

[Detailed description of the invention] [Industrial application field] The present invention is. It relates to an information processing device.

[Conventional technology] Conventionally, in this type of information processing device, when executing a jump instruction, the processor calculates the jump address when the jump condition is satisfied during a long instruction line, and outputs the result to the address bus. , the next instruction was retrieved from the memory.

[Problems to be Solved by the Invention] In the conventional information processing device described above, when executing a jump instruction, the execution of the jump condition and the calculation of the jump address are performed in the same instruction cycle. The disadvantage is that it is slow.

[Means for Solving the Problems] An information processing device according to the present invention has a first instruction register that holds an instruction to be executed, and a register that stores an instruction to be executed at the next address of the storage unit where the instruction to be executed is stored. When the instruction held in the second instruction register is a jump instruction. It has an address register that stores the jump destination address when the jump condition is met.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. The information processing device of this embodiment includes a lth microinstruction register 1, a second microinstruction register 2. an instruction decoder 3, a jump instruction decoder 4, a microinstruction storage section 5, and a first instruction decoder for storing a jump address.
Address register 6. a second address register 7 for storing the next address; a first address calculation circuit 8 for subtracting the jump address; a second address calculation circuit 9 for calculating the next address; It has two address lines 10 and 11.

This information processing device is. As shown in Figure 2. When one program instruction is executed at the rising edge of the clock, an address for fetching the next instruction is output from the first address line 10 in accordance with the instruction. According to the output address. The next program instruction is read from the microinstruction storage unit 5, execution starts at the next rising edge of the clock, and the process is repeated. These are the same as before.

Here, the microinstruction storage unit 5 is configured with, for example, a dual boat memory, and the first address line 10
The address value to be executed is output. at the same time. The next address value of the first address line 10 is output to the second address line 11 .

The output data of each address is output to the first and second microinstruction registers 1 and 2, respectively, and is held at the rising edge of the clock. The instruction held in the first microinstruction register 1 is decoded by the instruction decoder 3 and executed. The instruction held in the second microinstruction register 2 is . Unless the instruction held in the first microinstruction register 1 is a jump instruction, this is the instruction to be executed next.

Here, if the instruction held in the second microinstruction register 2 is a jump instruction, it is decoded by the jump instruction decoder 4. The first address calculation circuit 8 calculates a jump address when the jump condition of the jump instruction is satisfied, and sends it to the first address register 6. It is held at the rising edge of the clock.

or. The second address register 7 holds the next address value of the instruction being executed.

and. Next, the jump instruction is held in the first microinstruction register 1 and executed, and when the jump condition is satisfied, the data in the first address register 6 is changed to the first address register 7 in clause 2. 1 address line 10, and the next instruction to be executed is sent from the microinstruction storage unit 5.

[Effects of the Invention] As explained above, the present invention has a first microinstruction register that holds instructions to be executed, and an instruction stored at the next address of the storage section where the instruction to be executed was stored. By having a second microinstruction register that holds the second microinstruction register, and an address register that holds the jump destination address when the jump instruction is established when the instruction in the second microinstruction register is a jump instruction, high-speed processing can be achieved. It has the effect of being able to execute instructions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the apparatus shown in FIG. 1... First microinstruction register, 2... Second microinstruction register, 3... Instruction decoder, 4...
・Jump instruction decoder, 5... Microinstruction storage unit, 6... First address register, 7... Second address register, 8... First address calculation circuit, 9
. . . second address calculation circuit, 10 . . . first address line. 11...Second address line. Figure 1 Clock Figure 2

Claims (1)

[Claims] 1. It has a processor and a storage unit that stores a program consisting of a plurality of instructions that instruct the operation of the processor,
The processor reads an instruction from the storage unit as a current instruction, operates according to the instructions of the current instruction, and at the same time outputs an address where a next instruction, which is an instruction following the current instruction, is stored, and reads the instruction from the storage unit. In an information processing device that reads the next instruction, a first instruction register holds the current instruction, and a first instruction register holds the instruction stored at the next address of the storage unit where the current instruction was stored. Information processing comprising: a second instruction register; and, when the instruction held in the second instruction register is a jump instruction, an address register that stores a jump destination address when the jump instruction is established. Device.