JPH0358128A - Information processor - Google Patents

Abstract

PURPOSE:To quicken the execution cycle of an instruction by providing a jump instruction judging decoder for judging an unconditional jump instruction or a conditional jump instruction, and an address register for storing an address of a jump destination when the conditional jump instruction is formed, in the case it is decided to be the conditional jump instruction. CONSTITUTION:When an instruction stored in a micro-instruction register 2 is a conditional jump instruction, it is decoded by a jump instruction judging decoder 4. Subsequently, a jump address when a jump condition of a jump instruction is formed by an address arithmetic circuit 8 is calculated, sent out to an address register 6, and stored at a rise of a clock. Also, in an address register 7, the next address value of the instruction which is being executed is stored. Next, the jump instruction is stored in the next micro-instruction register 1 and executed, and when the jump condition is formed, the contents of the address register 6 are sent out to an address line 10 through an address circuit 12. In such a way, the execution cycle of an instruction is quickened.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an information processing device.

[Conventional technology]

Conventionally, when executing a jump instruction, this type of information processing device calculates a jump address when a jump condition is met during execution of the instruction, outputs the result to the address bus, and retrieves the next instruction from the storage unit. Ta. Furthermore, an unconditional jump command has also been executed as a single command.

[Problem to be solved by the invention]

In the conventional information processing device described above, when executing a jump instruction, the determination of whether the jump condition has been established and the calculation of the jump address are performed in the same instruction cycle, which slows down the instruction execution cycle. There are drawbacks.

[Means to solve the problem]

The information processing device of the present invention has a storage unit that stores a program, and reads a first program from the storage unit and operates according to instructions of the read first program, and at the same time, a second program that is the next program is operated. In an information processing device that outputs an address where a second program is stored and reads the second program from the storage unit, the information processing device includes a first microinstruction register that stores instructions to be executed, and a first microinstruction register that stores instructions to be executed. a second micro-instruction register for storing an instruction stored at the next address of the storage unit that has been previously stored; and an instruction in the second micro-instruction register is an unconditional jump instruction or a conditional jump instruction. a jump instruction determination decoder for determining whether the jump instruction is an unconditional jump instruction; an address circuit for outputting a jump destination address to the storage unit when the jump instruction determination decoder determines that the jump instruction is an unconditional jump instruction; and an address register that stores a jump destination address when the conditional jump instruction is established.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 and 2 are microinstruction registers (first microinstruction register and second microinstruction register), 3 is an instruction decoder, 4 is a jump instruction judgment decoder, and 5 is a microinstruction storage unit (storage unit). , 6 is an address register for storing the jump destination address, 7 is an address register for storing the next address, 8 is an address calculation circuit for calculating the jump address, 9 is an address calculation circuit for calculating the next address, 10 and 11 are address lines, and 2 is an address circuit.

Next, the operation will be explained.

As shown in FIG. 2, when the information processing device shown in FIG. 1 executes one program instruction at the rising edge of the clock, it outputs an address for fetching the next instruction to the address line 10 according to that instruction. ．． The next program instruction is read from the microinstruction storage unit 5 according to the output address, and execution is started at the next rising edge of the clock.
Repeat this. The above operation is also performed in the prior art.

The microinstruction storage unit 5 is configured with, for example, a dual port memory, and the address value of the instruction to be executed is outputted to the address line 10. At the same time, the next address value of the address line 10 is output to the address line 11. Further, the output data of each address is output to the microinstruction registers 1 and 2, respectively, and stored at the rising edge of the clock. The instructions stored in the microinstruction register 1 are decoded by the instruction register 3 and executed. Furthermore, the instruction stored in the microinstruction register 2 is a jump instruction, or the instruction stored in the microinstruction register 2 is a jump instruction.
This is the next instruction to be executed, unless the instruction stored in is an unconditional jump instruction.

Here, if the instruction stored in the microinstruction register 2 is a conditional jump instruction, it is decoded by the jump instruction judgment decoder, and the jump address is calculated by the address calculation circuit 8 when the jump condition of the jump instruction is satisfied. , is sent to the address register 6 and stored at the rising edge of the clock. Also, address register 7
The next address value of the instruction being executed is stored in . Then, the jump instruction is stored in the next microinstruction register 1 and executed, and if the jump condition is satisfied, the contents of the address register 6 are sent to the address line 10 through the address circuit 12, and if the jump condition is not satisfied, the contents of the address register 7 are sent to the address line 10. The contents are transferred to address line 10 through address circuit 12.
The next instruction to be executed is sent from the microinstruction storage unit 5.

Next, if the instruction stored in the microinstruction register 2 is an unconditional jump instruction, it is decoded by a jump instruction judgment decoder, and a jump address is calculated by an address calculation circuit 8 and sent to an address line 10 through an address circuit 12. Ru. Then, at the same time that the next instruction to be executed is sent out from the microinstruction storage section 5, the instruction stored in the microinstruction register 1 is executed.

〔Effect of the invention〕

As explained above, the present invention has a first microinstruction register that stores an instruction to be executed, and a second microinstruction register that stores an instruction stored at the next address of the storage section where the instruction to be executed is stored. microinstruction register 2, a jump instruction judgment decoder that judges the instruction in microinstruction register 2 as an unconditional jump or a conditional jump instruction, and if the jump instruction judgment decoder judges that the instruction is an unconditional jump, the jump destination address is stored in the memory section. It is said that the instruction execution cycle can be made faster by having an address circuit that outputs an output to a conditional jump instruction, and an address register that stores the jump destination address when the conditional jump instruction is satisfied if it is determined to be a conditional jump instruction. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a time chart of the operation of the information processing device shown in the figure. DESCRIPTION OF SYMBOLS 1... Micro instruction register, 2... Micro instruction register, 3... Instruction decoder, 4... Jump instruction judgment decoder, 5... Micro instruction storage section, 6...
・Address register, 7...Address register, 8・
...Address calculation circuit, 9...Address calculation circuit, 1
0...address line, 11...address line, 12...
・Address circuit.

Claims (1)

[Claims] It has a storage unit that stores a program, reads a first program from the storage unit, and operates according to instructions of the read first program, and at the same time, a second program that is the next program is stored. In an information processing device that outputs an address and reads out the second program from the storage unit, a first microinstruction register stores an instruction to be executed, and a microinstruction register next to the storage unit in which the instruction to be executed is stored. a second micro-instruction register that stores an instruction stored at an address of , and a jump instruction determination decoder that determines whether the instruction in the second micro-instruction register is an unconditional jump instruction or a conditional jump instruction. and an address circuit that outputs a jump destination address to the storage unit when the jump instruction determination decoder determines that the jump instruction is an unconditional jump instruction, and when the conditional jump instruction is established when the jump instruction is determined to be a conditional jump instruction. An information processing device comprising: an address register that stores a jump destination address.