JP2005134987A - Pipeline arithmetic processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pipeline arithmetic processor allowing forwarding even if not arranging an NOP instruction inside a program when processing the program including a prescribed instruction requiring a plurality of cycles at execution. <P>SOLUTION: A control part 11 decides whether an instruction read from an instruction memory 1 is a load instruction requiring two cycles at the execution or not. As a result, when deciding that it is the load instruction, the control part 11 stops the operation of a program counter 10 in the first cycle to stop the execution of the processing of the succeeding instruction, and operates the program counter 10 in the second cycle to allow the execution of the processing of the succeeding instruction, in a period of the two cycles of the load instruction. When not deciding that it is the load instruction, the controller 11 performs no process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a pipeline arithmetic processing apparatus that divides an instruction into fine processing units, processes them by overlapping them, and increases the processing speed of the instructions.

As this kind of pipeline arithmetic processing device, a device that operates correctly even when a program developed for instruction pipeline processing of a predetermined number of stages is executed by instruction pipeline processing having a larger number of stages is known. (See Patent Document 1).
By the way, as shown in FIG. 3, for example, when the first instruction is a branch instruction, the following processing is performed as the pipeline processing performed by the conventional pipeline arithmetic processing unit.

That is, in this case, the read address of the subsequent instruction is not determined until the branch instruction is decoded and determined at the instruction decoding stage RD. For this reason, a NOP (No Operation) instruction has been placed as the second instruction.
In FIG. 3, “IF” represents an instruction fetch stage for fetching an instruction, “RD” represents an instruction decode stage for decoding (decodes) an instruction, and “EXE” represents an instruction execution stage for executing an instruction. These meanings are the same in the present specification.

Further, as pipeline processing performed by a conventional pipeline arithmetic processing unit, as shown in FIG. 4, for example, when both branch instructions are consecutive, such as the first instruction and the second instruction are both branch instructions, Is inconvenient.
In other words, when branch instructions are continuous, after the transition to the first branch destination address, it must be the address that originally incremented the branch destination address in the next cycle, but it is written to the second branch destination address. As a result, the program executed at the first branch destination fails without being executed.

For this reason, the failure of the program is prevented by placing the respective NOP instructions after both branch instructions, that is, the first instruction and the second instruction.
Further, in the conventional pipeline arithmetic processing apparatus, since the value is read from the register to the execution unit at the stage “RD”, there is an inconvenience that the operation result of the immediately preceding instruction cannot be used by the immediately following instruction, and this inconvenience is solved. Therefore, a forwarding mechanism (chaining mechanism) is provided.

This forwarding mechanism is a mechanism in which write data is directly transferred to an arithmetic processing unit when data writing and reading occur simultaneously for one register. This has the effect of reducing the apparent delay slot of each instruction by one.
FIG. 5 shows an example in which the operation result of the first instruction in which the instruction execution stages EXE1 and EXE2 are two cycles can be used for the third instruction by forwarding.

Next, in FIG. 6, the case where the add instruction ADD and the branch instruction BEQ, which are composed of the following programs, are pipeline processed will be considered.
ADD% SR0% SR1% SR2 (Register SR0 = Register SR1 + Register SR2)
BEQ% SR0% SR3 Label1 (If register SR0 = register SR3, branch to Label1)
In this case, if there is a forwarding mechanism, the pipeline processing of the add instruction ADD and the branch instruction BEQ is as shown in FIG. 6 and need not be interlocked.
Japanese Patent Laid-Open No. 2000-29696

Conventionally, in pipeline processing, when a plurality of branch instructions are continuous as described above, a NOP instruction is placed immediately after each branch instruction.
In this case, since the NOP instruction is added immediately after each branch instruction, the amount of program code increases.
On the other hand, as described above, when performing an add instruction and a branch instruction, it is theoretically possible to directly use the data obtained in the execution stage of the instruction immediately before the branch instruction as the branch condition of the branch instruction using the forwarding mechanism. Is possible.

However, the time obtained by adding the instruction execution time in the add instruction and the address generation time of the branch instruction increases the delay of the arithmetic circuit and decreases the operating frequency.
Therefore, the following pipeline processing that can cope with branch processing without changing the program even when forwarding is applied and can suppress a decrease in operating frequency due to a delay in forwarding can be considered.

An example of this pipeline processing will be described with reference to FIG.
FIG. 7 shows a case where an add instruction ADD and a branch instruction BEQ consisting of the following programs are executed, and the register SR0 used for the branch condition of the branch instruction is updated by the immediately preceding add instruction. It is.
Sample code A
ADD% SR0% SR1% SR2 (Register SR0 = Register SR1 + Register SR2)
BEQ% SR0% S R3 Label1 (If register SR0 = register SR3, branch to Label1)
In this case, in the first clock cycle “1”, the first instruction (addition instruction) is fetched from the instruction memory to the instruction register (IF stage).

In the next clock cycle “2”, the first instruction (add instruction) fetched in the instruction register is decoded (RD stage), and at the same time, the second instruction (branch instruction) is fetched from the instruction memory to the instruction register. (IF stage).
In the next clock cycle “3”, the decoded first instruction (addition instruction) is executed, and the processing result is written to the register.

  Also, in clock cycle “3”, the register that decodes the second instruction (branch instruction) and writes the addition result of the first instruction (addition instruction) is the same as the register that reads by the second instruction (branch instruction). Determine whether. If the result of this determination is that both registers are the same, they are replaced with NOP instructions using hardware, and branch instructions are not read from the registers. Further, in clock cycle “3”, the third instruction is fetched from the instruction memory into the instruction register.

In the next clock cycle “4”, the second instruction is processed as follows. That is, the register in which the addition result executed by the first instruction (addition instruction) is written is read to generate a branch destination address.
In the clock cycle “4”, the third instruction is processed as follows. That is, the operation (increment) of the program counter is stopped, and the third instruction is again taken from the instruction memory into the instruction register.

The processing described above performs the same operation as when a NOP instruction (an instruction that does not change the internal state) is inserted between the addition instruction ADD and the branch instruction BEQ as in the following program.
ADD% SR0% SR1% SR2 (Register SR0 = Register SR1 + Register SR2)
NOP
BEQ% SR0% SR3 Label1 (If register SR0 = register SR3, branch to Label1)
As described above, in the processing shown in FIG. 7, when the register for writing the addition result of the first instruction (addition instruction) and the register for reading by the second instruction (branch instruction) are the same, a hardware NOP is used. By replacing with an instruction, the NOP instruction can be omitted from the program.

However, when forwarding is performed with an instruction consisting of two cycles at the time of execution processing, such as a load instruction, there is a restriction that a NOP instruction must be arranged after the load instruction in the program.
Accordingly, an object of the present invention is to process a pipeline operation process capable of forwarding even if a NOP instruction is not arranged in the program when a program including a predetermined instruction that requires a plurality of cycles during execution processing is processed. To provide an apparatus.

In order to solve the above-mentioned problems and achieve the object of the present invention, each invention is configured as follows.
In other words, according to a first aspect of the present invention, there is provided a pipeline arithmetic processing unit in which an instruction is pipeline processed. A determination unit that determines whether the instruction is a predetermined instruction that requires a plurality of cycles during execution processing, and the determination unit However, when it is determined that the instruction is a predetermined instruction, the execution of the subsequent instruction is stopped during a plurality of cycles in which the execution process of the predetermined instruction is performed, and the processing of the subsequent instruction is performed after the stop is released. Control means to be executed.

  In a second aspect based on the first aspect, the determination means determines whether or not the instruction is a load instruction that requires two cycles during execution processing, and the control means includes: When the determination means determines that the instruction is a load instruction, during the two-cycle period in which the execution process of the load instruction is performed, the operation of the program counter is temporarily stopped in the first cycle and the execution of the subsequent instruction is stopped. In the second cycle, the program counter is operated to process the subsequent instruction.

  According to the present invention having such a configuration, when a program including a predetermined instruction that requires a plurality of cycles during execution processing is processed, forwarding is possible even if a NOP instruction is not arranged in the program. A pipeline arithmetic processing device can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an embodiment of a pipeline arithmetic processing apparatus according to the present invention.
As shown in FIG. 1, the pipeline arithmetic processing apparatus according to this embodiment includes an instruction memory 1, an instruction register 2, a branch destination address calculation unit 3, an instruction decoding unit 4, an execution unit 5, and a register file. 6, an adder 8, a multiplexer 9, a program counter 10, and a control unit 11.

The instruction memory 1 is a memory for storing various instructions (programs), and predetermined instructions are stored at predetermined addresses. The instruction memory 1 reads an instruction at an address (address) designated by the program counter 10 and outputs the read instruction to the instruction register 2.
The instruction register 2 is a register that temporarily stores an instruction output from the instruction memory 1. The instruction stored in the instruction register 2 is supplied to the instruction decoding unit 4.

The branch destination address calculation unit 3 obtains the branch destination address when it is necessary to calculate the branch destination address of the instruction based on the instruction from the instruction decoding unit 4. The address obtained by the branch destination address calculation unit 3 is supplied to the input side of the multiplexer 9.
The instruction decoding unit 4 decodes (interprets) an instruction from the instruction register 2. The instruction interpreted by the instruction decoding unit 4 is supplied to the execution unit 5.

The execution unit 5 executes the instruction decoded by the instruction decoding unit 4. The data processed by the execution unit 5 is stored in a predetermined register of the register file 6.
The register file 6 is composed of a plurality of registers, and each register stores data processed by the execution unit 5. The contents of each register can be supplied to the instruction decode unit 4 and the execution unit 5, respectively.

  The adder 8 performs addition for reading out the next instruction based on an instruction from the program counter 10 and outputs the addition result. The addition for reading the next instruction depends on the instruction length and is +4 for a 32-bit fixed-length instruction and +2 for a 16-bit fixed-length instruction. The addition output of the adder 8 is supplied to the input side of the multiplexer 9.

The multiplexer 9 selects the output of the branch destination address calculation unit 3 or the adder 8 based on an instruction from the control unit 11. The output of the multiplexer 9 is supplied to the program counter 10.
The program counter 10 is a counter for obtaining an address for reading an instruction in the instruction memory 1 based on an output from the multiplexer 9. The address obtained by the program counter 10 is supplied to the instruction memory 1. The program counter 10 is configured such that its operation (increment) is temporarily stopped (locked) based on control from the control unit 11 as described later.

The control unit 11 determines whether or not the instruction supplied from the instruction register 2 is a predetermined instruction (in this example, a load instruction) that requires a plurality of cycles (for example, two cycles) during the execution process. ing.
If the control unit 11 determines that the instruction is a load instruction, the control unit 11 temporarily stops the operation of the program counter 10 in the first cycle in the period of two cycles in which the execution process of the load instruction is performed. Then, the execution of the subsequent instruction is stopped, and the program counter 10 is operated in the second cycle to execute the subsequent instruction.

In addition, the specific example of the above control of the control part 11 is demonstrated with reference to drawings so that it may mention later.
Next, pipeline processing according to the embodiment having such a configuration will be described with reference to FIG.
In this example, a case will be described in which the first instruction is a load instruction (LW) that requires two cycles during execution processing, and the second instruction is an addition instruction (ADD).

That is, in this example, a case where the program is composed of the following sample code will be described.
LW% SR0 [% SR1]% SR2 (Read from the address of (register SR1 + register SR2))
ADD% SR3% SR0% SR3 (Register SR3 = Register SR0 + Register SR3)
In this case, as shown in FIG. 2, the first instruction is fetched from the instruction memory 1 into the instruction register 2 in the first clock cycle “1” (IF stage). At this time, the control unit 11 receives the first instruction fetched into the instruction register 2, and determines whether or not the received first instruction is a load instruction that requires two cycles during execution processing.

Here, since the first instruction is a load instruction as described above, the control unit 11 determines that the first instruction is a load instruction.
In the next clock cycle “2”, the first instruction fetched into the instruction register 2 is decoded by the instruction decoding unit 4 (RD stage). At this time, the next second instruction is fetched from the instruction memory 1 into the instruction register 2 (IF stage). At this time, the control unit 11 determines whether or not the second instruction fetched into the instruction register 2 is a load instruction, but here determines that it is not a load instruction.

In the next clock cycle “3”, the first instruction decoded by the instruction decode unit 4 is executed by the execution unit 5, and as a result of this execution, a read address of a data memory (not shown) is generated (EXE1 stage) ).
Here, as described above, the control unit 11 determines that the first instruction is a load instruction that requires two cycles during execution processing. Therefore, in the clock cycle “3”, the control unit 11 temporarily stops the operation of the program counter 10. As a result, the second instruction fetched into the instruction register 2 is not decoded by the instruction decoding unit 4, and the third instruction is not fetched from the instruction memory 1 into the instruction register 2.

In the next clock cycle “4”, the following processing is performed for the first instruction. That is, data is read from the address of the data memory generated as described above, and the read data is written to the register of the register file 6 (EXE2 stage).
In the clock cycle “4”, the following processing is performed for the second instruction. That is, the second instruction fetched in the instruction register 2 is decoded by the instruction decoding unit 4 (RD stage).

At this time, based on an instruction from the control unit 11, the execution unit 5 forwards the data read from the data memory by the first instruction as described above. That is, the execution unit 5 enables the data read from the data memory by the first instruction to be used as input data in the next clock cycle “5” operation.
Further, in the clock cycle “4”, the third instruction is fetched from the instruction memory 1 into the instruction register 2 (IF stage).

  In the next clock cycle “5”, the following processing is performed for the second instruction. That is, the execution unit 5 performs an addition process using the data forwarded as described above (EXE stage). In the clock cycle “5”, the third instruction fetched into the instruction register 2 is decoded by the instruction decoding unit 4 (RD stage), and the fourth instruction is fetched from the instruction memory 1 into the instruction register 2 (IF stage). ).

In the next clock cycle “6”, the content of the third instruction decoded by the instruction decoding unit 4 is executed by the execution unit 5 (EXE stage), and the fourth instruction fetched in the instruction register 2 is changed to the instruction decoding unit. 4 (RD stage).
As described above, in this embodiment, it is determined whether or not an instruction is a load instruction that requires two cycles during execution processing. When it is determined that the instruction is a load instruction, execution processing of the load instruction is performed. In the period of two cycles in which the program is performed, the operation of the program counter is stopped in the first cycle to stop the processing of the subsequent instruction, and the program counter is operated in the second cycle to execute the processing of the subsequent instruction. I did it.

Therefore, according to this embodiment, when the program includes an instruction that requires two cycles for execution processing, such as a load instruction, it is not necessary to place a NOP instruction after the load instruction of the program. The amount can be reduced.
In the above embodiment, a load instruction has been described as an example of an instruction that requires two cycles for execution processing.

However, examples of instructions that require two cycles or two or more cycles (plural cycles) during execution processing include product-sum operation instructions and vector instructions in addition to the load instructions described above.
As described above, when a specific instruction that requires a plurality of cycles during execution processing is included in the program, when the instruction is fetched from the instruction memory 1 to the instruction register 2, the control unit 11 specifies the instruction. It is determined whether or not it is an instruction. If it is determined that the instruction is a specific instruction, the same processing as that when it is determined that the instruction is a load instruction is performed during a plurality of cycles during which the execution process of the specific instruction is performed.

It is a block diagram which shows the structure of embodiment of this invention. In this embodiment, it is explanatory drawing explaining the pipeline process in the case of including the instruction which requires 2 cycles at the time of an execution process. It is explanatory drawing for demonstrating an example of the conventional pipeline process. It is explanatory drawing for demonstrating the inconvenience at the time of the branch in the conventional pipeline processing. It is explanatory drawing for demonstrating the forwarding in the conventional pipeline processing. It is explanatory drawing for demonstrating the other forwarding in the conventional pipeline processing. In the conventional pipeline process, it is explanatory drawing for demonstrating the pipeline process considered in order to eliminate the inconvenience when using the same register before and behind.

Explanation of symbols

  1 is an instruction memory, 2 is an instruction register, 3 is a branch destination address calculation unit, 4 is an instruction decoding unit, 5 is an execution unit, 6 is a register file, 8 is an adder, 9 is a multiplexer, 10 is a program counter, and 11 is It is a control unit.

Claims (2)

In a pipeline processing unit in which instructions are pipelined,
Determination means for determining whether or not the instruction is a predetermined instruction that requires a plurality of cycles during execution processing;
When the determination means determines that the instruction is a predetermined instruction, the execution of the subsequent instruction is stopped during a period of a plurality of cycles in which the execution process of the predetermined instruction is performed, and the subsequent instruction is released after the stop is released. Control means for executing the processing of
A pipeline arithmetic processing apparatus comprising: The determination means determines whether or not the instruction is a load instruction that requires two cycles during execution processing,
When the determination means determines that the load instruction is a load instruction, the control means temporarily stops the operation of the program counter in the first cycle during the two-cycle period during which the execution process of the load instruction is performed. 2. The pipeline arithmetic processing apparatus according to claim 1, wherein execution of processing is stopped, and the program counter is operated in a second cycle to execute processing of the subsequent instruction.

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