JP2503223B2 - Prior control method - Google Patents

Description

DETAILED DESCRIPTION [Outline] When an inter-register operation instruction that does not require address calculation is executed, the value of the resulting condition code is calculated by prediction, and the processing is determined using the condition code. The instruction is intended to reduce the waiting time and speed up the processing by making an early decision on the processing using the predicted value.

[Industrial applications]

The present invention relates to a pipeline type processing device, and more particularly to a preceding control method in a case where a subsequent instruction uses a condition code of a preceding instruction to determine a process to be executed.

[Conventional technology]

Generally, an instruction executed by a processor requires an address calculation to access the main memory,
There are some which do not require address calculation of operands, such as inter-register arithmetic instructions.

In addition, in addition (AR), subtraction (SR), comparison (CR), and other operation instructions, exception conditions such as a negative operation result or overflow may occur. Is done.

Therefore, these operation instructions set a condition code of a value according to the operation result at the end of their execution, and subsequent instructions, for example, a branch (BR) instruction, determine the value of the condition code and respond. It is designed to separate processing.

By the way, when such an arithmetic instruction and a branch instruction are consecutive, the subsequent branch instruction must refer to the condition code only after the execution of the preceding arithmetic instruction is completed, so that the instruction must be kept waiting. become.

The conventional method will be described with reference to the flow chart of the pipeline shown in FIG.

In FIG. 4, the horizontal axis indicates the execution cycle of the pipeline, or is numbered for the sake of convenience so that sequential cycles can be referred to.

The illustrated example is a case where a branch instruction BR is executed following the addition instruction AR, and a subsequent instruction or a branch destination instruction is executed.

When each instruction is input to the pipeline, it sequentially flows through each stage of D, A, T, B, E, and W every cycle (τ). Here, D represents instruction decoding, A represents address calculation, T represents buffer memory tag check, B represents buffer reading, E represents execution, and W represents result writing.

The add instruction AR is input to the pipeline in the cycle, executes the add operation in the E stage of the cycle, and sets the value in the condition code (denoted by CC) in the W stage of the cycle according to the result.

The branch instruction BR is input to the pipeline in a cycle 1τ after the addition instruction AR.

The branch instruction BR calculates the address of the branch destination instruction at the A stage of the cycle, reads the branch destination instruction from the buffer at the B stage of the cycle, and prefetches (prefetches) the instruction at the beginning of the E stage. Hereinafter, this instruction is called a prefetch instruction. Then at the E stage of the cycle,
By referring to the value of CC set by the addition instruction AR, condition determination is performed, and it is determined whether the instruction to be executed next may be the instruction subsequent to the branch instruction BR or is changed to the prefetch instruction of the branch destination.

If the branch is successful, the prefetch instruction is input to the pipeline in a cycle delayed by 4τ from the input of the branch instruction BR.

On the other hand, in the case where the branch is not successful, a method is adopted in which the subsequent instructions of the branch instruction BR are sequentially input to the pipeline in consideration of the case where the branch is not successful (cycle or subsequent instruction is pipelined. Input), no special delay will occur. If the branch is successful, these subsequent instructions that have been input to the pipeline in advance are invalidated and no inconvenience occurs.

[Problems to be solved by the invention]

In a conventional pipeline type processing device, a waiting time is executed each time a combination of an operation instruction including a condition code setting process and a branch instruction that determines a condition by using the condition code and divides the process is executed. However, there is a problem that the processing speed of the processing device decreases as the frequency of appearance of these instructions increases.

[Means for solving problems]

Paying attention to the fact that the address calculation circuit is empty for instructions that do not need to calculate the address of the operand, such as register-to-register operation instructions, use this to calculate the predicted value of the condition code and use it for the condition code. By passing the instruction to the subsequent instruction, the waiting time of the subsequent instruction is shortened.

 The principle of the present invention will be described with reference to FIG.

FIG. 1 is a conceptual flow of a pipeline of a processing device according to the present invention. In the figure, is the condition code
The flow of the add instruction AR in the example of the preceding instruction accompanied by the process of setting CC, is the flow of the branch instruction BR as an example of the subsequent instruction that determines the next process using the condition code CC,
Is the flow of the prefetch instruction at the branch destination that executes the processing determined by the subsequent instruction.

In each instruction flow, D, A, T, B, E, W
Represents the sequential stages of the pipeline.

Similarly, commonly in each instruction flow, 10 is an instruction buffer, 11 is an instruction register, 12 is an address calculation circuit, 13 is a buffer memory, 14 is an arithmetic unit, 15 is a first condition code latch CC-1, 16 is a second. The condition code latches CC-2 and CC17 represent a condition comparison circuit. For the sake of convenience, only the hardware elements required for each are shown in each instruction flow.

The instruction buffer 10 temporarily holds a prefetched instruction to be input to the pipeline, and has a plurality of stages.

The instruction register 11 holds the instruction input to the pipeline at the D stage and is used to fetch the OP code and address information of the instruction.

The address calculation circuit 12 normally calculates an operand or an effective address for instruction fetch at the A stage based on the address information of the instruction. However, in the present invention, in particular, like an inter-register operation instruction such as an addition instruction AR,
In the case of the addition instruction AR which does not require the calculation of the effective address of the operand and involves setting the condition code CC, it is also used for the prediction operation of the condition code CC. In the latter case, a general purpose register is used as the input source.

The buffer memory 13 is provided in the middle for temporary storage of data in order to shorten the access time to the main storage device (not shown), and is used for fetching operands and instructions at the T and B stages.

The arithmetic unit 14 executes the arithmetic operation and the logical operation determined by the instruction at the E stage.

In the first condition code latch 15 (CC-1),
The value of the condition code CC generated based on the calculation result of the calculation unit 14 is set in the W stage.

The second condition code latch 16 (CC-2) is unique to the present invention, and the predicted value obtained when the address calculation circuit 12 performs the predictive calculation of the condition code CC at the A stage in the figure is: It is set at the T stage.

The condition comparison circuit 17 is unique to the present invention, and the CC value specified in the branch instruction BR that uses the condition code CC and the second condition code latch 16 (CC-
The predicted CC value set in 2) is compared at the A stage in the figure, and it is determined whether the prefetch of the branch destination instruction is executed or not according to the result.

In the figure, when the condition comparison circuit 17 detects that two CC values match, the condition is satisfied, that is, the branch is successful,
The address calculation circuit 12 causes the buffer memory 13 to be accessed in the T and B stages by the effective address of the prefetch instruction calculated in the A stage.

The prefetch instruction read from the buffer memory 13 is
At the beginning of the E stage, the data is stored in the instruction buffer 10 as shown in the figure, and is subsequently input to the pipeline.

[Action]

The operation of the present invention will be described with reference to FIG. 1 and the flow chart of the pipeline shown in FIG. FIG. 2 corresponds to the flow chart of the conventional method shown in FIG. 4, and since concrete examples of symbols, numbers and applied instructions in the figure are common, duplicate explanations are omitted. To do.

As shown in the second condition code latch 16 (CC-2) of FIG. 1, in the flow of the add instruction AR in FIG. 2, the prediction operation of the condition code using the address calculation circuit 12 at the A stage is performed. Then, the resulting value is set in the second condition code latch 16 at the T stage.
Set to (CC-2) so that it can be referenced by the next branch instruction BR. The condition code CC generated based on the result of the operation actually performed by the operation unit 14 at the E stage is the first condition code latch at the W stage.
Set to 15 (CC-1), but not used here.

In the flow of the branch instruction BR, at the A stage, the address calculation circuit 12 calculates the effective address of the prefetch instruction of the branch destination, and the condition comparison circuit 17 calculates the predicted value CC of the second condition code latch 16 (CC-2). To check. If the result is a successful branch, T stage and B
The buffer memory 13 is accessed at the stage, the prefetch instruction at the branch destination is read, and the prefetch instruction is stored in the instruction buffer 10 at the beginning of the E stage.

That is, in the E stage of the branch instruction BR, the add instruction AR
Does not need to refer to the actual CC set in the first condition code latch 15 (CC-1) in the W stage of the same cycle to make a condition determination, and immediately outputs the branch destination prefetch instruction to the instruction buffer 10 during the cycle. Can be put into the pipeline.

Therefore, the waiting time is shortened by one cycle (τ) as compared with the case of the conventional method shown in FIG. 4, and the delay from the branch instruction BR is 3τ.

The condition code prediction calculation performed by the address calculation circuit 12 does not require the numerical value of the result of the actual calculation performed by the calculation unit 14. For example, in the case of an addition instruction, the calculation result is 0, positive, negative, or carry. It suffices to know only in which state it is. However, in this case, since only the adder of the address calculation circuit can be used, the content of the prediction calculation is limited to simple ones such as addition and subtraction and comparison. However, the operation itself is the same as the operation performed by the operation unit 14 and is not simplified, and only the operation results are used. In the case of the addition instruction, 0, 1, 2, and 3 are set as the predicted values of the condition code CC depending on whether the result obtained by the prediction calculation is 0, positive, negative, or carry.

〔Example〕

FIG. 3 shows one of the pipelines of the processing apparatus according to the present invention.
It is a block diagram of an Example.

In FIG. 3, the block elements designated 10 to 17 are the same as those shown in FIG. In FIG. 3, the block elements newly added to show the detailed structure are indicated by 18 to 28. Below is a list of block elements in the figure.

10: Instruction buffer, which temporarily holds instructions waiting to be executed.

11: An instruction register, which holds an instruction input for execution.

12: An address calculation circuit that calculates the execution address of the operand or prefetch instruction. It is also used to calculate the predicted value of the condition code CC.

13: Buffer memory.

14: An arithmetic unit.

15: The first condition code latch (CC-1), and the operation unit 14 sets the condition code CC.

16: Second condition code latch (CC-2), which the address calculation circuit calculates and sets the predicted value of CC.

17: A condition comparison circuit, which compares the designated CC value in the instruction with the predicted CC value of CC-2 to judge the success / failure of the branch.

18: A general-purpose register group, which serves as an input data source to the address calculation circuit 12 when performing a prediction operation of a condition code.

19 to 21: Address registers, address calculation circuit 12
Configure the input register of.

22: An adder that adds the values of the address registers 19 to 21.

23: An effective address register (EAR), which stores the effective address calculated by the address calculation circuit 12.

24: A register number latch in use, which holds the number of the register used by the instruction preceding the pipeline.

25: A register comparison circuit that compares the numbers of registers used between instructions to detect interference.

26: Register interference latch, which is set to ON to indicate the presence of register interference when the register comparison circuit 25 detects a match in register number between instructions.

27: An instruction control circuit that determines whether to issue the instruction fetch request iFCH from the OP code of the instruction.

28: Main memory.

 Next, the operation of this embodiment will be described.

When the add instruction AR from the instruction buffer 10 enters the instruction register 11, the OP code is decoded and the instruction control circuit 27
to go into.

The instruction control circuit 27 determines from the decoding result of the OP code whether or not this instruction needs an address calculation. And in the case of instructions that need address calculation,
An operand or instruction fetch request is issued to the memory in the cycle of the stage A where address calculation is performed, but this request is not issued for an instruction that does not require address calculation. Therefore, in the case of an instruction that does not require address calculation, there is a margin of control, and this is used to input the contents of the general-purpose register to the adder 22 to perform simple operations such as addition and subtraction and comparison. In this case, add instruction AR
Is a register-to-register addition instruction, it is determined that it is not necessary to perform operand address calculation, the contents of the register designated by the addition instruction AR are read from the general-purpose register group 18, and are input to the address registers 19 and 20. To do.

In this case, not only the addition instruction AR but also the subtraction and comparison can be performed by inverting the contents as shown in the output of the address register 20.

The address registers 19 and 20 are input, the adder 22 performs the calculation, and the result is held in the register EAR23. At the same time, when the calculation result is "0", it is "0", and when it is positive, it is "1".
The second condition code latch 16 (CC-2) is set to "2" when the value is negative and "3" when there is a carry. At this point, we have already predicted CC.

Next, the add instruction AR proceeds to the E stage because it is not necessary to read the data from the buffer memory 13.

In the E stage, the arithmetic unit 14 is caused to perform actual arithmetic. Since an addition instruction or the like requires an operation between registers and an operation of writing to the registers, the contents of the designated register are passed to the arithmetic unit 14.

The arithmetic unit 14 arithmetically operates the passed data and writes the result to the register, and at the same time, sets the original CC in the first condition code latch 15 (CC-1).

Next, when the branch instruction BR is input to the instruction register 11, the OP code is decoded and enters the instruction control circuit 27. Here, it is judged again what kind of instruction, but in the case of a branch instruction, it is necessary to judge whether to branch to the designated address by looking at CC or to process the subsequent instruction as it is.

In the case of the conventional method, it is not possible to determine which to decide at this point in time, so calculate the branch destination address, issue a prefetch request for the instruction from that address, and at the same time input the subsequent instruction into the pipeline. Was done. Then, when the CC was set, the processing was decided, either one was selected, and the other instruction was invalidated.

However, in the method of the present invention, since the predicted CC has already been set, the conditional comparison circuit 17 is used to compare the CC portion (MASK portion) of the branch instruction BC, and it is determined whether or not to branch. If they match, branch.

If they match, the branch destination instruction fetch request (iFC
H) is output to the buffer memory 13. On the other hand, if they do not match, the instruction to fetch the branch destination instruction (iFCH) is not issued and the subsequent instruction is input to the pipeline.

On the other hand, in the conventional method, since the fetch request of the branch destination instruction is always issued, if there is no such instruction in the buffer memory 13, the data fetch request (REQUEST) must be sent to the main storage device 28. There wasn't. There is no problem if the branch is taken, but if it is decided not to branch, it means that a useless request is made to the main storage device, which causes a delay in other events.

However, according to the method of the present invention, it is possible to predict whether or not to issue a fetch request for a branch destination instruction by predicting CC, so if no branch is taken, the fetch request is not issued.
Since an extra request is not made to the main storage device, there is an advantage that it does not affect other events.

More importantly, assuming that the branch is decided by CC, in the conventional method, the CC is not decided yet when the prefetch instruction enters the instruction buffer 10, so that the execution is delayed by 1t. Since CC prediction is performed in the method, execution can be started when the prefetch instruction enters the instruction buffer 10.

〔The invention's effect〕

As described above, in the advanced control method according to the present invention,
If the preceding instruction that sets the condition code is one that does not perform address calculation, the condition code value is predicted early at the A stage of address calculation, and the subsequent instruction that uses the condition code also calculates the address. Since the predicted condition code is used in the A stage of, and the next processing is determined early, it is possible to issue a prefetch request for an instruction only when necessary, and it is also possible to execute the prefetched instruction. It can be started in the shortest possible time.

The efficiency of this pipeline is improved and the processing speed of the processing device is improved.

[Brief description of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a flow chart of a pipeline for explaining the operation of the present invention, FIG. 3 is a block diagram of the pipeline according to one embodiment of the present invention, and FIG. The figure is a flow chart of the pipeline according to the conventional method. In Fig. 1, 10: instruction buffer 11: instruction register 12: address calculation circuit 13: buffer memory 14: operation unit 16: second condition code latch CC-2 17: condition comparison circuit

Claims (1)

(57) [Claims] 1. In a pipeline type processor having an instruction control unit having an address calculation circuit (12), when an instruction for which address calculation is unnecessary and a condition code is set is executed, the execution end of the instruction is terminated. Without having it, the predicted value of the condition code is obtained by calculation using the address calculation circuit (12), and the condition code is predicted for the subsequent instruction that determines the content to be processed using the condition code. A preceding control method, which is characterized by passing a value and controlling to determine the contents to be processed early.