JPS6217841A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the titled device from the generation of overhead by storing the counted value of a count branching instruction in an address developing circuit part, and reading out the counted value to decide the branch of the count branching instruction. CONSTITUTION:An instruction from an instruction fetch memory accessing circuit part 23 is set up in an instruction register 1 of the address developing circuit part 21, an address is calculated by an adder 4 on the basis of the value of the register 1, the address is stored in a branching address register 8 of the circuit part 23, and the stored contents and an instruction address for instruction prefetch which is obtained from a preceding address register 9 are inputted to a selecting circuit 10. Then, the count branching instruction set up in the register 1 is recognized by an instruction decoding circuit 6 and the recognized information and the contents of a general register 2 are inputted to a count branching instruction branch deciding circuit 5. When a register value specified by an operation register specifying part R in the register 1 is not '1', an FF7 is set up, and in case of '1', the register 8 is selected by the circuit 10 and the branching address instruction is set up in the register 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the execution of branch instructions in an information processing device, and particularly to speeding up counting branch instructions.

(Prior Art) Conventionally, an information processing apparatus is configured as shown in FIG. In FIG. 4, 21 is an address expansion circuit section;
2 is an operand memory access circuit section, 23 is an instruction fetch memory access circuit section, and 24 is an arithmetic execution circuit section.

In FIG. 4, the instruction fetch memory access circuit section 2
3 is input to the address expansion circuit unit 21 via the signal line 101. Address expansion circuit section 21
At the same time as decoding the input instruction, address expansion of the operand is performed, and the obtained address is sent to the operand memory access circuit section 2 via the signal line 102.
21 outputs. Furthermore, the operand is taken out from the operand memory access circuit 22 at the above address, inputted to the arithmetic execution circuit section 241 via the signal line 103, and the arithmetic operation is executed according to the command operation instruction.

The result of the operation is stored in the memory via the signal line 104, and is also stored in the internal register of the address expansion section 21 via the signal line 105, during the execution process of the corresponding instruction. ends.

The execution process of the above instructions is controlled to be executed sequentially using multiple instructions as shown in Figure 5, and each instruction is executed in machine cycles to speed up the execution of each instruction. I can do it. This is an instruction execution control method called pipeline control.

In the information processing apparatus described above, branch instructions are generally executed as follows.

In FIG. 5, assuming that ■4 is a branch instruction, address expansion is performed at timing T,
The branch destination address is determined. This branch destination address is input to the instruction fetch memory access circuit unit 23 via the signal line shown in FIG. 4, and the branch destination instruction J1 is fetched at timing T. On the other hand, the instruction Ill on the side where the branch is not taken is fetched at timing T, and its address is expanded at timing T. Branch instruction I
Assuming that , is a conditional branch instruction obtained by the operation result of instruction I, instruction I at timing TaJ.

Based on the operation result, either the operand memory access of instruction I or the address expansion of instruction 6 is selected at timing T.

If one of the above is selected, the other is canceled.

In this way, if the branch instruction (2) is taken, timing 2T is required for execution, and if the branch is not taken, it can be executed at timing IT. The k15 diagram is
This is a time chart when the branch instruction (2) is established.

Next, let us assume that a counting branch instruction as shown in FIG. 6 is to be executed. During execution, the count branch instruction is subtracted by ``1'' from the value (R) (stored in the register) indicated by R in the instruction word, and if that value is not ``0'', the branch destination address ``[
The instruction branches to 'X)+fBl+D'', and if it is 'O#', the branch will not be taken.

Conventionally, in information processing devices using pipeline control, the above-mentioned count branch instruction is
As shown in Figure 7 (it was executed as shown in Figure 7)
In the figure, a counting branch instruction I calculates a branch destination address by calculating the address expansion "(X)+(B)+D" at timing T, and at timing T4, the branch destination instruction J, or fetched. Next, at timing T, the operation (R
)-1 was executed, and as a result, address expansion of the branch destination instruction J1 was started at timing T.

In other words, conventionally, since the operation execution circuit unit 24 performs the operation (J-1), there is a waiting time for waiting for the operation result, and when a branch is established, at least timing 3T is required as the execution time of the branch instruction. , which required 2T machine cycles when the result was not satisfied.Furthermore, in this case, even though the branch decision based on the operation result of (It)-1 was made at the edge rather than the instruction fetch memory access, the branch decision Previously, there was a risk of extra memory accesses, which caused overhead.

On the other hand, in order to improve the performance on the side where the branch is not taken, it is necessary to issue the instruction fetch memory access of instruction 4 at timing T in FIG. However, since the above memory access is performed before the branch decision, there is a possibility that the access will be canceled, and if the branch is established, the above-mentioned wasteful memory access will be issued. Since a memory access is performed before the branch, there is a possibility that the access will be canceled, and if a branch is taken, there is an overhead for issuing a wasteful memory access.

An object of the present invention is to provide an information processing apparatus in which address expansion, memory access, and arithmetic execution in the execution of an instruction are executed in a pipeline in respective circuit sections, and a register that stores the count value of a counting branch instruction in the address expansion circuit section. It is an object of the present invention to provide an information processing apparatus which eliminates the above-mentioned drawbacks and is configured so that no overhead is generated by checking the contents thereof and performing branch judgment of counting branch instructions.

(Means for Solving the Problems) An information processing device according to the present invention includes at least an address expansion circuit unit, an instruction fetch memory, and a reaccess circuit, and includes address expansion, memory access, and
and the execution of calculations is pipelined.

In the present invention, the address expansion circuit section includes an instruction register means for storing the count value of the count branch instruction, a count branch instruction branch judgment means for successively outputting the above-mentioned hand value and makes a branch judgment of the count branch instruction; The instruction register means includes addition means for performing a γ address 1f calculation of a branch destination address using the index value, base value, and displacement value contained in the instruction register means.

On the other hand, the instruction fetch memory access circuit section includes a branch instruction branch determination means for storing the branch destination address outputted from the addition means, and an instruction address for pre-fetching an instruction from the branch destination address in advance.
A preceding address register means for updating the contents by counting up the instruction address at any time, and a preceding address register means corresponding to the output of the counting branch instruction branch judgment means and corresponding to the output of the branch instruction branch judgment means. a selection means for selecting an output, and a high-speed memory access for performing address conversion at high speed according to the address output from the selection means and sending address information determined by the result of the address conversion to the instruction register means. The device is configured to include means.

In the above, the present invention is configured so that a branch destination address can be determined and a branch determination can be made in the address expansion phase in the pipeline processing of the upper IF count branch instruction.

(Embodiment) Next, the present invention will be described with reference to the drawings.0 FIG. 1 is a block diagram showing an embodiment of a part of an information processing apparatus according to the present invention, including an address expansion circuit section and an instruction fetch memory. FIG. 3 is a block diagram showing details of an access circuit section. In FIG. 1, 1 is an instruction register, 2 is a general-purpose register, 3 is a register at the base, 4 is an adder circuit, 5 is a counting branch instruction branch judgment circuit, 6 is an instruction decode circuit, and 7
is a flip-flop, 8 is a branch destination address register, 9
1 is a preceding address register, 10 is a selection circuit, and 11 is a high-speed memory access circuit.0 In FIG.
3 through the signal line 101 are correctly aligned and set in the instruction register 1. In the general register 2 and pace register 3 respectively,
Information is set from each arithmetic execution circuit section 24 via a signal line 105. The index value for address calculation is sent from the index specification part (X) of the instruction register 1 to the general-purpose register 2 via the signal line 108, and the base value is sent from the base specification part (B) to the signal line 109. These are sent to the pace register 3 via the signal line 110 from the general register 2 and pace register 3 respectively.
, 111.

The address adder circuit 4 receives information (from (X) +
This is for calculating the address of (B)+D. The output of the address addition circuit M4 is input to the fidget operand memory access circuit section 22 and the instruction fetch memory access circuit section 23 via the signal line 102 and the signal line 106.

Further, the general-purpose register 2 is configured to be able to read out the contents sent from the operation register designating section (R) of the instruction register 1 via the signal line 107 to the signal line 113f, and input the contents to the counting branch instruction branch judgment circuit 5. Ru. Count branch instruction branch judgment F] 1 path 5 outputs information on signal lines 114 and 115 outputted from the instruction decoding circuit 6 that recognizes the count branch instruction set in the instruction register l, and sends it out via the signal line 113. When the register value (R) specified by the arithmetic register specifying section ( ) ( ) is not "1", the flip-flop 7 is set.

The counting branch instruction branch determination circuit 5 is composed of a logic circuit shown in FIG. 2, for example. In Figure 2, 12 is (F
t) (Detection circuit for detecting 1, 13, 15,
16 is a NAND gate, and 14 is a T/C output gate.

A branch destination address register 8 provided in the instruction fetch memory access circuit section 23 is used to hold a branch destination address given by the output of the address adder circuit 4. The preceding address register 9 is used to hold an instruction address in advance for prefetching an instruction, and to count up as needed. Preceding address register 9
and the contents of the branch destination address register 8 are input to the selection circuit 10. The selection circuit 10 is switched by the signal output from the flip-flop 7 to the signal line 116.

The high-speed memory access circuit 11 consists of an address conversion table for performing address conversion at high speed and an instruction cache memory as a copy of the instruction word memory. The output is sent to the signal line 101 as the output of the instruction fetch memory access circuit section 23.

FIG. 3 shows an example of a time chart of count branch instructions executed in the above configuration. Next, the operation will be explained with reference to the above time chart.

In FIG. 3, if counting branch instruction I is executed, address expansion is performed at timing T, and the branch address is determined. At this time, at the same time (
The contents of the register specified by the arithmetic register specifying section (R) of the instruction register 1 are read out, and the value is checked by the counting branch instruction branch judgment circuit 5. That is, the register value specified by the arithmetic register specifying section (R) of the instruction register 1 (if R1 is not 11#, the set signal for setting the flip-flop 7 according to the logic circuit shown in FIG. 2 or the signal line 118) When the branch destination address of the counted branch instruction obtained at timing Ts is set in the branch destination address adder circuit 8 at timing T4, at the same time At this time, the address of the flip-flop 7 set on the set signal line 118 is held.
If the value of is 1'', the subsequent instruction during address expansion ■
, is canceled, the branch destination address register 8 is selected in the selection circuit 10, and the high speed memory access circuit 11 is accessed by the output sent from the selection circuit 10 via the signal line 117. Next, at timing T5, the branch destination instruction J1 is set in the instruction register 1, and address expansion of the instruction is started.

As described above, the execution time when the branch of the count branch instruction is established in the first embodiment is completed within the time of timing 2T. On the other hand, when the branch is not taken, the address expansion of the subsequent instruction I, whose address is being expanded, is enabled at timing T4. At this time, since the flip-flop 7 is not set, the preceding address register 9 is selected by the selection circuit 10, and at this time, the instruction
The preceding instruction following 1 ■4 is high-speed memory access circuit 1
Fetched from 1. Next, at timing T, the operand fetch access circuit s22 executes the instruction 11.
The operand of instruction I4 is fetched, the instruction word of instruction I4 is set in instruction register 1#, and address expansion is started.

As described above, when the branch of the count branch instruction in this embodiment is not taken, execution is completed within the time of timing IT without causing any disturbance in the pipeline.

(Effects of the Invention) As explained above, the present invention enables high-speed execution of the counting branch instruction by making a branch judgment in the address expansion phase of the counting branch instruction in the execution of the counting branch instruction. , since it is possible to control so that unnecessary memory accesses are not performed, there is an effect that overhead can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a block diagram partially showing an embodiment of an information processing apparatus according to the present invention, and shows details of an address expansion circuit section and an instruction fetch memory access circuit section. FIG. 2 is a block diagram showing details of the counting branch instruction branch determination circuit in FIG. 1. FIG. 3 is a time chart showing an example of the execution of the count branch instruction shown in FIG. FIG. 4 is a block diagram showing the functions of a general information processing device. FIG. 5 is a time chart showing the state of instruction pipeline control in the information processing apparatus of FIG. 4. FIG. FIG. 6 is an explanatory diagram showing an example of an instruction format of a counting branch instruction. FIG. 7 is a time chart showing an example of execution of a counting branch instruction. 1...Instruction register 2...General-purpose register 3...
・Pace register 4... Address addition circuit 5...
Counting branch instruction Branch determination circuit 6...Instruction decoding circuit 7...Flip-flop 8...Branch destination address register 9...Preceding address register IO...Selection circuit 11...High speed memory access circuit 12 ...Detection circuits 13, 15, 16...NAND gate 14
...T/C output gate 21...Address expansion circuit section 22...Operand memory access circuit section 23...
Instruction fetch memory access circuit section 24...Arithmetic execution circuit section Characteristics Applicant NEC Corporation Agent Patent Attorney Hisashi Inoro et al. Lala

Claims (1)

[Claims] In an information processing device that includes at least an address expansion circuit section and an instruction fetch memory access circuit section, and performs pipeline processing of address expansion, memory access, and arithmetic execution in instruction execution, the address expansion circuit section is configured to perform count branch instruction processing. an instruction register means for storing numerical values; a counting branch instruction branch judgment means for reading the counted value and making a branch judgment of the counting branch instruction; an index value, a base value, and The instruction fetch memory access circuit section stores the branch destination address outputted from the addition means. a branch destination address register means for pre-fetching an instruction from the branch destination address; and a preceding address register means for storing an instruction address for pre-fetching an instruction from the branch destination address and updating the contents by counting up the instruction address at any time. , selection means for selecting either the output of the branch destination address register means or the output of the preceding address register means in response to the output of the counting branch instruction branch determination means; and an address output from the selection means. and high-speed memory access means for executing address conversion at high speed according to the address conversion result and sending address information determined by the result of the address conversion to the instruction register means, An information processing device characterized in that it is configured to be able to obtain a branch destination address and make a branch determination in an expansion phase.