JPH02236727A - Information processor - Google Patents

Abstract

PURPOSE:To execute an indirect branch instruction at high speed by adding a decoder, a register, and a selector, and directly taking the instruction of a branch destination by a branch destination address taken out from a memory. CONSTITUTION:The memory 11 can be accessed by the output 10-1 of a real address register 10, and taken out data 11-1 is aligned with an aligner 12, and a result 12-1 is stored in the register 13, and simultaneously, it is sent to the selector 24. The decoder 20 decodes the instruction code 1-1 of an instruction held at an instruction register 1, and judges whether or not the instruction held at the instruction register 1 is the indirect branch instruction, and a result 20-1 is sent via the registers 21-23, which controls the selector 24. When the instruction is the indirect branch instruction, the selector 24 is controlled so as to select the output 12-1 of the aligner 12. Thereby, since the branch destination address taken out from the memory is stored in a logic address register without passing an adder for address calculation, execution speed can be accelerated so much.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application J] The present invention relates to an information processing device, and particularly to a control method for fetching instructions at a branch destination when an indirect branch instruction is executed. [Prior Art] When executing an indirect branch instruction, in conventional information processing devices, the branch destination address retrieved from memory is passed through an address calculation adder, stored in a logical address register, and the branch destination instruction is retrieved. [Problems to be Solved by the Invention] In the conventional method described above, when executing an indirect branch instruction, the branch destination address retrieved from memory is passed through an address calculation adder and then stored in a logical address register, and the branch destination instruction is executed. The downside is that the execution speed is slow because it has to be retrieved. [1,000 steps to solve the problem] The information processing device of the present invention includes a decoder that decodes an instruction held in an instruction register and determines whether it is an indirect branch instruction, and an address calculated by an address calculation adder. or a selector that selects a branch destination address taken out from memory, and a decoder's decoded result is carried around until the memory is accessed, and when the decoded result indicates an indirect branch instruction, the branch destination taken out from memory is selected. and a register for controlling the selector to make a selection.

[Effect]

Since the branch destination address taken out from memory is stored in the logical address register without passing through the address calculation adder, the execution speed is increased accordingly.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus according to the present invention.

Instruction word register 1 is an instruction register that holds instruction words. The pace register file 2 and the general-purpose register file 3 are used to store the outputs 1-2, l of the instructions held in the instruction register 1.
-3, its contents are read and held in registers 4 and 5, respectively. The register 6 holds the displacement part 14 of the instruction held by the instruction register 1.

Adder 7 for address calculation is output 4 of register 4, 5.6
-1.5-1. The address of the operand is calculated from 6-1, and the result 7-1 is stored in the logical address register 8 via the selector 24. The real address translation buffer 9 is accessed by the output 8-1 of the logical address register 8,
The extracted execution address 9-1 is stored in register IO. Memory 11 is output 1 of real address register lO
The data 11-1 accessed and retrieved by 0-1 is aligned by the aligner 12, and the result 12-1 is stored in the register 1.
3 and simultaneously sends it to the selector 24. The decoder 20 decodes the instruction code 1-1 of the instruction held in the instruction register 1, and inputs the instruction code 1-1 to the instruction register 1. It is determined whether the instruction held in is an indirect branch instruction, and the result is 20-1.
registers 21, 22. 23 to control the selector 24, and in the case of an indirect branch instruction, the output 12 of the aligner l2
The selector 24 is controlled to select -1.

For example, if instruction A held in instruction register 1 in To cycle is an indirect branch instruction, in T cycle, register 4.5 contains the pace register file 2 and general register file 3 read by instruction A. The contents are stored respectively, and the displacement portion of instruction A is stored in register 6. At this time, the decoder 20 simultaneously decodes the instruction code of instruction A, and stores information (・"l") indicating that it is an indirect branch instruction in the register 2l.In the T2 cycle, the address calculation river adder 7
A logical address is calculated and stored in the logical address register 8. Information 21-1 in the register 2l is also stored in the register 22. In the T3 cycle, the real address translation buffer 9 is accessed using the output 8-1 of the logical address register 8, and the extracted real address is stored in the register IO. Information 22-1 of the register 22 is stored in the register 23. In the T4 cycle, the memory 11 is accessed using the output 10-1 of the real address register 10, the branch destination address is taken out, aligned by the aligner l2, stored in the register l3, and simultaneously sent to the selector 24. At this time, information 23-1 that the data retrieved from memory 1 is the branch destination address is sent from the register 23 to the selector 24, and the selector 24 outputs the output of the aligner 12, 23-1.
1 is selected and stored in the logical address register 8.

FIG. 2 shows a time chart of the series of operations described above, in which (a) is a time chart according to the conventional method, and FIG. 2 (b) is a time chart according to the method of this embodiment. In the figure, To ,T,,T2,T,,T4,T,
,T. represents a machine cycle, A represents the instruction A, and Ao represents the branch destination address of the instruction A. In the figure (a), the branch destination address of instruction A, 80, is stored in the logical address register 8 in the TS cycle, whereas in the figure (b), it is stored in the logical address register 8 in the T4 cycle. be done. In other words, when an indirect branch instruction is executed in this embodiment, the method according to the present invention can be executed one machine cycle faster than the conventional method.

(Effects of the Invention) As explained above, the present invention adds a decoder, a register, and a selector, and directly retrieves the branch destination instruction using the branch destination address retrieved from memory, thereby enabling indirect branch instructions. The effect is that it can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the information processing device of the present invention, FIG. 2(a) is a time chart according to the conventional method,
FIG. 2(b) is a time chart according to the method of this embodiment. 1...Instruction register, 4.5.6...Register, 8...Logical address register, +0. 13, 21, 22. 23...Register, 2...Pace register file, 3...General purpose register file, 7...Address adder 9...Real address translation buffer, 1l...Memory, l2...Aligner, zO ...Decoder, 24...Selector.

Claims (1)

[Claims] 1. Information for executing an indirect branch instruction that does not specify a branch destination address as an operand address, but rather executes a branch based on a branch destination address that is placed in advance in a memory area specified by the operand address. In the processing unit, there are a decoder that decodes the instruction held in the instruction register and determines whether it is an indirect branch instruction, and a selector that selects the address calculated by the address calculation adder or the branch destination address retrieved from memory. , a register that controls a selector to carry around the decoding result of the decoder until the memory is accessed, and to select the branch destination retrieved from the memory when the decoding result indicates an indirect branch instruction. Characteristic information processing device.