JP2842930B2 - Instruction readout circuit used in test processor of semiconductor integrated circuit test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to, for example, a test processor of a semiconductor integrated circuit test apparatus, and relates to an instruction reading circuit that reads an instruction from an instruction memory, that is, fetches (captures) an instruction.

[Prior Art] FIG. 8 shows a conventional instruction reading circuit. The instruction read from the instruction memory 11 is stored in the register 12, the instruction in the register 12 is decoded by the instruction decoder 13, and the instruction is executed by the execution unit 13 according to the decoded content, and the next address is calculated. Then, the instruction memory 11 is read out at the calculated address, and the same operation is performed thereafter.

Each instruction has a fixed word type, and the number of words formed by the instruction is different. Decoding the instruction and knowing the word type (number of words) of the instruction for the first time, then calculating the address of the next instruction to read it can. For example, as shown in FIG. 9, instructions A, B, C,... Are sequentially stored in the instruction memory 11, and the word type of the instruction A is 1 (the number of words is 1) and the word type of the instruction B is 2
(The number of words is 2) and the word type of the instruction C is 3 (the number of words is 3), when the address of the instruction B is address 1, the instruction B is read, decoded, and its word type is 2 Knowing that there is, an address 3 for reading the next instruction C is obtained by adding 2 to the address 1 of the instruction B.

Therefore, as shown in FIG. 10, the first instruction A is read, decoded, and executed. At that time, the next instruction B can be read at the same time. That is, until the decoding of the read instruction is completed, the next instruction A is read. Cannot be read. Therefore, there is a decoding period from the execution of one instruction to the next execution, and it is not possible to execute instructions continuously, and there is a disadvantage that the processing time as a whole becomes longer. Further, it is necessary to hold the input data of the instruction decoder 13 until the decoding operation is completed by the instruction decoder 13, that is, until the word type is determined.

[Means for Solving the Problems] An instruction reading circuit used in a test processor of a semiconductor integrated circuit test apparatus according to the present invention includes: an instruction register for storing an instruction read from an address specified by an adder of an instruction memory; The instruction decoder to which the instruction stored in the register is supplied, the word type register in which the word type in each read instruction is stored at the same time as the instruction is stored in the instruction register, and the word type register A word type decoder that decodes a stored word type to calculate the number of instructions words, an addition register that stores data output by the adder, and an adder that adds the output of the word type decoder and the output of the addition register And

FIG. 1 shows an embodiment of the present invention. The instruction memory 11 is read from the address from the address operation unit 15, and the read instruction is stored in the first and second registers 16, 1
7 are stored alternately. One of the instructions in the first and second registers 16 and 17 is selected by the multiplexer 18, and the selected instruction is supplied to the instruction decoder 13. The execution unit 14 executes the instruction according to the decoding result of the instruction decoder 13. The word type in each instruction read from the instruction memory 11 is stored in the word type register 19, and the word type in the word type register 19 is decoded by the word type decoder 21 and read out next according to the decoding result. The address is calculated by the address calculator 15. First register 16, second register 17, word register 1
The acquisition of each of the items 9, the selection control of the multi-type lexer 18, the initialization of the address operation unit 15, and the like are performed by the sequencer 22 that controls the entire sequence.

As described above, in the present invention, the word type decoding of the instruction and the operation of the next address are performed in parallel with the decoding and execution of the instruction. The processing can be performed, and the instruction can be read next without having to wait for the address calculation by the execution unit 14. Moreover, since the read instruction is stored alternately in the first and second registers 16 and 17, even before the decoding of the previously read instruction is completed, the register which is not the register in which the previously read instruction is stored is stored. The newly read instruction can be stored in the register.

Therefore, as shown in FIG. 2, the first instruction is read out, stored in the first register 16, and the first instruction is manually coded, and at the same time, the address of the second instruction is calculated. The second instruction is read at the calculated address and stored in the second register 17. Simultaneously with the execution of the first instruction, the second instruction is decoded by the instruction decoder 13, and the address operation of the third instruction is performed. Store in register 16. Hereinafter, the same operation is performed. Conventionally, the next instruction is read in the execution state (step) of the read instruction, but in the present invention, the next instruction can be read in the decode state (step) of the read instruction, and the processing speed is improved accordingly.

As shown in FIG. 3, a word type 3 instruction A, a word type 2 instruction B, a word type 1 instruction C, and a word type 3 instruction D are sequentially stored in the instruction memory 11 and are sequentially read out. The operation will be described using the case as an example. First, as shown in FIG. 4, the register 23 in the address operation unit 15 is initialized to zero, and before reading from the instruction memory 11, the output of the word type decoder 21 is zero.
The output of the adder 24 for adding the register 23 and the output of the word type decoder 21 is zero, the address 0 is given to the instruction memory 11, the instruction A is read, and this is stored in the first register 16. At the same time, the word type Aw = 3 is stored in the word type register 19. Next, as shown in FIG.
Instruction A in register 16 is selected, and instruction A is
At the same time, Aw = 3 decoded by the word type decoder 21 is added to zero of the register 23, and stored in the register 23, the address 3 and the instruction memory 11 are read, and the instruction B is read. Issued and stored in the second register 17 and its word type
Bw = 2 is stored in the word type register 19. Next, as shown in FIG. 6, the instruction A is executed by the execution unit 14, the instruction B of the second register 17 is selected by the multiplexer 18, the instruction B is decoded by the instruction decoder 13, and the word type decoder 21 is decoded. , The word type Bw = 2 is decoded, and the result is added to 3 of the register 23. The addition result 5 is stored in the register 23 and given to the instruction memory 11 as the address 5, and the instruction C is read out. Instruction C is stored in first register 16 and its word type Cw = 1 is stored in word type register 19. Next, as shown in FIG.
Is executed, the instruction C of the first register 16 is selected by the multiplexer 18, the instruction C is decoded by the instruction decoder 13, and the word type Cw is set to 1 by the word type decoder 21.
Is decoded, and this is added to 5 of the register 23.
Address 6 is given to instruction memory 11,
Instruction D is read, instruction D is stored in second register 17, and its word type Dw = 3 is stored in word type register 19.

The instruction stored in the first register 16 is supplied to the instruction decoder 13 and then the next instruction is stored in the first register 16, that is, the hardware configuration is such that the number of registers is one. Yes, but in that case the software is slightly more complicated.

[Effects of the Invention] As described above, according to the present invention, an instruction is read out and stored alternately in the first and second registers, and the word type of the instruction is stored in the word type register. In order to perform the word type decoding and the next address operation, the instruction can be executed in each step,
Processing can be performed at a higher speed than before.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a flow of processing in the circuit of FIG. 1, FIG. 3 is a diagram showing an example of an instruction in the instruction memory 11, and FIG.
7 are diagrams showing states in respective steps when the instructions shown in FIG. 3 are sequentially read, FIG. 8 is a block diagram showing a conventional instruction reading circuit, and FIG. 9 is an example of the contents of an instruction memory. FIG. 10 is a diagram showing a flow of processing in the conventional circuit shown in FIG.

Claims (1)

(57) [Claims] An instruction register for storing an instruction read from an address specified by an adder of an instruction memory; an instruction decoder for supplying an instruction stored in the instruction register; and an instruction register storing the instruction in the instruction register At the same time as
A word type register for storing a word type in each read instruction; a word type decoder for decoding the word type stored in the word type register to output the number of words of the instruction; and the adder An instruction reading circuit used in a test processor of a semiconductor integrated circuit test device, comprising: an addition register that stores data output by the adder; and an adder that adds the output of the word type decoder and the output of the addition register.