JPS6265133A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To execute plural instructions just in a single instruction time by checking whether or not the prefetched plural instructions can be executed after decoding them simultaneously and synthesizing those instructions. CONSTITUTION:Plural instructions set in two pairs, etc. which are prefetched by a prefetch instruction buffer 1 with the address given from a buffer read address register 2 and the address passed through an adder 3. These read-out instructions are decoded by an instruction decoder 6 and at the same time it is checked whether two instructions can be synsethized into a single instruction or not. If this synthesizing is possible, selectors 7-9 are controlled for selection of operands and instructions to be synthesized. These selected operands and instructions are stored in operand registers 10-12 and an instruction register 13 respectively. Then plural instruction, e.g., two instruction are executed by a single instruction through a general-purpose register group 14, an arithmetic unit 15, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction prefetching device for an information processing device, and more particularly to synthesis of prefetched instructions.

(Prior art) Conventionally, this instruction prefetching device stores the prefetched instruction in a storage means, decodes the prefetched instruction according to the instruction execution order, and sends the decoded instruction to the calculation unit. Ta.

(Problems to be Solved by the Invention) In the conventional instruction prefetching device described above, one instruction and button decoding are executed in sequence, so multiple prefetched instructions are simultaneously decoded and combined into one operation. Even if it is possible to achieve
The disadvantage is that the calculation can only be performed for each instruction, and the calculation time is significantly longer than the execution time of a single instruction.

The purpose of the present invention is to temporarily hold a plurality of prefetched instructions, detect whether or not the prefetched instructions can be simultaneously decoded and synthesized, and, if they can be combined and operated, combine them. It is an object of the present invention to provide an instruction prefetching device configured to eliminate the above-mentioned drawbacks and shorten calculation time by sending calculation instructions to a calculation section.

(Means for solving the problem) The instruction prefetching device according to the present invention includes prefetched instruction holding means,
It is configured to include an instruction decoding means and a selector means.

The prefetched instruction holding means is for holding a plurality of prefetched instructions.

The instruction decoding means simultaneously decodes multiple prefetched instructions,
This is to detect whether it is possible to synthesize and execute.

The selector means is for sending the combined calculation command to the calculation section if the calculation can be executed by combination.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an instruction prefetching device according to the present invention. In FIG. 1, a 1-digit prefetch instruction buffer, 2 a back read address register, 3.
4 are the first and second adders, respectively, 5.7.8.9
are the first to fourth selectors, 6 is an instruction decoder, and 1 is the first to fourth selector.
0 to 12 are the first to third operand registers, respectively;
13 is an instruction register, 14 is a general-purpose register, and 15 is an arithmetic unit.

In FIG. 1, a prefetch instruction buffer 1 inputs and holds a prefetched instruction from a memory (not shown), and transfers the contents of the buffer read address register 2 and the contents of the buffer read address register 2 to the first buffer 9. The value decremented by 1 by the device 3 is accessed by the signal lines 101 and 102 and read out at the same time. The instructions read simultaneously are applied to the instruction decoder 6 via signal lines 103 and 104, and are simultaneously decoded by the instruction decoder 6.

At this time, it is also checked whether two consecutively issued instructions can be combined into one instruction. ``If two instructions can be combined into one instruction, the first selector 5 selects an address obtained by decrementing the contents of the packed read address register 2 by 2 by the second addition 54, and stores it in the buffer read address register 2. If two instructions can be combined into one instruction, the second to fourth selectors 7 to 9
selects operands and instructions to be synthesized and stores them in first to third operand registers 10 to 12 and instruction register 13, respectively. 1st operand register 1
0 specifies the general-purpose register for writing in the general-purpose register group 14, and specifies the second operand register 11 and the third
The operand register 12 specifies a general-purpose register for reading out of the general-purpose register group 14. instruction register 1
3 specifies the operation of the arithmetic unit 15.

Next, the operation of the instruction preemption device shown in FIG. 1 will be explained.

As shown in FIG. 2, instructions LPRR2, 4 are prefetched at address 2 of prefetch instruction buffer 1, and instruction 5Q is prefetched at address 1.
Assume that RR2,,5 are preempted. Buffer read address register 2 contains the instruction LD to be executed next.
It shows address 2 of RR,,4.

The instruction LDRR2,,4 digits (G2)←(G4) means,
Instruction 5BRR2,, 5 digits GR2)←(GR2)-(G
R5). Here, (GRl)(i=2.4.
5...) represents the contents of the i-th register of the general-purpose register group 14. Preemption υ instruction buffer 1 is signal line 10
The contents of addresses 2 and 1 are simultaneously read by XIBRA on signal line 102 and YIBRA on signal line 102, and the instruction w
ll is input into the secret chamber.

The instruction decoder 6 reads instructions LDRR2, 4 and instruction 5BRR2.
,,5 and synthesize (GR2)←(GR4)-(GR5
), it is determined that synthesis is possible. Second
- Select the fourth selectors 7 to 9, set the address specifying GR2 in the first operand register 10, set the address specifying the second operand register 11KHGR4, and set the address specifying GR2 in the first operand register 11. Set the address specifying GR5 to .

An instruction for instructing subtraction is set in the instruction register 13. That is, the above operation is a combination of instructions LDRR2, 4 and instructions 5BRR2, 5.

Next, GR4 and GR specified by the second and third operand registers 11.12 of the general-purpose register group 14 are
5 is read out, and the subtraction specified by the instruction register 13 is executed by the arithmetic unit 15.

That is, the result of (GR4)-(GR5) is
This is the output from. The result obtained from the arithmetic unit 15 is written to GR2 designated by the first operand register 10.

As described above, instructions LDRR2,,4 and instruction 5BR
R2,,5 are combined into one instruction.

Since the second adder 4 is selected by the first selector 5, 2-2=0 is input to the buffer read address register 2 of the prefetch 9-instruction buffer 1. That is, instructions LDRRI, , 5 are shown, and the address of the next instruction to be executed is shown.

(Effects of the Invention) As described above, the present invention has the advantage that a plurality of instructions can be executed in the execution time of one instruction by simultaneously decoding and combining a plurality of prefetched instructions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an instruction prefetching device according to the present invention. FIG. 2 is an explanatory diagram showing an example of instructions stored in the prefetch instruction buffer. 1... Prefetch instruction buffer 2... Buffer read address register 3.4...
Adders 5.7-9...Selector 6...Instruction decoder 10-13...Register 14...General-purpose register group 15...Arithmetic units 101-109...Signal line

Claims (1)

[Claims] a prefetched instruction holding means for holding a plurality of prefetched instructions; an instruction decoding means for simultaneously decoding the plurality of prefetched instructions and detecting whether or not they can be executed by combining them; An instruction prefetching device comprising: selector means for sending the combined operation instruction to an operation section when the operation can be executed.