JPS622363A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To execute quickly an operation to data which has been stored in a vector register, by using an operator which has been provided in a scalar arithmetic unit, by providing a selecting means on scalar and vector operating parts, respectively. CONSTITUTION:Selecting means 110, 210, 310 and 410 which have been provided in a vector operating part 100 select an input of vector registers 130, 230, 330 and 430. Also, selecting means 550, 560 which have been provided in a scalar operating part 500 select an input of a scalar arithmetic unit 570. That is to say, thes means 550 and 560 select an input of the unit 570 from in outputs of scalar registers 530, 540 or outputs of vector registers 130, 140, 230, 240, 330, 340, 430 and 440. In this way, a result of operation of the unit 570 can be inputted directly to the vector register 130, etc. through the means 110 by the means, and a data which has been stored in the vector register can be calculated quickly by using an operator in the unit 570.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic device, and particularly to an arithmetic device having a vector arithmetic section and a scalar arithmetic section.

[Conventional technology]

Conventionally, this type of arithmetic device has a vector arithmetic unit 100 having a plurality of vector pipes PL and P2, as shown in FIG.
．． Scalar operation unit 500. It is composed of a main memory 600, a vector calculation unit 100, a scalar calculation unit 500, and a control unit 700 that controls the main memory 600, and each vector pipe PL, P2 is a vector for the first operand that stores a plurality of element data. Register 130.2
30 and a vector register 140 for the second operand.
240, selection means 110, 210 for selecting the input of the vector register 130 for the first operand from the output of the main memory 600 or the output of the vector arithmetic unit 150, 250, and the vector register 140 for the second operand. Selection means 1 for selecting 240 inputs
20, 220 and vector registers 130, 140, 2
30, 240, and vector calculation units 150, 250 that perform calculations on the output data of 30, 240.

The scalar operation unit 500 also includes a scalar register 530 for the first operand, a scalar register 540 for the second operand, and a scalar register for the first operand from among the output of the main memory 600 or the output of the scalar operation unit 570. Selection means 510 for selecting the input of 530 and a scalar register 54 for the second operand
It consisted of a selection means 520 for selecting manual input of 0, and a scalar calculation unit 570 for performing calculations on the output data of the scalar registers 530 and 540.

When performing vector calculation, the selection means 1
10. Vector operation data selected by 120, 210, 220 is transferred to vector register 130.140.2.
30° 240-, and are stored in vector registers 130, 140, 230 .
The data sequentially read out from 240 is sequentially calculated by the vector calculation units 15Q and 25Q, and the selection means 110 and 210
Each pipe PI,
When P2 is performed simultaneously and a scalar operation is performed, the data selected by the selection means 510 and 520 is stored in the scalar registers 530 and 540 in advance, and the scalar registers 530 and 5 are
The data read from the scalar operation unit 570
and passes through the selection means 510 to the scalar register 5.
30 or passed through selection means 520 and stored in scalar register 540.

[Problem that the invention seeks to solve]

By the way, there are various types of operations that can be performed on data stored in vector registers, and some of them, such as division, require arithmetic units with extremely complex hardware configurations. be. However, in the conventional arithmetic device described above, the vector arithmetic unit 100 and the scalar arithmetic unit 500 are configured independently, so when performing division on data stored in a vector register, for example, each vector Arithmetic unit 150.2 in the pipe
50 must be provided with such a divider, which poses a problem in that the amount of hardware increases significantly.

Therefore, in the configuration shown in FIG. 5, the arithmetic unit that requires a large amount of hardware is provided only in the scalar arithmetic unit 570, and when it is desired to perform that kind of arithmetic operation on data stored in the vector register, the data is once stored in the vector register. It is conceivable to read the data, store it in a scalar register, and execute it using scalar operations, but it takes extra time to transfer data between registers, and it also becomes difficult to execute using vector operation instructions, which slows down the processing speed, so this is not practical. I can't say it's on point.

The present invention solves these conventional problems, and its purpose is to quickly perform operations on data stored in vector registers using an arithmetic unit provided in a scalar arithmetic unit. The object of the present invention is to provide a practical arithmetic device which eliminates the need to provide an arithmetic unit with a large amount of hardware in each vector pipe.

[Means for solving problems]

In order to solve the above problems, an arithmetic device of the present invention includes a vector arithmetic section and a scalar arithmetic section each having a plurality of vector pipes, and a control section that controls both arithmetic sections, and each vector pipe in the vector arithmetic section has a plurality of vector pipes. includes a vector register for first and second operands that stores a plurality of element data, and an arithmetic unit that performs an operation on the element data output from the vector register, and the scalar operation unit includes In an arithmetic device including a scalar register, an arithmetic unit, and selection means for selecting inputs of the first and second scalar registers from outputs of the arithmetic unit, each vector pipe of the vector arithmetic unit is provided with an arithmetic operation in the own vector pipe. a selection means for selecting data to be input to the first and second operand vector registers in the own vector pipe from the output of the unit or the output of the arithmetic unit in the scalar arithmetic unit, and in the scalar arithmetic unit; , a selection means is provided for selecting data to be input to the arithmetic unit in the scalar arithmetic section from among the outputs of the first and second scalar registers or the outputs of the first and second operand vector registers in the plurality of vector pipes. .

[Effect]

When performing an operation on the data stored in the vector register using the arithmetic unit provided in the scalar operation unit, the element data stored in the vector register of the vector operation unit is The results are sequentially selected by the means and directly inputted to the arithmetic unit of the scalar arithmetic unit, and the obtained arithmetic results are selected by the selection means provided in the vector arithmetic unit and directly stored in the vector register.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, in which a vector calculation unit 100 includes four vector pipes P1 to P4.
．． One scalar operation unit 500. main memory 600
and a control unit 800.

Each of the vector pipes P1 to P4 of the vector calculation unit 100 has a vector register 130, 2 for the first operand.
30, 330, 430, vector registers 140, 240, 340, 440 for second operand, output of main memory 600, vector operation unit) 150,
Selection means 110° 210.310, 410 for selecting the input of the vector register 130.230.330.430 for the first operand from among the outputs of 250, 350° 450 or the outputs of the scalar arithmetic unit 570; vector register 140.240.
Selection means 120, 22 for selecting inputs of 340 and 440
0,320,420 and vector register 130°14
0, 230.240.330.340.440.430
A vector calculation unit 7) that performs calculations on the output data of
It consists of 150, 250, 350°450.

This vector operation unit 150, 250, 350.4
50 is provided with a plurality of types of arithmetic units, but in this embodiment, arithmetic units that require a large amount of hardware are not included.

The scalar operation unit 500 also includes a scalar register 530 for the first operand, a scalar register 540 for the second operand, and a scalar register for the first operand from the output of the main memory 600 or the output of the scalar operation unit 570. Selection means 510 for selecting the input of 530 and selection means 520 for selecting the input of scalar register 540 for the second operand and the output of scalar register 530 or vector register 130.2.
selection means 550 for selecting the input of the scalar arithmetic unit 570 from among the outputs of 30.330.430; and the output of the scalar register 540 or the vector register 14;
It is composed of a selection means 560 that selects the input of the scalar operation unit 570 from among the outputs of 0, 240, 340, and 440, and a scalar operation unit 570 that operates on the data selected by the selection means 550 and 560. This scalar arithmetic unit 570 is provided with a plurality of types of arithmetic units, but in this embodiment, a pipeline type arithmetic unit is used as the arithmetic unit that also performs operations on the output data of the vector register.

The control unit 800 generates various signals for controlling the vector calculation unit 100, the scalar calculation unit 500, and the main memory 600.The control unit 700 in FIG. 5 uses the calculation unit of the scalar calculation unit 500. A control function for performing vector calculations is added.

As described above, in this embodiment, the vector register 130,
140,230,240,330,340,430,4
40 can be directly input to the scalar calculation unit 570 by the selection means 550, 560, and the calculation results of the scalar calculation unit 570 can be input to the selection means 110, 120.
, 210, 220, 310, 320° 410.420 directly by vector registers 130, 140° 230.
240, 330, 340, 430, and 440, the vector operation instruction causes the arithmetic unit of the scalar operation unit 570 to perform an operation on the data stored in the vector register, and the result of the operation is used as the source. It becomes possible to perform operations such as storing data in a vector register.

2 and 3 are time charts when vector operations are performed on data stored in the vector register using the arithmetic unit provided in the scalar arithmetic unit 570. Please refer to each figure below. An example of how the arithmetic unit of this embodiment is used will now be described. It is assumed here that the vector operation taken as an example has eight elements, and the operation result is written into the vector register for the first operand. Also, the first operands (1
0).

(14) and the second operands (20) and (24) are stored, and similarly the first operands (11) and (15) of elements l and 5 and the second operands (21) and ( 25), vector register 3
30.340 has the first operand (12) of elements 2 and 6,
(16) and the second operand (22).

(26), the first operands (13), (17) and the second operands (23), (27) of elements 3 and 7 are stored in vector registers 430 and 440.

When a vector operation instruction arrives, the control unit 800 takes out element 0 from the vector registers 130 and 140, causes the selection means 550 and 560 to select the data of this element 0, and causes the scalar operation unit 570 to perform an operation.

Note that the arithmetic unit to be used is designated by a signal separately given from the control unit 800. Next, the control unit 800 controls this element O.
The selection means 110 selects the result and stores it in the vector register 130.

Assuming that the arithmetic units used in the scalar arithmetic unit 570 have a pipeline configuration, the control unit 800 selects the vector registers 230 and 240 at the next timing after the selection means 550 and 560 select the data of element 0.
The data of element 1 is extracted from the selection means 550, 56.
0, and the vector register 33 is selected at the next timing.
The data of element 2 is extracted from 0,340 and the selection means 5
50,560, and at the next timing, the data of element 3 is taken out from the vector register 430.440 and selected by the selection means 550.560, and at the next timing, the data of element 4 is taken out from the vector register 130.140. The selection means 550 and 560 are used to select, and the extraction and selection of data up to element 7 is sequentially controlled.

The data selected by the selection means 550, 560 are
The controller 800 performs pipeline processing and outputs one after another by the arithmetic units in the scalar arithmetic unit 570.
The calculation results of elements O and 4 are stored in the vector register 130 through the selection means 110, the calculation results of elements 1 and 5 are stored in the vector register 230 through the selection means 210, and the calculation results of elements 2 and 4 are stored in the vector register 230 through the selection means 210.
The calculation results of elements 3 and 6 are sent to the vector register 330 through the selection means 310, and the calculation results of elements 3 and 7 are sent to the selection means 410.
They are respectively stored in the vector register 430 through them.

It goes without saying that the calculation results can also be stored in the second operand vector registers 140, 240, 340, and 440 depending on how the instructions are given.

In this arithmetic device, vector arithmetic units 150, 250, 3
Vector calculations using the arithmetic unit located at 50° 450 can be performed in the same manner as before, and in the case of scalar calculations, the output data of the scalar registers 530 and 540 is selected by the selection means 550 and 560, and the scalar calculation unit 570 performs the calculation. The control unit 80 stores the operation result in the scalar register 530 through the selection means 510 or in the scalar register 540 through the selection means 520.
Controlled by 0.

FIG. 4 is a block diagram of main parts of an embodiment of the control unit 800, which includes an instruction control unit 801, a vector calculation control unit 802,
A scalar calculation control unit 803 is included.

In the figure, an instruction control unit 801 decodes a given arithmetic instruction and determines whether it is a vector arithmetic instruction using only the vector arithmetic unit 100 in FIG.
In the case of a vector calculation instruction using the scalar calculation unit 500, control is given to the decoding unit 811 along with necessary information, and in the case of a scalar calculation instruction using only the scalar calculation unit 500, control is passed to the scalar calculation control unit 803 along with the necessary information. The control of the scalar calculation control unit 803 is the same as the conventional one, and the selection control signals of the selection means 510, 520, 550, and 560 in FIG. Selector 8 specifies the arithmetic unit to be used and the start and end signals of the calculation.
04 to the scalar calculation unit 500.

The decoding unit 811 converts the received information into the vector calculation unit 100.
If it is a vector operation instruction that uses only the vector length, the vector length is stored in the vector length register 811, the arithmetic unit control section 806 and the timing control section 807 are activated, and the selector 810 is switched to the timing control section 807 side.

As a result, the calculation control unit 806 controls the vector calculation unit 100.
The timing control unit 807 starts controlling the selection means, vector register, etc. in the vector calculation unit 100, and performs the same control as in the past using only the vector calculation unit 100. be done.

On the other hand, when the received information is a vector operation instruction using the arithmetic unit of the scalar arithmetic unit 500, the decoding unit 811 stores the vector length in the vector length register 805, and then sends the timing information to the arithmetic unit control unit 809. Activate the control section 808 and set the selector 810 to the timing control section 8.
Switch to 08 side. As a result, the calculation control unit 809 issues a notification to the scalar calculation control unit 803 not to use the calculation unit used for vector calculation, and the selector 804 is switched to the vector calculation control unit 802 side, and the calculation control unit From 809 via selector 804, designation of the arithmetic unit used in arithmetic unit 570, and control signals for starting and ending arithmetic operations are sent out via selector 804, and vector operation is sent from timing control unit 808 via selector 810. A selection signal for the vector register write/read control signal 1 selection means is sent to the section 100, and a selection signal for the selection means of the scalar operation section 500 is sent via the selector 804.

〔Effect of the invention〕

As explained above, according to the present invention, the selection means selects the input of the arithmetic unit of the scalar arithmetic unit from the output of the scalar register or the output of the vector register of the scalar arithmetic unit, and the output of the vector arithmetic unit or the scalar and a selection means for selecting the input of the vector register from among the outputs of the arithmetic unit, so that the output of the vector register can be input directly to the scalar arithmetic unit, and the output of the scalar arithmetic unit can be input directly to the vector register. Therefore, the effect is that it is possible to quickly perform operations such as using the arithmetic unit provided in the scalar operation unit to perform operations on data stored in the vector register and returning the result to the vector register. be. Therefore, even if the configuration is such that the scalar arithmetic unit is provided in each vector pipe of the vector arithmetic section, instead of having an individual arithmetic unit that requires a large amount of hardware, a sufficiently practical arithmetic speed can be obtained. , there is an advantage that an arithmetic device with a small amount of hardware can be realized. In particular, as shown in the embodiment, if at least the arithmetic unit used for vector register operations among the arithmetic units of the scalar arithmetic unit has a pipelined arithmetic unit configuration, more sufficient performance can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are time charts used to explain an example of the operation of the arithmetic unit shown in FIG. The block diagram of the embodiment and FIG. 5 are diagrams of a conventional arithmetic unit. In the figure, 100 is a vector calculation unit, 110.120
゜210.220,310,320,410,420,
510, 520, 550, 560 are selection means; 130.
140.230.240.330.340.430.4
40 is a vector register, 150, 250, 550, 5
60 is a vector operation unit, 500 is a scalar operation unit, 530, 540 are scalar registers, 570 is a scalar operation unit, 600 is a main memory, 700, 8
00 is a control unit. Output of 130 1o14 Output of 1J40 n Figure 1 Operation explanatory diagram Figure 2 Output of 570 01 234567 Operation explanatory diagram Figure 1 Procedure amendment document (voluntary) 61.9.10

Claims (1)

[Scope of Claims] The invention includes a vector calculation unit and a scalar calculation unit each having a plurality of vector pipes, and a control unit that controls both calculation units, and each vector pipe in the vector calculation unit stores a plurality of element data. The scalar operation section includes a vector register for first and second operands and an arithmetic unit that performs an operation on element data output from the vector register, and the scalar operation section includes the first and second scalar registers, an arithmetic unit, and the arithmetic unit. an arithmetic device that selects inputs of the first and second scalar registers from outputs of the vector arithmetic unit, wherein each vector pipe of the vector arithmetic unit is provided with an output of an arithmetic unit in its own vector pipe or an input of the scalar arithmetic unit in the scalar arithmetic unit. a selection means for selecting data to be input to the first and second operand vector registers in the own vector pipe from among the outputs of the arithmetic unit; An arithmetic device comprising a selection means for selecting data to be input to an arithmetic unit in the scalar arithmetic unit from among the outputs of the vector registers for first and second operands in the plurality of vector pipes.