JP2741717B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a vector processing apparatus that enables a vector data load instruction and a scalar data load instruction to overlap in a vector data processing apparatus. A vector processing device for storing a vector load data in a vector register of a vector processing unit via a scalar processing unit for the purpose of improving processing speed, comprising: at least two adders for operand address operation; While the scalar processing unit performs the vector load using the one adder, the address calculation of the subsequent scalar instruction is calculated by the other adder, and during the interlock due to the interruption of the vector load, Issues the address of the subsequent scalar instruction from the adder A control unit for, configured to include a.

[Industrial applications]

The present invention relates to a vector processing apparatus that enables a vector data load instruction and a scalar data load instruction to be overlapped by a vector data processing apparatus.

The vector data processing device processes not only vector instructions but also scalar instructions to improve processing speed. The above-described overlapping processing can be realized by a conventional technique in an apparatus in which the vector processing unit and the scalar processing unit can operate independently of each other, but cannot be realized in an apparatus in which vector load / store is performed via the scalar processing unit. In this case, the scalar instruction and the vector instruction need to be overlapped in this vector processing device. The present invention is related to this field.

[Conventional technology]

Conventionally, in an apparatus that performs a vector load / store through a scalar processing unit, a subsequent scalar load instruction is executed after the vector load / store is completed.

[Problems to be solved by the invention]

As described above, in the conventional addition-type vector processing device, the scalar load instruction or the RX type (the operation of the register and the word specified by the address in the main storage that is index-modified) or the RS type (the operation of the register and the main storage) 2) The scalar instruction and the vector load / store instruction cannot be processed redundantly, and there is a problem in processing speed.

SUMMARY OF THE INVENTION It is an object of the present invention to enable overlapping processing of a vector data load instruction and a scalar data load instruction, thereby improving the processing speed of a vector processing device.

[Means for solving the problem]

The present invention is a vector processing device that stores vector load data in a vector register of a vector processing unit via a scalar processing unit, as described with reference to the block circuit diagram illustrated in FIG. At least two adders for operand address arithmetic;
The scalar processing unit causes the other adder to calculate the address of a subsequent scalar instruction while executing the vector load using the one adder, and also performs the other addition during the interlock due to the interruption of the vector load. And a control unit for causing the device to issue the address of the subsequent scalar instruction.

(Operation)

When the above-described device is used, the operand address of the succeeding scalar instruction can be obtained by the other of the adders performing the two operand address operations, and the scalar instruction can be executed. If this scalar instruction can be executed, the next vector operation instruction can be overlapped.

〔Example〕

FIG. 1 is a partial block circuit diagram of a vector processing apparatus according to an embodiment of the present invention.

Instruction processing in the processing device is performed in the order of decode (D), address calculation (A), operation (E), interrupt check (C), and register write (W) in the order of D, A, E,
It is executed according to the five states (start) of C and W. First, a vector load instruction, for example, from an instruction buffer 1 in which instruction data is stored is input to an operand address adder 6 via a D-state instruction buffer (DB) 2 and an A-state instruction buffer (AB) 3 and the instruction decoder 8 And at the same time instructs the activation of the normal sequence instruction. Instruction pipeline control unit 10 (control unit)
Receives the SCU (storage control unit) interlock signal, the interrupt operation enable signal, the move in end signal, and the signals from the instruction decoders 8 and 9, and controls the adders 6, 7 and the address multiplexer 11. When the vector is loaded, the adder 6 is operated, and the output of the adder 6 is supplied to the address bus multiplexer 11.
Is controlled to be selected by. In this way, the operand address is calculated at the time of vector loading, and the vector loading process, that is, data transfer from the buffer storage device of the scalar processing unit to the vector register of the vector processing unit is executed.

During a vector load, if a buffer miss occurs, that is, if data supplied to the buffer storage unit of the scalar processing unit is not transferred, an SCU interlock signal is output and the vector The scalar instruction following the load is the preceding D-state instruction buffer (PDB) 4 and the preceding A-state instruction buffer (PAB)
5, the instruction is supplied to the operand address adder 7 and the instruction decoder 9, and simultaneously instructs the start of the preceding sequence instruction. In this case, the instruction pipeline control unit 10 operates the adder 7 and controls the address bus multiplexer 11 to select the output of the adder 7. In this way,
When the vector load, which is a normal sequence instruction, is interrupted, a scalar load instruction to be executed after the vector load is completed is started via the preceding instruction buffer, the operand address is calculated by the adder 7, and the scalar load processing is performed. Be executed. Further, the vector operation instruction following the scalar load can be continuously executed. The move-in-end signal is a signal supplied to determine acceptance or non-acceptance of an interrupt operation during SCU interlock. The two adders for the operand address operation are an instruction address adder (not shown)
Can also be used depending on the circuit configuration.

FIG. 2 is a diagram for explaining the flow of instruction processing in the embodiment of the present invention, and FIG. 3 shows a similar diagram of instruction processing using a conventional method for comparison.

In FIG. 2, as an example, a vector load (VL
D) The instruction is processed as shown in each element e1 to e12.
Here, when a buffer error occurs during processing of element e5, SC
Assuming that the U interlock is output, if an interrupt is possible, an interrupt is performed, a scalar load (LD) instruction is activated in advance, and processing of the LD instruction is completed (indicated by a block). Then, the following vector operation (VAD)
Instructions (elements 1 to 12) are also pre-activated and executed. In this way, the VLD, LD, and VAD instructions are processed redundantly.

In the conventional method shown in FIG. 3, even if an SCU interlock occurs, the LD instruction cannot be processed until the VLD instruction is completed.
Sequential processing is performed in the order of LD, LD, and VAD instructions.

〔The invention's effect〕

According to the present invention, overlapping processing of a vector load instruction and a scalar data load instruction is enabled, and the processing speed of the vector processing device can be improved.

[Brief description of the drawings]

FIG. 1 is a partial block circuit diagram of a processing device for carrying out an embodiment of the present invention, FIG. 2 is a diagram for explaining the flow of instruction processing of the embodiment, and FIG. 3 is the same as FIG. FIG. In the figure, 1... Instruction buffer, 2... D-state instruction buffer, 3... A-state instruction buffer, 4... Preceding D-state instruction buffer, 5... Preceding A-state instruction buffer, 6, 7. Adder, 8, 9 ... instruction decoder, 10 ... instruction pipeline control unit, 11 ... address bus multiplexer.

Claims (1)

(57) [Claims] 1. A vector processing device for storing vector load data in a vector register of a vector processing unit via a scalar processing unit, comprising: at least two adders for an operand address operation; The unit causes the other adder to calculate the address of a subsequent scalar instruction while the vector load is being executed using the one adder. A control unit for issuing an address of a subsequent scalar instruction.