JPH01224870A - Main memory access instruction execution control system for information processor - Google Patents

Abstract

PURPOSE:To make a processing faster by canceling the queuing of a succeeding main memory access instruction without waiting for the completion of a preceding effective address storing instruction and starting the effective control of the main memory access instruction from a stage in which a value stored in an output register is sent to a main memory control part when the executing sequence of the instruction is detected with a detecting part. CONSTITUTION:By outputting a detecting signal from a detecting part 7, the queuing condition is forcibly canceled, and the execution control is started from the stage in which a value stored in the output register, that is, the effective address obtained by the effective address storing instruction is sent to a main memory control part 2. As this result, the title system can make the main memory access processing faster than a system in which the execution control of the succeeding main memory access instruction is started from the stage in which the contents of a scalar register 4 are taken out through an effective address adder 9 to the output register, after the updating of the scalar register 4 due to the effective address storing instruction.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a main memory access instruction execution control method in an information processing device, and in particular, calculates an effective address on the main memory with a preceding instruction, and uses the obtained effective address. [Prior art] In an information processing device such as a vector processing device that handles vector data, an address on the main memory is An operation is performed in which the address is determined by a preceding instruction and the subsequent instruction uses that address to access the main memory. For example, this is the case with a vector load in which vector data in main memory is loaded into a vector register using the following two instructions.

LEA SIO←SO+S1+100...(
1) VLD VRO←M (310,320) ・
f21 Here, the instruction (1) is an effective address storage instruction (hereinafter referred to as "effective address storage instruction") that adds the contents of the pace register SO, the contents of the index register S1, and the displacement 100 described in the specific field of the instruction, and stores the result in the pace register S10. (referred to as the LEA instruction), instruction (2) uses the contents of the pace register 310 determined by the LEA instruction (1) as the base address, which is the storage start address on the main memory, and uses the contents of the scalar register 320 as the base address between the elements of vector data. The target vector data is stored as a distance from the main memory in the vector register V.
This is a vector load instruction (hereinafter referred to as a VLD instruction) to load into the RO.

Execution control of such instruction sequences (11, (21) has conventionally been performed in a similar manner.

First, by executing the LEA instruction (1), the contents of the pace register SO in the scalar register group, the contents of the index register S1, and the displacement 100 specified by the LEA instruction (1, 1) are added to the effective address adder. performs an addition operation, and stores the result in the pace register SIO in the scalar register group.

On the other hand, after the activation of LEA instruction (1), the next VLD instruction (2) is immediately decoded, but since VLD instruction (2) is an instruction that uses the result of the preceding instruction (11),
Activation of the LD instruction (2) is deferred. Then, when the base address is stored in the pace register S10, V
LD instruction (2) is activated, first the pace register SIO
The contents of S1 are sent to the main memory control unit, the first element of the vector data is read out, and thereafter the pace register S1
The effective address of each element obtained by sequentially adding the inter-element distance of the scalar register S20 to the contents of 0 by the address effective adder is sent to the main memory storage section.

[Problem that the invention seeks to solve]

As described above, in the past, the next VLD instruction (2) had to wait until the execution result of the LEA instruction (11) was stored in the pace register 310, so vector loading could not be performed at high speed.

In addition, when the result of the preceding instruction is used by the subsequent instruction, so-called bypass control is adopted in which the result of the preceding instruction is stored in the scalar register group, and at the same time the scalar register group is bypassed for use in the subsequent instruction, thereby speeding up vector loading. Efforts have been made to achieve this, but a satisfactory speed has not yet been achieved.

An object of the present invention is to execute an instruction in which the effective address on the main memory is determined by the preceding instruction and the subsequent instruction accesses the main memory using the obtained effective address, such as when executing an instruction such as a vector load. The purpose is to make the process happen at high speed.

[Means for solving problems]

In order to achieve the above object, the present invention includes a main memory that stores instructions and data, a main memory control unit that controls access to the main memory, a scalar register group, and a scalar register in the scalar register group. an effective address adder that receives the contents and a value indicated in a specific field in the instruction; an output register that holds the output of the effective address adder; and supplies the contents of the output register to the main memory control section. In an information processing device including a main memory send line and a write line that supplies the contents of the output register to the scalar register group, a preceding instruction calculates an effective address using the effective address adder, and This is an effective address storage instruction that stores an address in a scalar register in the scalar register group specified by the instruction, and the subsequent instruction sends the effective address to be stored in the scalar register to the main memory control unit and stores the effective address in the scalar register group. It has a detection unit that detects that it is a main memory access instruction that accesses memory, and in response to a detection signal from the detection unit, the main memory access instruction is placed in a scalar register update wait state by the effective address storage instruction. and the execution control of the main memory access instruction is started from the step of sending the value stored in the output register to the main memory control unit. Main memory access instruction execution control method in devices.

(Operation) When an instruction appears in the order of an effective address storage instruction and a main memory access instruction that uses the effective address stored in a scalar register by this effective address storage instruction, this fact is detected by the detection unit. In the execution control of the effective address storage instruction, the scalar data read from the scalar register group and the value specified in the specific field of the effective address storage instruction are added by the effective address adder and held once in the output register. The data is stored in the scalar register specified by the instruction in the scalar register group via the write line from the register.On the other hand, the subsequent main memory access instruction waits for the scalar register to be updated by the preceding effective address storage instruction. When a detection signal is issued from the detection section, the wait state is forcibly canceled, and the value stored in the output register, that is, the effective address obtained by the preceding effective address storage instruction, is sent to the main memory control section. Execution control is started from the step of .As a result, execution control of the subsequent main memory access instruction is started after the scalar register is updated by the effective address storage instruction.
Compared to the conventional method, which starts from the step of fetching the contents of a scalar register to an output register via an effective address adder, main memory access processing can be sped up.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of an information processing apparatus to which the present invention is applied.

In the figure, a main memory 1 is a storage section that stores data necessary for instructions and operations, or operation results.

The main memory 1iIJ control unit 2 is connected to the main memory 1, and the control unit 8
Alternatively, it performs control when reading instructions and data from the main memory 1 or storing data in the main memory 1 according to an address given from the register 12.

The vector register group 3 is a register group that stores data necessary for vector calculations and intermediate results of the calculations, and is connected to the main memory control unit 2 and a vector calculation unit (not shown).

Instructions fetched from the main memory 1 are stored in the instruction register 5 via the main memory control unit 2.

Originally, it is common to provide an instruction cache or an instruction buffer between the instruction register 5 and the main memory 1 to absorb the access gear to the main memory 1, but in this embodiment, the explanation is simplified. It is omitted for this reason. The instruction decoder 6 decodes the instructions held in the instruction register 5 and sends the decoding results to the detection section 7 and the control section 8.

Based on the decoding result from the instruction decoder 6, the detection unit 7
The preceding instruction is an instruction to obtain an effective address and store it in a scalar register, and the following instruction is an instruction that uses the effective address stored in that scalar register. When a sequence is detected, the controller 8 is notified of this fact. For example, as shown in FIG.
The contents of the second stage register RG2 are stored, and the contents of the first stage register RG1 are stored as LEA.
Instruction (This is an instruction to find an effective address and store it in a scalar register as shown in 11, and the content of the second stage register RG2 is an instruction that uses the effective address found in the preceding instruction as in VLD instruction (2). In this case, the decoder DCD outputs a detection signal.

The control unit 8 includes a scalar register group 4. Effective address adder9. It manages various resources such as various registers and paths (lines), and activates instructions and controls each functional unit according to the status of each resource and information from the instruction decoder 6 and detection unit 7.

The scalar register group 4 is a register group that stores data necessary for scalar operations and intermediate results of operations, and includes vector registers SO, index registers 31, etc. necessary for address calculation. In this case, the contents of two scalar registers in the scalar register group 4 can be read simultaneously, the contents of one being stored in the register Ila via the selector 20a, and the contents of the other being stored in the register Ila via the selector 20b. and stored in register llb. The scalar register group 4 has a bypass line 2 that bypasses it.
1, and whether to select the bypass line 21 or the output of the scalar register group 4 is determined by selectors 20a and 20b operated by a control signal (not shown) from the control section 8. Registers 14a, 14b, and 14c are a group of registers that sequentially transmit the value of a specific field of the instruction held in instruction register 5, and the output of the final register 14c is applied to gate 16. Also, registers 11a, ll
The output of b is applied to gate 17.18, which gate 1
7.18 and the gate 16 are opened and closed according to control signals from the control section 8, and each output is input to the effective address adder 9.

The effective address adder 9 is activated by the control section 8 to perform an operation of adding the respective outputs of the gates 16, 17, and 18. The control unit 8 controls the opening/closing states of the gates 16, 17, and 18 so that the effective address adder 9 can add the contents of two scalar registers or add three values including the value of the instruction field. It is also possible to output the contents of one scalar register as the addition result.

The register 12 is a register that holds the output of the effective address adder 9, and the output is transmitted to the main memory control unit 2 via the main memory sending line 22 and is also supplied to the register 13. Register 13 is a relay register that sends the contents of register 12 to write line 23 . The register 13 may be omitted and the output of the register 12 may be output to the write line 23 as well.

The contents of the register 12 sent to the write line 23 are applied to a selector 19 which also inputs other data (not shown), and the data selected here is stored in the write register 10. The output of the write register 10 is transmitted to the scalar register group 4 and also transmitted via the bypass line 21 to the selectors 20a and 20b.

The aforementioned control section 8 includes an execution start control section 30 and an executing command management section 31, as shown in FIG.

The instruction is decoded by the instruction decoder 6 shown in FIG. 1 and sent to the execution start control section 30. The execution start control unit 30 determines whether or not the data necessary for executing the decoded instruction is prepared based on the management information etc. in the executing instruction management unit 31, and determines whether the data etc. necessary for executing the decoded instruction are prepared. It outputs a start signal to start the instruction, and also sends management information (for example, execution time, execution result storage register number, etc.) necessary for storing the execution result of the instruction to the executing instruction management section 31. The executing instruction management unit 31 manages the execution state of the instruction according to the management information passed from the execution start control unit 30, and stores the information or control signal necessary for storing the execution result of the executed instruction as a scalar shown in FIG. It is sent to each component such as register group 4.

On the other hand, for an instruction that cannot be activated due to factors such as data necessary for execution not being prepared while waiting for the execution result of a preceding instruction, the execution activation control unit 30 puts the execution of the instruction in a waiting state. And by eliminating that waiting factor,
The command is activated. At this time, conventionally, the waiting state was canceled based only on the execution state of the preceding instruction managed by the executing instruction management section 31, but in this embodiment, the execution start control section 30 uses the detection shown in FIG. In addition to the output of the section 7, the detection result of the detection section 7 is also used to determine whether to release the waiting state.

Next, the operation of this embodiment will be described using as an example the following instruction sequence used in the description of the prior art.

LEA SIO←SO+S1+100...(1
)VLD VRO←M (510,520) −+
21 First, the LEA instruction fi fetched from main memory 1
When + is stored in the instruction register 5, it is decoded by the instruction decoder 6, the decoding information is transmitted to the detection unit 7 and the control unit 8, and the value 100 of the specific field of the LEA instruction (1) is sent to the register 14a. . At this time, the detection unit 7 detects that the preceding instruction is the LEA instruction (1) using the register RG.
Store it in I.

The execution activation control unit 30 of the control unit 8 activates the LEA instruction (11) in response to the decoding information from the instruction decoder 6, and the executing instruction management unit 31 manages its execution state. Instruction execution control is performed as follows.First,
The contents of the base register SO and the contents of the index register S1 in the scalar register group 4 are determined by the selectors 20a and 20.
The timing-adjusted LEA instruction < The value 100 of the specific field of I+ is added to the effective address adder 9, and an addition operation is performed in the effective address adder 9. Then, at the timing when the output of the effective address adder 9 becomes valid, the addition result (this is the base address used in the subsequent VLD instruction (2)) is stored in the register 12, and at the next timing, it is stored in the register 13. Then, at the next timing, it is transferred to the register 10 via the write line 23 and stored in the pace register SIO designated by the LEA instruction 11) of the scalar register group 4.

On the other hand, following the decoding of the LEA instruction (1), the VLD instruction (2) stored next in the instruction register 5 is decoded by the instruction decoder 6.
The decoding information is sent to the detection unit 7 and the control unit 8.
transmitted to. At this time, the detection unit 7 receives the VLD command (2).
The decoding information of is stored in register RGI, and register RGI
The decoding information of the LEA instruction fi+ stored in is transferred to the register RG2. The execution start control unit 30 of the control unit 8 is
After starting the LEA instruction +11, its subsequent instruction VLD
It is determined whether or not instruction (2) can be started. However, since VLD instruction (2) is an instruction that uses the execution result of LEA instruction tl+, and the execution of LEA instruction +11 has not yet been completed, that VLD Wait for execution of instruction (2). However, at this time, the decoder DCD of the detection unit 7 detects that the VLD instruction (2) appears in the instruction sequence following the LEA instruction (11), and adds a detection signal to the execution start M control unit 3o. The control unit 30 controls the preceding LEA
Forcibly release the wait state of VLD instruction (2) without waiting for the completion of execution of instruction (11), and execute VLD instruction (2).
The base address obtained by executing the LEA instruction (11) is still held in the L0 register 12 starting from the step of sending the value of the register 12 to the main memory control unit 2. By executing the VLD instruction (2) from the stage of sending it to the storage control unit 2, it becomes possible to execute main memory access using the correct base address at high speed.
One reason for starting the execution of the D instruction (2) from the stage of sending the contents of the register 12 to the main memory control unit 2 is to shorten the time, but another reason is that if the VLD
Starting from the first step of instruction (2), that is, the step of transferring the contents of pace register SIO in scalar register group 4 to register 12 via effective address adder 9,
The old contents of the pace register 310 are transferred to the register 12 when the base address obtained by the preceding LEA instruction (1) is not yet stored in the pace register S10, and the correct base address held by the register 12 is lost. This is to prevent this from happening, as it would lead to destruction.

Figures 4 and 5 show the LEA instruction (1) and the VLD instruction (
FIG. 4 shows the timing chart when executing the instruction sequence of 2), and FIG. 5 shows the case according to the present embodiment, and FIG. 5 shows the case according to the conventional example. As shown in FIG. 4, in the case of this embodiment, in the timing cycle TI immediately after the LEA instruction +11 is activated,
The contents of pace register so and index register 31 are register 11a.

11b, the addition of SO+31+100 is performed in the effective address adder 9 in the next timing cycle T2, and the addition result of the effective address adder 9 is stored in the register 12 in the next timing cycle T3. As mentioned above, the execution of the subsequent VLD instruction (2) starts from the stage of sending the value of the register 12 to the main memory control unit 2, so as early as the next timing cycle T4, the VLD instruction (2) is executed.
The pace address is sent to the main memory control unit 2 by executing the LD instruction (2). Note that the base address stored in the register 12 is set in the register 13 in timing cycle T4 by executing the LEA instruction (1) that is executed in parallel with the VLD instruction (2), and is set in the register 13 in the next timing cycle T5. and stored in the base register SIO in the next timing cycle T6.

On the other hand, in the conventional method, as shown in FIG.
By executing the A instruction +11, the base address set in register 12 in timing cycle T3 is transferred to register 13 in the next timing cycle T4, transferred to register 10 in the next timing cycle T5, and transferred in the next timing cycle T6. While storing it in the pace register 310, the base address in the output register is stored in the register lla via the bypass line 21 under the execution control of the VLD instruction (2), and the effective address adder 9 is activated in the next timing cycle T7. is passed to register 12 in the next timing cycle T8, and this register 1
The base address retrieved in step 2 is sent to the main memory control unit 2, and it takes 8T timing cycles to start sending out the base address.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various other additions and changes are possible. For example, the present invention is applicable to cases where a preceding effective address store instruction determines a base address to be used by a subsequent vector store instruction.

〔Effect of the invention〕

As explained above, in the present invention, when the effective address store instruction and the jf7 access instruction that uses the effective address calculated by the effective address store instruction and stored in the scalar register are executed in this order, the subsequent main This method takes advantage of the fact that the correct effective address has already been set in the output register (register 12 in the embodiment) in which the effective address is to be set in the execution control process of the memory access instruction in the execution control process of the preceding effective address storage instruction. , ★When the execution order of such instructions is detected in the output section, the waiting state of the subsequent main memory access instruction is released without waiting for the completion of the preceding effective address storage instruction, and the instruction is stored in the output register. Since the effective control of the main memory access command is started from the stage of sending the value obtained to the main memory control section, there is an effect that main memory access processing such as vector loading can be speeded up.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an information processing device to which the present invention is applied, FIG. 2 is a block diagram showing an example of the configuration of the detection section 7, and FIG. 3 is a block diagram of main parts showing an example of the configuration of the control section 8. , Figure 4 shows the LEA command +11. FIG. 5 is a time chart of the embodiment of the present invention when executing the VLD instruction (2), and FIG. 5 is a time chart of the conventional method when executing the LEA instruction (11, VLD instruction (2). In the figure, 1... Main memory 2 Main memory control unit 3 Hector register group 4 Scalar register group 5 Instruction register 6 Instruction decoder 7 Detection unit 8 Control unit 9・・Effective address adder 10, lla, llb, 12.13.14a to 14c・
・Register 22 ・Main memory output line 23 ・Comment line Patent applicant: 1 person other than NEC Corporation

Claims (1)

[Claims] A main memory that stores instructions and data, a main memory control unit that controls access to the main memory, a scalar register group, the contents of the scalar registers in the scalar register group, and the contents of the instructions. an effective address adder that inputs a value indicated in a specific field; an output register that holds the output of the effective address adder; and a main memory sending line that supplies the contents of the output register to the main memory control unit. , and a write line that supplies the contents of the output register to the scalar register group, wherein a preceding instruction determines an effective address using the effective address adder, and specifies the determined effective address in the instruction. This is an effective address storage instruction to store in a scalar register in the scalar register group, and a subsequent instruction sends the effective address to be stored in the scalar register to the main memory control unit to access the main memory. The main memory access instruction includes a detection unit that detects that the instruction is a main memory access instruction, and in response to a detection signal from the detection unit, the main memory access instruction is forcibly released from a scalar register update wait state due to the effective address storage instruction. Main memory access in an information processing device, characterized in that execution control of the main memory access instruction is started from a step of sending a value stored in the output register to the main memory control unit. Instruction execution control method.