JP3461887B2 - Variable length pipeline controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit in a computer system, and more particularly to a microprocessor equipped with a pipeline controller.

[0002]

2. Description of the Related Art In recent years,
Many processors and the like that operate based on the RISC (Limited Instruction Set Computer) system have a pipeline architecture. In such a pipeline processor, each of an instruction fetch module, an instruction decode module, an instruction execution module, a memory access module, and a write back module constitutes a pipeline. Then, in one instruction cycle, each module can execute processing for different instructions in parallel.

FIG. 13 shows an example of the configuration of part of a pipeline control device in such a pipeline processor. This configuration relates to the program counter pipeline (PC pipe) of the pipeline control device.

Adder 1301 (hereinafter PC_adder
Called 1301), the program counter value that is sequentially incremented from a predetermined initial value is AND gate 1
In synchronization with a clock CLK input via 307 to 1310, an instruction fetch stage program counter value holding unit 1302 (hereinafter, referred to as PC_IF1302), an instruction decode stage program counter value holding unit 1303.
(Hereinafter, referred to as PC_ID 1303), instruction execution stage program counter value holding unit 1304 (hereinafter, PC_ID 1303)
EX1304), memory access stage program counter value holding unit 1305 (hereinafter PC_MA13)
05)) and the write-back stage program counter value holding unit 1306 (hereinafter referred to as PC_WB 1306). Note that PC_IF1302
The program counter value output from PC_add
The program counter value is sequentially incremented by being input to r1301.

As a result, the instruction fetch module, the instruction decode module, the instruction execution module, the memory access module, and the write back module, which are not shown, are held in the program counter value holding units 1302-1306. The processing related to the instruction corresponding to the program counter value is executed.

Here, the instruction fetch module fetches an instruction from the memory. The instruction decode module decodes the fetched instruction. The instruction execution module executes the decoded instruction. The memory access module reads the operand data from the memory or writes the operand data in the memory. The write-back module writes the operand data obtained from the memory by the above-mentioned memory access or the operand data processed by the execution module into the register inside the processor chip.

The OR gates 1311 to 1313,
Wait signals if_wait, id_wait, ex_
The wait and ma_wait will be described later.
The program counter pipeline as described above
It is necessary to hold the program counter value in each module when exception processing occurs in each module.

In addition to the program counter pipeline shown in FIG. 13, the pipeline control device is provided with an operand pipeline for transmitting an instruction operand to each module.

FIG. 14 is an explanatory diagram of pipeline processing. For each instruction cycle, each execution stage corresponding to the instructions A to D includes an instruction fetch module (not shown),
The parallel execution in the instruction decode module, instruction execution module, memory access module, and write back module is shown.

In instruction cycle 1, an instruction fetch stage for instruction A (hereinafter referred to as an IF stage)
Is executed in an instruction fetch module (not shown).

In instruction cycle 2, an instruction decode stage for instruction A (hereinafter referred to as an ID stage)
Is executed in an instruction decode module (not shown), and the IF stage for the instruction B following the instruction A is executed in the instruction fetch module.

In the instruction cycle 3, the instruction execution stage for the instruction A (hereinafter referred to as the EX stage) is
In particular, the instruction execution module (not shown) executes the ID stage for the instruction B in the instruction decode module, and the IF stage for the instruction C following the instruction B is executed in the instruction fetch module.

In the instruction cycle 4, the memory access stage for the instruction A (hereinafter referred to as the MA stage) is executed in the memory access module (not shown), and the EX stage for the instruction B is executed in the instruction execution module. And the ID stage for instruction C is executed in the instruction decode module, and the IF stage for instruction D following instruction C is
It is executed in the instruction fetch module.

In the instruction cycle 5, the write back stage for the instruction A (hereinafter referred to as the WB stage).
Is executed in a write back module (not shown), the MA stage for the instruction B is executed in the memory access module, the EX stage for the instruction C is executed in the instruction execution module, and the ID stage for the instruction D is executed. It is executed in the decoding module and, though not specifically shown,
The IF stage for the instruction E following the instruction D is executed in the instruction fetch module.

In the pipeline processing described above, the IF
When the stage and the MA stage are executed, a data read operation or a data write operation is performed on the memory. Some memories are built into the processor chip and some are connected to the outside of the processor chip. Hereinafter, the former will be called an internal memory and the latter will be called an external memory.

Since it is generally difficult to access the external memory at a time interval of a pipeline pitch (= 1 instruction cycle), a memory wait occurs.

FIG. 15 is an explanatory diagram of pipeline processing when a memory wait occurs. Since the operation when the memory wait occurs in the IF stage and the operation when the memory wait occurs in the MA stage are almost the same, in FIG. 15, the memory wait occurs only in the MA stage for simplification of description. The case is shown. In FIG. 15, IFw, IDw, EXw, and M
Aw is IF stage, ID stage, EX stage,
It shows that a memory wait is occurring at the time of executing each of the MA stage and the MA stage.

When a memory wait occurs in the MA stage for the instruction A, the MA stage originally ending in the instruction cycle 4 is repeated in the instruction cycle 5 due to the occurrence of the memory wait.
In addition, since the execution of the MA stage for the instruction A is not completed in the instruction cycle 5, for each of the subsequent instruction streams, that is, the instructions B, C, and D, the EX stage executed in the instruction cycle 4, the ID stage, and The IF stage is repeated in instruction cycle 5 as well.
This operation is realized as follows in the configuration shown in FIG. First, the weight signal ma_wai
By asserting t at the timing shown in FIG. 15A, the AND gate 1310 is turned off, and the AND gates 1309, 1308, and 1307 are turned off via the OR gates 1313, 1312, and 1311. As a result, in the instruction cycle 5, since the clock CLK is not input, PC_MA1
The state of instruction cycle 4 is maintained in each of 305, PC_EX 1304, PC_ID 1303, and PC_IF 1302.

As described above, a wait time having a time length of one instruction cycle is generated in the entire pipeline, and the processing currently being executed is delayed by that time. That is, as can be understood by comparing FIG. 14 and FIG. 15, for example, the execution of the instruction B ends in the instruction cycle 6 as shown in FIG. 14 when the memory wait does not occur, whereas If a wait is occurring, instruction cycle 6 as shown in FIG.
Does not end, and ends in instruction cycle 7.

When a memory wait occurs in the IF stage, the wait signal if_ is passed through the OR gate 11.
By asserting wait, AND gate 1
307 is turned off. As a result, a wait state occurs in PC_IF 1302. It should be noted that weights may be generated in the ID stage and the EX stage due to various causes. When a wait occurs in the ID stage, there is a multicycle wait that occurs when a multicycle instruction such as a multiply instruction is executed. In this case, the AND gates 1308 and 1307 are turned off by asserting the wait signal id_wait via the OR gate 12. As a result, a wait state occurs in PC_ID 1303 and PC_IF 1302. Further, when a wait occurs in the EX stage, there is a load use interlock that occurs when an operand loaded from the memory is operated by the next instruction. In this case, the wait signal id_wait is asserted via the OR gate 13 so that the AND gates 1309, 1
308 and 1307 are turned off. As a result, PC_
EX1304, PC_ID1303 and PC_IF13
At 02, a wait state occurs.

FIG. 16 is an explanatory diagram of pipeline processing when a memory wait occurs in the MA stage of each instruction. From this figure, it can be understood that the processing delay in the entire pipeline becomes more significant.

Here, generally, an operand address for accessing the external memory is generated inside the processor chip, and a certain delay occurs until the external memory recognizes the address. This delay value is a signal propagation delay in a bus inside the processor chip and a circuit connecting the bus, a signal propagation delay in an output buffer driving circuit, and an output buffer for driving an external pin of a processor chip having a large capacity. It is the sum of the signal processing delay in itself and the signal propagation delay due to the wiring capacitance and resistance of the address bus outside the processor chip.

Also, a signal propagation delay occurs until the external memory outputs the operand data and the data is fetched in the processor chip. Here, inside the processor chip, the operand data accessed by the end of the MA stage must be determined. Therefore, when the above delay when the external memory is accessed is estimated to be 1/2 instruction cycle for each of the operand address and the operand data,
As shown in FIG. 17, even if a memory wait (one wait) having a time length of one instruction cycle is inserted in the MA stage of each instruction for external memory access, the results are as shown in (a) and (b) of FIG. As shown, the effective access time to the external memory is one instruction cycle. That is, as described above, it is difficult to access an external memory at a time interval of a pipeline pitch (= 1 instruction cycle). Therefore, one wait is inserted in the MA stage to avoid it. However, due to the above-mentioned delay, the effective access time to the external memory becomes one instruction cycle.

Therefore, in the past, further memory weight is required. That is, for example, as shown in FIG. 18, 2 waits are inserted in the MA stage of each instruction for external memory access, and the time length of the MA stage is set to 3 instruction cycles.
As shown in (b), the effective access time having a time length of two instruction cycles was secured for the external memory.

The above facts occur not only in the MA stage but also in the IF stage. As described above, in the conventional technique, the signal delay in the internal and external interfaces of the processor chip reduces the effective access time at the time of external memory access in the pipeline processing. Therefore, the memory weight for compensating for the reduced amount. However, there is a problem in that the processing delay in the entire pipeline is increased because of the extra requirement.

It is an object of the present invention to make it possible to prevent the signal delay in the interface inside and outside the processor chip from affecting the effective access time at the time of accessing the external memory in the pipeline processing.

[0027]

FIG. 1 is a block diagram of the present invention. In the present invention, first, the instruction fetch means 10 shown below is provided as a constituent of the backbone of a pipeline.
1, instruction decoding means 102, instruction execution means 103, memory access means 104, and write back means 105
Have.

That is, the instruction fetch unit 101 fetches an instruction from the memory unit in the instruction fetch stage IF which can be executed in parallel with other stages. The instruction decoding unit 102 decodes the fetched instruction at an instruction decode stage ID that can be executed in parallel with other stages.

The instruction execution means 103 executes the decoded instruction in the instruction execution stage EX which can be executed in parallel with other stages. In the memory access stage MA, which can be executed in parallel with other stages, the memory access means 104 reads or writes to the memory means with respect to the address calculated in the instruction execution stage EX.

Then, the write-back means 105, in the write-back stage WB which can be executed in parallel with the other stages, the operand data obtained from the memory means in the memory access stage MA or the operand processed in the instruction execution stage EX. Write the data to the register means.

Next, in FIG. 1, the instruction fetch stage dividing means 106 outputs the instruction fetch stage IF to the instruction address output stage IFa for outputting the instruction address to the memory means and the instruction corresponding to the instruction address from the memory means. Instruction data input stage IFd for inputting data
Split into. Now, for example, the instruction fetch unit 101, the instruction decoding unit 102, the instruction execution unit 103, the memory access unit 104, and the data used by the write back unit 105 (for example, the program counter value) are sequentially held, and the instruction fetch unit Stage data holding means (PC_IF202), instruction decode stage data holding means (PC_ID203), instruction execution stage data holding means (PC_EX204), memory access stage data holding means (PC_MA205), and write back stage data holding means (PC_WB20).
Suppose a pipeline consisting of 6) is configured. In this case, the instruction fetch stage dividing means 106
The instruction fetch stage data holding means holds the data used in the instruction address output stage IFa which is a stage for outputting the instruction address to the external memory (PC_
IF202) and the instruction data input stage data holding means (PC_Fd 214) for holding the data used in the instruction data input stage IFd, which is the stage for inputting the instruction data corresponding to the instruction address from the memory means.

In FIG. 1, the memory access stage dividing means 109 corresponds to the operand address output stage Ma for outputting the memory access stage MA to the memory means and the operand address to the memory means. It is divided into operand data read / write stages Md for reading or writing operand data. Now, for example, assume the same case as that assumed in the description of the instruction fetch stage dividing unit 106 described above. In this case, the memory access stage dividing means 109 causes the memory access stage data holding means to hold the data used in the operand address output stage Ma which is a stage for outputting the operand address to the memory means. Holding means (PC_MA205),
The memory means is divided into operand data read / write stage data holding means (PC_Md 215) for holding data used in the operand data read / write stage Md which is a stage for reading or writing the operand data corresponding to the operand address. .

In the above-mentioned configuration of the present invention, it further comprises an instruction fetch stage division control means 107 and a memory access stage division control means 110 (both correspond to the pipeline wait / stage number control circuit 801) shown below. can do.

First, the instruction fetch stage division control means 107 fetches instructions to an external memory connected to the outside of the processor chip while the instruction fetch stage division means 106 does not divide the instruction fetch stage IF. At the time of occurrence, the instruction fetch stage IF is sent to the instruction fetch stage dividing means 106.
To split.

Further, the instruction fetch stage division control means 107 has a branch in the execution of the branch instruction while the instruction fetch stage IF is divided, and a branch destination instruction corresponding to the branch is built in the processor chip. At the time of fetching from the internal memory, the instruction fetch stage dividing means 106 is caused to cancel the division of the instruction fetch stage IF.

Next, the memory access stage division control means 110, when the memory access stage division means 109 does not divide the memory access stage MA,
When access of operand data to an external memory connected to the outside of the processor chip occurs, the memory access stage dividing means 109 divides the memory access stage MA.

Further, the memory access stage division control means 110 executes a memory access stage MA in a divided state, executes an instruction without a memory access, and executes a memory access executed by an instruction following the instruction. When it is for the internal memory built in the memory access stage MA, the memory access stage division means 109 is caused to cancel the division of the memory access stage MA.

In the configuration of the invention described above, further, the instruction address output stage wait control means 108 for putting the instruction address output stage IFa into a wait state for an arbitrary number of instruction cycles and the operand address output stage Ma for an arbitrary number of instruction cycles. Operand address output stage wait control means 11 for setting only wait state
1 (both pipeline weight / stage number control circuit 801
Corresponding to the above).

In addition, in the constitution of the invention so far,
The operation of outputting the instruction address in the instruction address output stage IFa and the operation of inputting the instruction data in the instruction data input stage IFd, which are executed by the instruction fetch unit 101, are executed in parallel, and the operand is executed by the memory access unit 104. An output operation of an operand address in the address output stage Ma,
The read or write operation of the operand data in the operand data read / write stage Md can be configured to be executed in parallel.

[0040]

In the instruction fetch stage IF, when the instruction stored in the internal memory built into the processor chip is fetched, the instruction fetch stage IF is not divided. As a result, the penalty for canceling the pipeline processing when a branch occurs can be reduced.

On the other hand, when the instruction fetch stage IF is not divided and the instruction fetch occurs in the external memory connected to the outside of the processor chip, the instruction fetch stage division control means 107 causes the instruction fetch stage IF The dividing unit 106 is caused to divide the instruction fetch stage IF. As a result, in the instruction cycle in which the divided instruction fetch stage IF is executed, it is possible to shorten the time during which the processing of the other stages is in the wait state, and the performance of the pipeline processing at the timing other than when the branch occurs. Can be improved. In this case, the instruction address output stage wait control means 108 appropriately controls the wait state of the instruction address output stage which is generated by dividing the instruction fetch stage IF.

Further, the division of the instruction fetch stage IF is canceled at the time when a branch is generated by the execution of the branch instruction and the branch target instruction corresponding to the branch is fetched from the internal memory incorporated in the processor chip. This makes it possible to change the pipeline state to an optimum state without losing valid data during pipeline processing.

On the other hand, when the access of operand data to the external memory connected to the outside of the processor chip occurs while the memory access stage MA is not divided, the memory access stage division control means 110 makes the memory access. Stage dividing means 109
, The memory access stage MA is divided. As a result, in the instruction cycle in which the divided memory access stage MA is executed, it is possible to shorten the time in which the processing of the other stages is in the wait state, and the performance of the pipeline processing at the timing other than when the branch occurs. Can be improved. In this case, the operand address output stage wait control means 111 appropriately controls the wait state of the operand address output stage generated by dividing the memory access stage MA.

The memory access stage M is executed at the time when an instruction without memory access is executed and the memory access executed by the instruction following the instruction is for the internal memory incorporated in the processor chip.
By releasing the division of A, the state of the pipeline can be changed to the optimum state without losing valid data during pipeline processing, as in the case of the instruction fetch stage.

[0045]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 shows a partial embodiment of the pipeline control device according to the present invention.

In FIG. 2, 1301, 1303, 1304,
The respective portions indicated by 1306 to 1313 are 201, 203, 204, 206 in the prior art shown in FIG.
˜213 has the same function as each part.

The configuration of FIG. 2 differs from that of FIG. 13 in that
It is as follows. That is, first, the instruction fetch stage may optionally include a first instruction fetch stage (hereinafter referred to as an IFa stage) for outputting an instruction address to the memory and a second instruction fetch stage for fetching instruction data from the memory. It can be divided into instruction fetch stages (hereinafter referred to as Fd stages). In addition, the memory access stage inputs or outputs the operand data to or from the first memory access stage (hereinafter, referred to as Ma stage) for outputting the operand address to the memory, as the case may be. Second memory access stage (hereinafter referred to as Md stage). If the instruction fetch stage is not divided, the first instruction fetch stage program counter value holding unit 202 (hereinafter, simply PC_IF20
2) is output to the PC via the multiplexer 220.
In the case where the instruction fetch stage is input to the _ID 203 and the instruction fetch stage is divided, the output of the PC_IF 202 is passed to the second instruction fetch stage program counter value holding unit 214 (hereinafter, referred to as PC_Fd 214) and then to the PC_ID 203 via the multiplexer 220. Is entered. If the memory access stage is not divided, the first memory access stage program counter value holding unit 205 (hereinafter simply referred to as PC_MA 205)
Output of PC_WB20 via multiplexer 221
6 and the memory access stage is divided, the output of the PC_MA 205 is the second memory access stage program counter value holding unit 215 (hereinafter PC
_Md 215) and then input to the PC_WB 206 via the multiplexer 221. Therefore, when neither the instruction fetch stage nor the memory access stage is divided, the configuration of FIG. 2 becomes the same as the configuration of FIG.

The operation of the embodiment having the above configuration will be described below. First, FIG. 3 is an explanatory diagram of pipeline processing when a memory such as an internal memory that can be accessed in one instruction cycle is accessed. In this case, neither the instruction fetch stage nor the memory access stage is divided, the output of PC_IF 202 is input to PC_ID 203 via multiplexer 220, and the output of PC_MA 205 is multiplexer 221.
Is input to PC_WB 206 via. That is, the processing in this case is the same as the general pipeline processing described above with reference to FIG.

Next, FIG. 4 shows the pipeline pitch (= 1
FIG. 10 is an explanatory diagram of pipeline processing when an external memory that is difficult to access at an interval of (instruction cycle) is accessed.

This drawing is shown in FIG.
This will be described in comparison with 8. First, in FIG. 4, the memory access stage is divided into a Ma stage and an Md stage, which is a major feature related to the present invention.
On the other hand, in FIG. 18 relating to the conventional technique, the memory access stage is not divided. As a result, in FIG. 4, for example, in the instruction cycle 6, M for the instruction A
By executing the d stage, operand data for the instruction A is transferred between the CPU and the external memory, and at the same time, the Ma (Maw) stage for the instruction B is executed, so that the instruction B for the instruction B is executed. Operand address for accessing operand data is C
It will be output from the PU to the external memory. That is, by dividing the stage in which the CPU specifies the operand address in the external memory and the stage in which the CPU transmits and receives the operand data to and from the external memory,
These operations can be pipelined in parallel between two instructions.

As a result, the operation of FIG. 4 has the following advantages as compared with the operation of FIG. That is, first
In FIGS. 4 and 18, the instruction cycle length required to execute the memory access is 3 instruction cycles. As a result, in both cases, (c) and (d) of FIG. 4 and (a) of FIG.
As shown in (b), an effective access time having a time length of two instruction cycles is secured for the external memory.

However, of the three instruction cycles which form the memory access stage, the time to enter the memory wait state is two instruction cycles in FIG.
Then, it is only one instruction cycle. Therefore, the time during which the other instruction stages cannot be executed in parallel among the three instruction cycle times that constitute the memory access stage is two instruction cycles in FIG. 18, whereas it is only one instruction cycle in FIG.

For this reason, in the instruction execution stage for the instruction B following the instruction A, for example, in FIG.
A memory wait (E) having the same time length as the time length (MAw × 2) of the two waits inserted in the MA stage of instruction A
Xw × 2) is inserted, the instruction A in FIG.
Memory weight (EXw) having the same time length as the time length (Maw × 1) of one weight inserted in the Ma stage of
X1) is only inserted. Therefore, in FIG. 4, in the instruction cycle 6 in which the Md stage of the instruction A is executed, the Ma stage which is the next stage to the EX stage for the instruction B can be executed. Regarding the instructions C to E, in the instruction cycle 6, the state before the instruction cycle 5 is not repeated.

As a result, for example, the instruction cycle length until the instruction B finishes executing is 10 instruction cycles in FIG. 18, whereas it is 9 instruction cycles in FIG. Further, for example, the instruction cycle length until the instruction D finishes executing reaches 16 instruction cycles in FIG. 18, whereas it is 13 instruction cycles in FIG. As described above, this embodiment can reduce the processing delay in the entire pipeline as compared with the related art.

FIG. 5 is an explanatory diagram of pipeline processing when an external memory which can be accessed at a time interval of pipeline pitch (= 1 instruction cycle) is accessed.

Also in this case, as in the case of FIG. 4, the memory access stage is divided into the Ma stage and the Md stage. As a result, as shown in (a) and (b) of FIG. 5, an effective access time having a time length of one instruction cycle is secured to the external memory without inserting a memory wait in the memory access stage. be able to.

The above operation is performed not only in the memory access stage but also in the instruction fetch stage, so that the stage outputs I address to the memory.
By dividing into the Fa stage and the Fd stage for fetching instruction data from the memory, exactly the same effect is realized.

Here, when a branch instruction is executed using pipeline processing, generally, in the pipeline, following branch instruction data, the branch instruction is decoded, and as a result, no branch occurs. The data relating to the instruction group to be executed is input. Therefore, if a branch occurs as a result of the decoding of a branch instruction, the data related to the instruction group input to the pipeline following the data related to the branch instruction is canceled and the data related to the branch destination instruction group is input. There is a need to fix it.

In this case, the instruction fetch stage is IF
By being divided into a stage and Fd stage,
When the number of stages of pipeline processing becomes long, the penalty due to cancellation of pipeline processing at the time of branch occurrence increases as described below, and the performance of pipeline processing deteriorates.

The above problem will be described by comparing the case where the instruction fetch stage is not divided and the case where the instruction fetch stage is divided. FIG. 6 is a diagram showing pipeline processing when a branch occurs when the instruction fetch stage is not divided.

First, in the instruction cycle 2, the instruction decode module not shown in the figure
The branch instruction A is decoded by determining the program counter value corresponding to the branch instruction A set in 203.

As a result, the instruction decoding module outputs the branch offset address, which is the operand data of the branch instruction, to the PC_adder 201 shown in FIG. PC
The _adder 201 adds the above branch offset address to the current program counter value output from the PC_IF 202.

The program counter value corresponding to the branch destination instruction C obtained as a result is P in the instruction cycle 3.
It is set in C_IF202. Then, in the instruction cycle 3, the instruction fetch module (not shown) determines the branch destination instruction C as shown in FIG. 6 by determining the program counter value corresponding to the branch destination instruction C set in the PC_IF 202. Fetch from memory.

Therefore, when the instruction fetch stage is not divided as shown in FIG. 6, only the data relating to one instruction of the instruction B is input to the pipeline by the time the decoding of the branch instruction A is completed. Therefore, only the data related to the one instruction is canceled. Specifically, in instruction cycles 5 and 6, the contents of PC_MA 205 and PC_Md 215 corresponding to instruction B are cleared, and in instruction cycle 7, the contents of PC_WB 206 corresponding to instruction B are cleared. Note that the IF stage, the ID stage, and the EX stage corresponding to the instruction B do not affect the execution of other instructions even if they are executed. Therefore, in each of the instruction cycles 2 to 4, the PC_IF 20 corresponding to the instruction B is
2, it is not necessary to clear the contents of PC_ID 203 and PC_EX 204.

Next, in FIG. 7, the instruction fetch stage is I
It is a figure showing pipeline processing when a branch occurs in the case of being divided into a Fa stage and an Fd stage.

In this case, since the data relating to the two instructions B and C have been input to the pipeline by the time the decoding of the branch instruction A is completed, these two data are canceled. .

As can be understood from the above description, when the instruction fetch stage is not divided as shown in FIG. 6, a branch instruction is executed to cause a branch, and as a result, the branch destination Before the instruction is executed, it takes only two instruction cycles, but when the instruction fetch stage is divided into the IFa stage and the Fd stage as shown in FIG. 7, the branch instruction is executed. Causes a branch, and as a result, it takes three instruction cycles until the instruction at the branch destination is executed.

In this way, if the number of stages of pipeline processing becomes long due to the division of the instruction fetch stage, the performance of pipeline processing will deteriorate.

In order to solve the above problems, the present embodiment is characterized in that whether or not the instruction fetch stage is divided can be controlled according to the situation. Similar control is performed for the memory access stage.

Specifically, the instruction fetch stage is divided when the instruction fetch to the external memory occurs while the instruction fetch stage is not divided. Similarly, the memory access stage is divided when the memory access to the external memory occurs in the state where the memory access stage is not divided.

Then, in the state where the instruction fetch stage is divided, execution of the branch instruction causes a branch,
At the time when the branch destination instruction is fetched from the internal memory, the division of the instruction fetch stage is released. Also, with the memory access stage divided,
When the instruction without the operand access is executed and the operand access executed by the instruction following the instruction is the operand access to the internal memory, the division of the memory access stage is released. Generally, in a RISC processor, memory access occurs only when a load instruction or a store instruction is executed. Therefore, when an instruction other than these instructions is executed, the division of the memory access stage is canceled. Can be done.

FIG. 8 is a peripheral configuration diagram of a pipeline weight / stage number control circuit 801 for realizing the above operation. 9 and 10 are state transition diagrams and timing charts of the instruction fetch stage control operation executed by this circuit, and FIGS. 11 and 12 are state transition diagrams of the memory access stage control operation executed by this circuit. 3 is a timing chart.

First, the instruction fetch stage control operation executed by the pipeline wait / stage number control circuit 801 will be described. As can be understood from the state transition diagram of FIG. 9, the pipeline weight / stage number control circuit 801
Functions as a 3-state finite state machine for instruction fetch stage control operations.

In FIG. 9, the first state is the IDLE state. In this state, the pipeline weight / stage number control circuit 801 does not assert the if_wait signal and the fd_sel signal to the pipeline control circuit shown in FIG. This state can occur when an instruction stored in the internal memory (hereinafter referred to as an internal instruction) is being fetched. And in this state,
The instruction fetch stage is not divided, and in FIG.
The output of the C_IF 202 is input to the PC_ID 203 via the multiplexer 220. In this IDLE state, since the instruction fetch stage is not divided, as described above, the penalty for canceling the pipeline processing when a branch occurs can be reduced.

The IDLE state is repeated until the external instruction fetch signal 803 from the instruction fetch module (not shown) is asserted. The external instruction fetch signal 803 is a signal indicating that a fetch for an instruction stored in the external memory (hereinafter referred to as an external instruction) has occurred.

The external instruction fetch signal 803 is asserted and the memory wait number control circuit 802 is activated.
When the if_waiting signal from is asserted,
A transition occurs from the IDLE state to the second state, the WAIT state. When the external instruction fetch signal 803 is asserted but the if_waiting signal from the memory wait number control circuit 802 is not asserted, a transition to the LAST state, which is the third state, occurs.

In the WAIT state, the pipeline weight / stage number control circuit 801 is different from the if_wait signal and fd_s in the pipeline control circuit shown in FIG.
Assert both el signals.

This WAIT state is repeated only during the time when the if_waiting signal from the memory wait number control circuit 802 is asserted. This if_wa
The iting signal is not asserted when the wait is not inserted or one wait is inserted in the instruction fetch stage, and is asserted only for the time of n−1 instruction cycle when the n (n ≧ 2) wait is inserted. . When the if_waiting signal is negated, a transition from the WAIT state to the LAST state, which is the third state, occurs.

In the LAST state, the pipeline wait / stage number control circuit 801 maintains the assertion of the fd_sel signal and negates the if_wait signal for the pipeline control circuit shown in FIG. In this state, an instruction fetch module (not shown) fetches an external instruction.

In this LAST state, one or both of the branch occurrence signal 805 from the instruction decode module (not shown) and the internal instruction fetch signal 804 from the instruction fetch module (not shown) are negated, and the instruction fetch module The external instruction fetch signal 803 from the memory wait count control circuit 802 or the if_waiting signal from the memory wait number control circuit 802 is maintained only while it is negated. Here, the branch occurrence signal 805 is a signal indicating that a branch has occurred as a result of execution of a branch instruction that is an external instruction. The internal instruction fetch signal 804 is a signal indicating that an instruction fetch to the internal memory has occurred.

In the LAST state, a fetch for a new external instruction occurs particularly in an instruction fetch module (not shown), the external instruction fetch signal 803 is asserted, and the memory wait number control circuit 80
When the if_waiting signal from 2 is asserted, the transition to the WAIT state occurs again.

As described above, in the IDLE state where the instruction fetch stage is not divided, the instruction fetch stage is divided when the instruction fetch to the external memory occurs, and in FIG. 2, the output of PC_IF 202 passes through PC_Fd 214. Later multiplexer 2
It will be input to the PC_ID 203 via 20. At this time, when the if_waiting signal from the memory wait number control circuit 802 is asserted, that is, when the external memory that is difficult to access at the time interval of the pipeline pitch (= 1 instruction cycle) is accessed, , A necessary wait state is generated in the WAIT state (see FIG. 4 described above). On the other hand, if_waitin from the memory wait number control circuit 802
When the g signal is not asserted, that is, when the external memory that can be accessed at the time interval of the pipeline pitch is accessed, the transition to the LAST state occurs directly without the WAIT state, The instruction fetch stage is divided (see FIG. 5 described above). Then, in the LAST state, the instruction fetch is performed while the instruction fetch stage is divided,
As described above, the performance of pipeline processing can be improved at timings other than when a branch occurs.

In the above-mentioned LAST state, when the pipeline processing is canceled, that is, the branch occurrence signal 805 from the instruction decoding module not shown is asserted, and the internal instruction fetch from the instruction fetch module not shown in particular. A transition to the IDLE state occurs when signal 803 is asserted. As a result, for example, as shown in FIG. 10, a branch occurs as a result of the execution of the ID stage for the branch instruction A, and
If the branch destination instruction D is an internal instruction, the fd_sel signal is negated and the division of the instruction fetch stage is released.

Next, the memory access stage control operation executed by the pipeline wait / stage number control circuit 801 shown in FIG. 8 will be described. As can be seen from the state transition diagram of FIG. 11, the pipeline weight /
The stage number control circuit 801 also functions as a three-state finite state machine in the memory access stage control operation as in the instruction fetch stage control operation.

First, in the IDLE state, the pipeline wait / stage number control circuit 801 is different from the ma_wait signal and m for the pipeline control circuit shown in FIG.
Do not assert the d_sel signal. In this state, the operand access to the internal memory is being executed. Then, in this state, the memory access stage is not divided, and in FIG. 2, the output of PC_MA 205 is output to PC_WB 206 via multiplexer 221.
Has been entered in.

In the IDLE state, an external memory access signal 806 from a memory access control circuit (not shown) is used.
Is repeated until is asserted. The external memory access signal 806 is a signal indicating that a fetch for an instruction stored in the external memory (hereinafter referred to as an external instruction) has occurred. This external memory access signal 8
Reference numeral 06 is a signal indicating that an operand access to the external memory has occurred.

Then, the external memory access signal 806 is asserted and the memory wait number control circuit 80
When the ma_waiting signal from 2 is asserted, a transition occurs from the IDLE state to the second state, the WAIT state. In addition, the external memory access signal 80
6 was asserted, but the memory wait number control circuit 80
When the ma_waiting signal from 2 is not asserted, a transition to the LAST state, which is the third state, occurs.

In the WAIT state, the pipeline weight / stage number control circuit 801 has the ma_wait signal and the md_s signal for the pipeline control circuit shown in FIG.
Assert both el signals. In the example of FIG. 4, the timing of the instruction cycle 4 is the timing of this WAIT state, as shown in (a) and (b).

This WAIT state is repeated only while the ma_waiting signal from the memory wait number control circuit 802 is asserted. This ma_wa
The iting signal is not asserted when a wait is not inserted or one wait is inserted in the memory access stage, and is asserted only for the time of n-1 instruction cycle when an n (n ≧ 2) wait is inserted. . When the ma_waiting signal is negated, a transition from the WAIT state to the LAST state, which is the third state, occurs.

In the LAST state, the pipeline wait / stage number control circuit 801 maintains the assertion of the md_sel signal and negates the ma_wait signal for the pipeline control circuit shown in FIG. In this state, a memory access module (not shown) executes operand access to the external memory. In the example of FIG. 4, as shown in (a) and (b),
The timing of the instruction cycle 5 is the timing described above.

In the LAST state, a non-memory access generation signal 80 from an instruction decoding module (not shown) is used.
8 or particularly one or both of the internal memory access signals 807 from the memory access control circuit (not shown) are negated, and the external memory access signal 806 from the memory access control circuit or the ma_waiting signal from the memory wait number control circuit 802. Only maintained while one or both are negated. here,
The non-memory access instruction generation signal 808 is a signal indicating that an instruction other than a load instruction and a store instruction has been executed. The internal memory access signal 807 is a signal indicating that an operand access to the internal memory has occurred.

In the LAST state, a new operand access to the external memory occurs particularly in a memory access module (not shown), the external memory access signal 806 is asserted, and the ma_waiting signal from the memory wait number control circuit 802 is asserted. Then, the transition to the WAIT state occurs again. In the example of FIG. 4, as shown in (a) and (b), the timing of the instruction cycle 6 is the timing of the WAIT state again.

As described above, in the IDLE state where the memory access stage is not divided, when the operand access to the external memory occurs, the memory access stage is divided, and in FIG.
The output of the MA_MA 205 is input to the PC_WB 206 via the multiplexer 221 after passing through the PC_Md 215. Then, in the LAST state, operand access is performed in a state where the memory access stage is divided.

In the LAST state described above, a point at which an instruction that does not generate an operand access to an internal memory or an external instruction is executed, that is, a non-memory access instruction generation signal 8 from an instruction decoding module (not shown).
When 08 is asserted and the internal memory access signal 807 from the memory access control circuit (not shown) is asserted, a transition to the IDLE state occurs. As a result, for example, as shown in FIG. 12, the memory operation is not generated by executing the comparison operation instruction B after the load instruction A for the external memory, and the next instruction C is the load instruction for the internal memory. If so, the md_sel signal is negated and the division of the memory access stage is released.

In the embodiment described above, the configuration example of the pipeline control device relating to the pipeline of the program counter has been described. However, the present invention is not limited to this. For example, the operation code of an instruction or the control obtained by decoding the operation code. The present invention can be applied to a pipeline for transmitting a signal to each module or a pipeline for transmitting an operand of an instruction to each module.

[0096]

According to the present invention, in pipeline processing, it is possible to switch the instruction fetch stage and the memory access stage between the divided state and the non-divided state. As a result, when an instruction fetch or operand data access is occurring to the internal memory built in the processor chip, the stages are not divided, so that pipeline processing at the time of branch occurrence The penalty for cancellation can be reduced. In addition, when an instruction fetch or an operand data access to an external memory connected to the outside of the processor chip occurs, each stage becomes a divided state, and the divided instruction fetch stage Alternatively, in the instruction cycle in which the memory access stage is being executed, the processing time of other stages can be shortened and the performance of pipeline processing can be improved at timings other than when a branch occurs. Becomes

Furthermore, when a branch occurs due to the execution of the branch instruction and the branch destination instruction corresponding to the branch is fetched from the internal memory incorporated in the processor chip, the division of the instruction fetch stage is canceled. , The division of the memory access stage is canceled at the time when an instruction without memory access is executed and the memory access executed by the instruction following the instruction is to the internal memory incorporated in the processor chip. This makes it possible to change the pipeline state to an optimum state without losing valid data during pipeline processing.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram of part of an embodiment of a pipeline control device according to the present invention.

FIG. 3 is an explanatory diagram of pipeline processing when an accessible memory is accessed in one instruction cycle.

FIG. 4 is an explanatory diagram of pipeline processing when an external memory that is difficult to access at a time interval of a pipeline pitch is accessed.

FIG. 5 is an explanatory diagram of pipeline processing when an external memory that can be accessed at a pipeline pitch time interval is accessed.

FIG. 6 is an explanatory diagram of pipeline processing when a branch occurs when the instruction fetch stage is not divided.

FIG. 7 shows instruction fetch stages IFa stage and Fd.
It is an explanatory view of pipeline processing when a branch occurs in the case of being divided into stages.

FIG. 8 is a peripheral configuration diagram of a pipeline weight / stage number control circuit 801.

FIG. 9 is a state transition diagram of an instruction fetch stage control operation.

FIG. 10 is a timing chart of an instruction fetch stage control operation.

FIG. 11 is a state transition diagram of a memory access stage control operation.

FIG. 12 is a timing chart of a memory access stage control operation.

FIG. 13 is a diagram showing a configuration example of a part of a pipeline control device in a conventional pipeline processor.

FIG. 14 is an explanatory diagram of pipeline processing.

FIG. 15 is an explanatory diagram of pipeline processing when a conventional memory wait occurs.

FIG. 16 is an explanatory diagram of conventional pipeline processing when a memory wait occurs for each instruction.

FIG. 17 is an explanatory diagram (in the case of 1 wait) of conventional pipeline processing at the time of accessing an external bus.

FIG. 18 is an explanatory diagram (in the case of 2 waits) of conventional pipeline processing at the time of accessing an external bus.

[Explanation of symbols]

101 instruction fetch means 102 instruction decode means 103 instruction execution means 104 memory access means 105 write back means 106 instruction fetch stage division means 107 instruction fetch stage division control means 108 instruction address output stage wait control means 109 memory access stage division means 110 memory access Stage division control means 111 Operand address output stage wait control means 201 Adder (PC_adder) 202 First instruction fetch stage program counter value holding unit (PC_IF202) 203 Instruction decode stage program counter value holding unit (PC_ID) 204 Instruction execution stage program counter value Holding Unit (PC_EX) 205 Memory Access Stage Program Counter Value Holding Unit (PC_EX A) 206 write back stage program counter value holding unit (PC_WB) 207 to 210, 216, 217 AND gates 211 to 213, 218, 219 or gate 214 second instruction fetch stage program counter value holding unit (PC_Fd) 215 second memory access Stage program counter value holding unit (PC_Md) 220, 221 Multiplexer 801 Pipeline wait / stage number control circuit 802 Memory wait number control circuit 803 External instruction fetch signal 804 Internal instruction fetch signal 805 Branch occurrence signal 806 External memory access signal 807 Internal memory access Signal 808 Non-memory access instruction generation signal

Claims (34)

(57) [Claims] 1. An instruction fetch means (101) for fetching an instruction from a memory means in an instruction fetch stage (IF) which can be executed in parallel with another stage.
And an instruction decoding unit (102) for decoding the fetched instruction in an instruction decoding stage (ID) that can be executed in parallel with other stages, and an instruction execution that can be executed in parallel with other stages. In the stage (EX), in the instruction execution means (103) that executes the decoded instruction, and in the memory access stage (MA) that can execute in parallel with other stages, calculation in the instruction execution stage (EX) The memory access means (104) for reading or writing to the memory means with respect to the read address and the write back stage (WB) which can be executed in parallel with other stages, in the memory access stage (MA). Operand data obtained from the memory means or the instruction execution A write-back means (105) for writing the operand data processed in the stage (EX) to a register means, and an instruction address output stage (IFa) for outputting an instruction address to the memory means by the instruction fetch stage (IF). And an instruction fetch stage dividing means (106) for dividing instruction data corresponding to the instruction address from the memory means into instruction data input stages (IFd). . 2. The instruction fetch stage dividing means (1
06) has not divided the instruction fetch stage (IF), the instruction fetch stage dividing means (106) is provided to the instruction fetch stage dividing means (106) at the time point when the instruction fetch is made to the external memory connected to the outside of the processor chip. The variable length pipeline control device according to claim 1, further comprising an instruction fetch stage division control means (107) for dividing the instruction fetch stage (IF). 3. The instruction fetch stage division control means (107), when the instruction fetch stage (IF) is divided, a branch occurs by execution of a branch instruction, and a branch destination corresponding to the branch. The instruction fetch stage dividing means (106) at the time when the instruction is fetched from the internal memory built in the processor chip.
3. The variable length pipeline control device according to claim 2, wherein the instruction fetch stage (IF) is released from the division. 4. The instruction address output stage (IF
The variable length pipeline control according to any one of claims 1 to 3, further comprising an instruction address output stage wait control means (108) for putting a) into a wait state for an arbitrary number of instruction cycles. apparatus. 5. The instruction address output stage (IF) executed by the instruction fetch means (101).
5. The output operation of the instruction address in a) and the input operation of the instruction data in the instruction data input stage (IFd) are executed in parallel, according to any one of claims 1 to 4. A variable length pipeline control device as described. 6. An instruction fetch means (101) for fetching an instruction from a memory means in an instruction fetch stage (IF) which can be executed in parallel with another stage.
And an instruction decoding unit (102) for decoding the fetched instruction in an instruction decoding stage (ID) that can be executed in parallel with other stages, and an instruction execution that can be executed in parallel with other stages. In the stage (EX), in the instruction execution means (103) that executes the decoded instruction, and in the memory access stage (MA) that can execute in parallel with other stages, calculation in the instruction execution stage (EX) In the memory access means (104) for reading or writing to the memory means for the written address and the write back stage (WB) which can be executed in parallel with other stages, in the memory access stage (MA). Operand data obtained from the memory means or the instruction execution Write-back means (105) for writing the operand data processed in the stage (EX) to the register means, the instruction fetch means (101), the instruction decode means (102), the instruction execution means (103), and the memory access The data used by the means (104) and the write-back means (105) are sequentially retained, and include an instruction fetch stage data retaining means, an instruction decode stage data retaining means, an instruction execution stage data retaining means, and a memory access. A pipeline composed of stage data holding means and write back stage data holding means, and an instruction address output stage (IFa) which is a stage for the instruction fetch stage data holding means to output an instruction address to the memory means. Used by Address output stage data holding means for holding data to be stored and instruction data for holding data used in an instruction data input stage (IFd) which is a stage for inputting instruction data corresponding to the instruction address from the memory means. A variable length pipeline control device comprising: an instruction fetch stage dividing means (106) for dividing into input stage data holding means. 7. The instruction fetch stage dividing means (1
06) has not divided the instruction fetch stage data holding means, the instruction fetch stage dividing means (10) at the time when an instruction fetch occurs in an external memory connected to the outside of the processor chip.
6) instruction fetch stage division control means (10) for dividing the instruction fetch stage data holding means
7. The variable length pipeline control device according to claim 6, further comprising 7). 8. The instruction fetch stage division control means (107), when the instruction fetch stage holding means is divided, executes a branch instruction to cause a branch, and a branch destination instruction corresponding to the branch. The instruction fetch stage dividing means (106) at the time point when is fetched from the internal memory built in the processor chip.
The variable length pipeline control device according to claim 7, wherein the instruction fetch stage data holding means is released from the division. 9. An instruction address output stage weight control means (108) for causing the instruction address output stage data holding means to wait an output operation of the data held by the means for an arbitrary number of instruction cycles. The variable length pipeline control device according to any one of claims 6 to 8. 10. The variable length pipeline control device according to claim 6, wherein the data held by the pipeline is a program counter value. 11. An instruction fetch means (10) for fetching an instruction from a memory means in an instruction fetch stage (IF) which can be executed in parallel with another stage.
1) and an instruction decoding stage (ID) that can be executed in parallel with other stages, and an instruction decoding unit (102) that decodes the fetched instruction, and can be executed in parallel with other stages. In the instruction execution stage (EX), in the instruction execution means (103) that executes the decoded instruction, and in the memory access stage (MA) that can execute in parallel with other stages, the instruction execution stage (EX). In the memory access means (104) for reading or writing to the memory means with respect to the address calculated in the above, and the write back stage (WB) which can be executed in parallel with other stages, the memory access stage (MA ) Operand data obtained from the memory means or the instruction A write-back means (105) for writing the operand data processed in the execution stage (EX) to a register means, and a memory access stage (MA) for an operand address output stage (Ma) for outputting an operand address to the memory means. ) And memory access stage dividing means (109) for dividing the operand data corresponding to the operand address into or from the memory means into operand data read / write stages (Md). Variable length pipeline control device. 12. Accessing the operand data to an external memory connected to the outside of a processor chip in a state where the memory access stage dividing means (109) does not divide the memory access stage (MA). The memory access stage division control means (110) for dividing the memory access stage (MA) with respect to the memory access stage division means (109) at the point of time of performing, further comprising: memory access stage division control means (110). Variable length pipeline controller. 13. The memory access stage division control means (110) includes the memory access stage (M).
In the state where A) is divided, the memory is executed when an instruction without memory access is executed and the memory access executed by the instruction following the instruction is for the internal memory incorporated in the processor chip. 13. The variable length pipeline control device according to claim 12, wherein the access stage dividing means (109) is caused to cancel the division of the memory access stage (MA). 14. The method according to claim 11, further comprising an operand address output stage wait control means (111) that puts the operand address output stage (Ma) into a wait state for an arbitrary number of instruction cycles. 2. A variable length pipeline control device according to item 1. 15. An output operation of the operand address in the operand address output stage (Ma) executed by the memory access means (104) and the operand data read / write stage (M).
The variable length pipeline control device according to any one of claims 11 to 14, wherein the read or write operation of the operand data in d) is executed in parallel. 16. An instruction fetch means (10) for fetching an instruction from a memory means in an instruction fetch stage (IF) which can be executed in parallel with another stage.
1) and an instruction decoding stage (ID) that can be executed in parallel with other stages, and an instruction decoding unit (102) that decodes the fetched instruction, and can be executed in parallel with other stages. In the instruction execution stage (EX), in the instruction execution means (103) that executes the decoded instruction, and in the memory access stage (MA) that can execute in parallel with other stages, the instruction execution stage (EX). In the memory access means (104) for reading or writing to the memory means with respect to the address calculated in the above, and the write back stage (WB) which can be executed in parallel with other stages, the memory access stage (MA ) Operand data obtained from the memory means or the instruction Write-back means (105) for writing the operand data processed in the execution stage (EX) to the register means, the instruction fetch means (101), the instruction decode means (102), the instruction execution means (103), and the memory Data to be used by the access unit (104) and the write-back unit (105) are sequentially held, and each of the instruction fetch stage data holding unit, the instruction decode stage data holding unit, the instruction execution stage data holding unit, and the memory. A pipeline including an access stage data holding unit and a write back stage data holding unit, and an operand address output stage which is a stage for outputting an operand address to the memory unit Operand address output stage data holding means for holding data used in memory (Ma), and operand data read / write stage (stage for reading or writing operand data corresponding to the operand address in the memory means). Memory access stage dividing means (10) for dividing the data used in Md) into operand data read / write stage data holding means
9) and a variable length pipeline controller. 17. The access of the operand data to an external memory connected to the outside of the processor chip occurs in a state where the memory access stage dividing means (109) does not divide the memory access stage data holding means. The memory access stage division control means (110) for dividing the memory access stage data holding means with respect to the memory access stage division means (109) at the time of performing, is further provided. Variable length pipeline controller. 18. The memory access stage division control means (110) executes an instruction without memory access and executes an instruction following the instruction while the memory access stage holding means is divided. The memory access stage dividing means (109) is caused to cancel the division of the memory access stage data holding means when the memory access is to an internal memory built in the processor chip. Item 18. The variable length pipeline control device according to item 17. 19. An operand address output stage wait control means (11) for causing said operand address output stage data holding means to wait the output operation of the data held by said means for an arbitrary number of instruction cycles.
The variable length pipeline control device according to any one of claims 16 to 18, further comprising 1). 20. The variable length pipeline control device according to claim 16, wherein the data held by the pipeline is a program counter value. 21. Instruction fetch means (10) for fetching instructions from memory means in an instruction fetch stage (IF) which can be executed in parallel with other stages.
1) and an instruction decoding stage (ID) that can be executed in parallel with other stages, and an instruction decoding unit (102) that decodes the fetched instruction, and can be executed in parallel with other stages. In the instruction execution stage (EX), in the instruction execution means (103) that executes the decoded instruction, and in the memory access stage (MA) that can execute in parallel with other stages, the instruction execution stage (EX). In the memory access means (104) for reading or writing to the memory means with respect to the address calculated in the above, and the write back stage (WB) which can be executed in parallel with other stages, the memory access stage (MA ) Operand data obtained from the memory means or the instruction A write back means (105) for writing the operand data processed in the execution stage (EX) to a register means, and an instruction address output stage (IFa) for outputting an instruction address to the memory means. ), An instruction fetch stage dividing means (106) for dividing instruction data corresponding to the instruction address from the memory means into instruction data input stages (IFd), and the memory access stage (MA) for operand address A memory access for dividing an operand address output stage (Ma) for outputting to the memory means and an operand data read / write stage (Md) for reading or writing the operand data corresponding to the operand address with respect to the memory means. Variable pipeline control apparatus characterized by comprising a stage splitting means (109), the. 22. When an instruction fetch occurs in an external memory connected to the outside of a processor chip in a state where the instruction fetch stage dividing means (106) does not divide the instruction fetch stage (IF). In the instruction fetch stage dividing means (106)
22. The variable length pipeline control device according to claim 21, further comprising an instruction fetch stage division control unit (107) for dividing the instruction fetch stage (IF). 23. The instruction fetch stage division control means (107), when the instruction fetch stage (IF) is divided, a branch occurs by execution of a branch instruction, and a branch destination corresponding to the branch. When the instruction is fetched from the internal memory built in the processor chip, the instruction fetch stage dividing means (10
23. The variable length pipeline control device according to claim 22, wherein 6) is caused to cancel the division of the instruction fetch stage (IF). 24. Accessing the operand data to an external memory connected to the outside of a processor chip in a state where the memory access stage dividing means (109) does not divide the memory access stage (MA). 24. The memory access stage division control means (110) for dividing the memory access stage (MA) with respect to the memory access stage division means (109) at the point of time of performing, further comprising: memory access stage division control means (110). The variable length pipeline control device according to any one of claims. 25. The memory access stage division control means (110) comprises the memory access stage (M).
In the state where A) is divided, the memory is executed when an instruction without memory access is executed and the memory access executed by the instruction following the instruction is to the internal memory incorporated in the processor chip. 25. The variable length pipeline control device according to claim 24, which causes the access stage dividing means (109) to release the division of the memory access stage (MA). 26. The instruction address output stage (IF
Instruction address output stage wait control means (108) for putting a) into a wait state for an arbitrary number of instruction cycles
26. An operand address output stage wait control means (111) for putting the operand address output stage (Ma) into a wait state for an arbitrary number of instruction cycles, further comprising: A variable length pipeline control device according to item. 27. The instruction address output stage (IF), which is executed by the instruction fetch means (101).
The operand address output stage in which the output operation of the instruction address in a) and the input operation of the instruction data in the instruction data input stage (IFd) are executed in parallel and are executed by the memory access means (104). 27. The output operation of the operand address in (Ma) and the read or write operation of the operand data in the operand data read / write stage (Md) are executed in parallel. The variable length pipeline control device according to any one of claims. 28. An instruction fetch means (10) for fetching an instruction from a memory means in an instruction fetch stage (IF) which can be executed in parallel with another stage.
1) and an instruction decoding stage (ID) that can be executed in parallel with other stages, and an instruction decoding unit (102) that decodes the fetched instruction, and can be executed in parallel with other stages. In the instruction execution stage (EX), in the instruction execution means (103) that executes the decoded instruction, and in the memory access stage (MA) that can execute in parallel with other stages, the instruction execution stage (EX). In the memory access means (104) for reading or writing to the memory means with respect to the address calculated in the above, and the write back stage (WB) which can be executed in parallel with other stages, the memory access stage (MA ) Operand data obtained from the memory means or the instruction Write-back means (105) for writing the operand data processed in the execution stage (EX) to the register means, the instruction fetch means (101), the instruction decode means (102), the instruction execution means (103), and the memory Data to be used by the access unit (104) and the write-back unit (105) are sequentially held, and each of the instruction fetch stage data holding unit, the instruction decode stage data holding unit, the instruction execution stage data holding unit, and the memory. A pipeline composed of access stage data holding means and write back stage data holding means, and an instruction address output stage (IFa) which is a stage for outputting an instruction address to the memory means by the instruction fetch stage data holding means. ) Instruction address output stage data holding means for holding data used and instruction holding data used in the instruction data input stage (IFd) which is a stage for inputting instruction data corresponding to the instruction address from the memory means The instruction fetch stage dividing means (106) for dividing into the data input stage data holding means and the memory access stage data holding means are constituted by an operand address output stage (Ma) which is a stage for outputting an operand address to the memory means. Operand address output stage for holding data to be used Data holding means and operand data read / write stage (M) which is a stage for reading or writing operand data corresponding to the operand address with respect to the memory means Memory access stage dividing means (10 for dividing the operand data read / write stage data holding means for holding the data used by)
9) and a variable length pipeline controller. 29. When an instruction fetch occurs in an external memory connected to the outside of a processor chip in a state where the instruction fetch stage dividing means (106) does not divide the instruction fetch stage data holding means. In the instruction fetch stage dividing means (1
06) to divide the instruction fetch stage data holding means into instruction fetch stage division control means (1
The variable length pipeline controller according to claim 28, further comprising: 07). 30. The instruction fetch stage division control means (107), when the instruction fetch stage holding means is divided, executes a branch instruction to cause a branch, and a branch destination instruction corresponding to the branch. Is fetched from the internal memory incorporated in the processor chip, the instruction fetch stage dividing means (10
30. The variable length pipeline control device according to claim 29, which causes 6) to cancel the division of the instruction fetch stage data holding means. 31. Accessing the operand data to an external memory connected to the outside of a processor chip in a state where the memory access stage dividing means (109) does not divide the memory access stage data holding means. 31. The memory access stage division control means (110) for dividing the memory access stage data holding means with respect to the memory access stage division means (109) at the point of time of the operation, further comprising: memory access stage division control means (110). The variable length pipeline control device according to any one of claims. 32. The memory access stage division control means (110) executes an instruction without memory access and executes an instruction following the instruction in a state where the memory access stage holding means is divided. The memory access stage dividing means (109) is caused to cancel the division of the memory access stage data holding means when the memory access is to an internal memory built in the processor chip. Item 32. The variable length pipeline controller according to item 31. 33. Instruction address output stage wait control means (108) for causing the instruction address output stage data holding means to wait the output operation of the data held by the means for an arbitrary number of instruction cycles, and the operand address. 29. Operand address output stage wait control means (111) for causing the output stage data holding means to wait for an output operation of the data held by the means for an arbitrary number of instruction cycles, further comprising: 33. The variable length pipeline control device according to any one of items 1 to 32. 34. The variable length pipeline control device according to claim 28, wherein the data held by the pipeline is a program counter value.