JPH0266628A - Information processor - Google Patents

Abstract

PURPOSE:To quickly release an instruction buffer and to read the stream of the branching destination of the subsequent branch instruction by preparing plural instruction buffers and an address buffer which holds the instruction read addresses of each stream and can be controlled independently of those instruction buffers. CONSTITUTION:The output of an instruction address adder 19 is selected by a selector 22 and stored in an instruction counter register 23 as the continuous subsequent instruction addresses. When the branching destination stream of a branch instruction is read out, the read addresses are successively stored in an instruction counter queue 20. When the branch instruction is executed, the continuous subsequent instruction addresses are obtained and outputted. At the same time, the instruction addresses of the branching destination streams are selected by a selector 21 and outputted as the instruction counters. When the branch existence is decided with execution of the branch instruction, the selector 22 selects the output of the selector 21 and the branch instruction address is stored in the register 23. Thus it is possible to release an instruction buffer without preparing an arithmetic execution stage of the branch instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to an information processing device that pre-controls instruction processing using a pipeline processing method.

[Conventional technology]

Conventionally, an information processing device that uses this kind of pipeline processing method has been provided with a plurality of instruction buffers, as described in Japanese Patent Application Laid-Open No. 58-96345, and prior to execution of a branch instruction, a branch destination instruction is stored. The processing stream (a series of instructions read from the storage device) is read, and when it is determined that the branch is established, the input to the instruction decoding circuit is transferred from the stream where the branch instruction appeared (main stream) to the branch destination instruction processing. By immediately switching to the stream, the overhead of reading the branch destination instruction is reduced.

Also, in the address buffer corresponding to each instruction buffer,
The read address of the stream of instruction processing is held, and when an instruction is executed, the instruction length of the instruction is added to the address of the address buffer corresponding to the stream being processed to obtain a continuous next instruction address. When a branch instruction is executed, the next consecutive instruction address is determined, and the instruction read address of the address buffer corresponding to the branch destination target stream is selected to determine the branch destination instruction address. These consecutive next instruction addresses,
The branch destination instruction address is used as a return address when an interrupt or failure occurs during execution of the instruction. The address of the instruction being processed is stored in the instruction counter register and used for managing the execution of the instruction processing. The instruction count value (address of the instruction being executed) that manages the execution of such instruction processing is herein referred to as an instruction counter.

FIG. 3 is a block diagram showing essential parts of an example of a conventional pipeline processing type information processing device.

In FIG. 3, 31 is a first instruction buffer, 32 is a second instruction buffer, and 33 is a third instruction buffer.

34 is a selector, 35 is an instruction decoding circuit, 36 is a branch determination circuit, 37 is an execution queue, and 38 is a selector for selecting instruction information from the execution queue 37. 39 is an instruction address adder, 40 to 42 are selectors for selecting an instruction counter from the instruction address adder 39 or the instruction decode circuit 35, 43 is a first instruction counter buffer, 44 is a second instruction counter buffer, 45
is a third instruction counter buffer, and 46 is a selector. In this information processing device, instructions are processed using a pipeline processing method. In other words, execution of each instruction process forms a stream of a series of instructions, and in that stream, each processing stage (instruction read stage, decode stage, operand read stage, operation execution stage, etc.) is sequentially advanced and piped. Executed in line processing.

The instruction sequence 1 is stored in each of the instruction buffers 31 to 33 for each stream of instruction processing, and corresponds to the instruction counter buffers 43 to 45, respectively.

The next instruction to be executed is selected by a control signal from the branch determination circuit 36, for example, selected from the first instruction buffer 31 by the selector 34, and supplied to the instruction decoding circuit 35 to be decoded. When the instruction decode circuit 35 decodes the instruction, it stores the instruction length and instruction stream number in the execution waiting instruction queue 37 along with the setup information necessary when executing the instruction. The instruction processing information stored in the execution waiting instruction queue 37 is sent to the selector 38
The set-up information 2a, the instruction length 2b,
The instruction stream number 2c is output to each. When entering the operation execution stage, the instruction counter buffer 43
.about.45, the instruction counter corresponding to the stream of the instruction processing is selected by the selector 46 and outputted according to the instruction of the instruction stream number 2c. Further, the instruction address adder 39 adds the instruction length 2b to the instruction counter, and
as the next instruction counter.

It is set to the original instruction counter buffer via selectors 40-42.

When a branch instruction is decoded by the instruction decoding circuit 35, the instruction decoding circuit 35 outputs a branch destination instruction address and forms a stream for one branch destination instruction. Therefore, instructions are read from instruction string 1, and an empty address is read out. It is stored in one of the instruction buffers 31-33. At this time,
The branch destination instruction address output from the instruction decode circuit 35 is held in the corresponding instruction counter buffers 43-45.

Specifically, we will explain the instruction processing operation in such an information processing device by taking as an example the case where processing of an instruction sequence including a branch instruction is performed, and how a stream corresponding to the instruction processing is generated and the instruction processing is performed. explain.

FIG. 4 is a diagram showing an example of an instruction stream for explaining the instruction processing operation of the information processing apparatus shown in FIG. When an information processing device executes instruction processing of a sequence of instructions, it generates a stream of instruction processing and executes the instruction processing by pipeline processing. First, a stream of instructions to be executed is stored in the first instruction buffer 31, and the instruction counter is
is set in the instruction counter buffer 43 of . As a result, the first stream #0 serving as the main stream is generated, and instruction processing of the instruction sequence is executed by pipeline processing. As the instruction processing 50 of stream #0 progresses and a branch instruction 51 appears, the branch instruction 51 generates stream #1 for the instruction processing 52 at the branch destination. Therefore, the second instruction buffer 32 that stores the instructions of the branch destination instruction sequence is secured, and the branch destination instruction address is set in the second instruction counter buffer 44. Branch judgment circuit 3
6, if the branch establishment determination is performed before the instruction operation is executed in the operation execution stage of the pipeline processing, the instruction processing of the advance control performed in the pipeline processing moves to stream #1. Then, the flow proceeds to the execution of instruction processing 52 for stream #1. As the instruction processing 52 progresses, a branch instruction 53 appears next in the processing in stream #1. In this case as well, in the same manner as described above, the branch instruction 53
In order to generate stream #2 corresponding to the branch destination instruction processing 54, the third instruction buffer 33 for storing the instructions of the instruction sequence of one branch destination is secured, and the branch destination instruction address is stored in the third instruction counter. Set in buffer 45. If a branch determination cannot be made immediately in the processing of a branch instruction 53, instruction processing 55 of a non-branched stream is proceeded at the same time. In this case, when the branch instruction 56 appears again in stream #1, a new stream for processing the branch destination instruction is generated in the same manner as described above. At this time, since the first instruction buffer 31 corresponding to stream #0 is not in use, an attempt is made to secure the first instruction buffer 31 by the branch instruction 56.
If the arithmetic execution stage of the branch instruction 51 has not yet been executed, the first instruction counter buffer 43 cannot be released. Therefore, the decoding of the branch instruction 56 has to wait until the arithmetic operation of the branch instruction 51 is executed, which disrupts the flow of pipeline processing and reduces the instruction processing speed.

[Problem to be solved by the invention]

As mentioned above, in a conventional pipeline processing type information processing device, even if a branch instruction decision is made quickly and the instruction in the stream in the instruction buffer is no longer needed, the read address in the instruction processing stream is Since the stored instruction counter buffer corresponds to the instruction buffer, the instruction buffer cannot be released until the branch instruction is executed and the instruction counter is determined. As a result, the reading of an instruction in the branch destination stream of a subsequent branch instruction is forced to wait, making it difficult to improve the performance of instruction processing.

The present invention has been made to solve the above problems.

An object of the present invention is to quickly release the instruction buffer when a branch decision is made and the instruction in the instruction buffer is no longer needed in an information processing device that processes instructions using a pipeline processing method, so that subsequent branches can be processed. The purpose is to enable stream reading of branch destinations of instructions.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides an information processing apparatus using a pipeline processing method, in which each processing stage of instruction reading, decoding, operand reading, and execution is performed sequentially, and processing for each instruction is performed in an overlapping manner. The method is characterized by having a plurality of instruction buffers for storing a series of instruction streams to be processed, and an address buffer that holds an instruction read address for each stream and can be controlled independently of the instruction buffers. .

[Effect]

According to the above means, in an information processing apparatus of a pipeline processing type, a plurality of instruction buffers storing a series of instruction streams of an instruction sequence to be processed and an instruction read address of each stream are held, and the instruction buffers are An independently controllable address buffer is provided. The read address of each stream is stored in an address buffer that is controlled independently of the instruction buffer, and the instruction counter is determined by the address buffer. When a branch destination stream is read, the read address is stored in the address buffer. When an instruction is executed, the next consecutive instruction address is determined by adding the instruction length to the instruction counter stored in the address buffer corresponding to the instruction stream. Also, when a branch instruction is executed, in addition to the control to obtain the next consecutive instruction address, the branch destination input! ~ Select the address buffer corresponding to the ream and find the branch instruction address.

As a result, the address buffer storing the instruction counter is released when the main stream is switched to the branch destination stream by executing a branch instruction. In this way, since the instruction counter is calculated independently of the instruction buffer, if it is determined that the instruction is a one-branch instruction, the instruction buffer that is no longer needed can be immediately released.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram showing the main parts of a pipeline processing type information processing apparatus according to an embodiment of the present invention. In FIG. 1, 11 is the first instruction buffer, and 2 is the second instruction buffer.
13 is a third instruction buffer. 1
4 is a selector, 15 is an instruction decoding circuit, 16 is a branch determination circuit, 17 is an execution queue, and 18 is a selector for selecting instruction information from the execution queue 17. 19 is an instruction address adder, 20 is an instruction counter queue, 21 is a selector that selects an instruction counter from the instruction counter queue 20, 22 is a selector that selects an instruction counter from the instruction address adder 19 or the selector 21, and 23 is an instruction It is a counter register.

In this information processing device, instructions are processed by a pipeline processing method, where each instruction process forms a stream of a series of instructions, and in this stream, instruction processing is performed at an instruction read stage, a decode stage, and an operand read stage. The processing stage and the calculation execution stage are sequentially advanced and executed.

The instruction sequence 1 is stored in each instruction buffer 11 to 13 for each stream of instruction processing. Instruction read addresses corresponding to these instruction streams are stored in the instruction counter queue 20, respectively. The next instruction to be executed is selected by a control signal from the branch determination circuit 16, for example, selected from the first instruction buffer 11 by the selector 14, and supplied to the instruction decoding circuit 15 to be decoded. When the instruction decoding circuit 15 decodes the instruction,
The instruction length and a subsequent branch destination flag indicating whether the subsequent instruction is a branch destination instruction are stored in the execution waiting instruction queue 17, along with set-up information necessary when executing an operation of the instruction. This subsequent branch destination flag becomes logical tl I ++ when the decoded instruction is a branch instruction and the branch destination stream is subsequently processed. Furthermore, when a branch instruction is decoded, the branch destination instruction address is stored in the instruction counter queue 20.

When an instruction (instruction information) to be executed is selected by the selector 18 and enters the arithmetic execution stage, the instruction counter register 23 outputs an instruction counter. At this time,
When the subsequent branch destination flag is logic “O++,” the selector 22 is controlled by the subsequent branch destination flag 2d output from the execution waiting instruction queue 17 via the selector 18, and the instruction stored in the instruction counter register 23 is The instruction counter that is the output from the instruction address adder 19, which is the counter plus the instruction length 2b, is selected and set in the instruction counter register 23.On the other hand, the subsequent branch destination flag is set to logic II.
In the case of I++, the selector 22 is controlled to select the instruction counter outputted from the instruction counter queue 20 via the selector 21, and to select the instruction counter output from the instruction counter register 23.
Set to .

Next, we will specifically explain the instruction processing operation in such an information processing device, taking as an example a case in which a sequence of instructions including a branch instruction is executed, and a stream corresponding to the instruction processing is generated and the instruction processing is performed. Explain how it works.

FIG. 2 is a diagram showing an example of an instruction stream for explaining the instruction processing operation of the information processing apparatus shown in FIG. When an information processing device executes instruction processing of a sequence of instructions, it generates a stream of instruction processing and executes the instruction processing by pipeline processing. First, a stream of instructions to be executed is stored in the first instruction buffer 11, and an instruction counter is set in the instruction counter register 23. As a result, the first stream #0, which becomes the main stream, is generated,
Instruction processing of an instruction sequence is executed by pipeline processing. The instruction processing 24 of stream #0 progresses and branch instruction 25
When this occurs, the branch instruction 25 generates stream #1 for the instruction processing 26 at the branch destination. For this reason, the second instruction buffer 12 stores the instructions of the branch destination instruction sequence.
is secured and the branch destination instruction address is set in the instruction counter queue 20a.

Assuming that the branch instruction 25 is determined by the branch determination circuit 16 to be a branch before the instruction is executed in the operation execution stage of pipeline processing, the instruction processing for advance control performed in the pipeline processing is performed in stream #1. Move to. Then, the first instruction buffer 11 is released. From the determination result of branch establishment for the branch instruction 25, the instruction following the branch instruction 25 is the branch destination instruction, so the instruction information from the instruction decoding circuit 15 is stored in the execution waiting instruction queue 1.
7, the subsequent branch destination flag indicating that the subsequent instruction is the branch destination is stored in the execution waiting instruction queue 17 as logic "1". As a result, the instruction processing shifts to stream #1 and proceeds to instruction processing 26. Instruction processing 2
When 6 advances, a branch instruction 27 appears. In this case as well, do the same as in the case of branch instruction 25.

An instruction buffer is prepared. For example, the third instruction buffer 13 is secured as the instruction buffer to be prepared, and the branch instruction address is set in the instruction counter queue 20b. As a result, branch destination stream #2 is generated,
Instruction processing 28a proceeds.

If a branch determination cannot be made immediately in the processing of the branch instruction 27, instruction processing 28b of the non-branched stream is proceeded at the same time. Instruction processing 2 for this non-branching stream
8b, when the branch instruction 29 appears again in stream #1, a new stream for processing the branch destination instruction is generated in the same way as described above. At this time, since the first instruction buffer 11 has already been released, decoding of the branch instruction 29 is not inhibited, the first instruction buffer 11 is secured, and the branch instruction address is set in the instruction counter queue 20c. . This results in
Instruction processing 30 proceeds with stream #0. Further, when the branch instruction 25 enters the arithmetic execution stage, the subsequent branch destination flag indicating that the instruction following the branch instruction 25 is a branch destination instruction is logical rt I I+, so the selector 22 selects the selector 21 The side of the output is selected.

As a result, the value of the instruction counter queue 20a is set in the instruction counter register 23.

Processing proceeds based on the instruction counter at that time.

In this way, the instruction counter queue 2 serves as an address buffer for storing read addresses of a stream of instructions.
0, and by controlling this instruction counter queue 20 independently of each instruction buffer 11 to 13, if a 1 branch decision is made immediately, the instruction buffer is released without waiting for the arithmetic execution stage of the branch instruction. can do.

Therefore, even when branch instructions appear consecutively, the flow of pipeline processing is not disrupted, and processing speed can be increased.

The main parts of the information processing apparatus according to this embodiment can be summarized as follows.

(1) In the initial operation, the selector 22 selects the main stream instruction successive address and stores it in the instruction counter register 23.

(2) When an instruction other than a branch instruction is executed.

An instruction address adder 19 adds the instruction counter and the instruction length, determines the next instruction address following the instruction, and outputs it as an instruction counter.

At this time, the output of the instruction address adder 19 is selected by the selector 22 and stored in the instruction counter register 23 as a continuous next instruction address.

(3) When a branch destination stream of a branch instruction is read, the read addresses are stored in the instruction counter queue 20 in order. When a branch instruction is executed, consecutive next instruction addresses are determined and output, and at the same time, the instruction address of the branch destination stream is selected by the selector 21 and output as an instruction counter. When it is determined that the branch is established by executing the branch instruction, the output of the selector 21 is selected by the selector 22, and the branch destination instruction address is stored in the instruction counter register 23.

(4) This allows the instruction buffer to be released without waiting for the arithmetic execution stage of the branch instruction. Therefore, even when branch instructions appear consecutively, the flow of pipeline processing is not disrupted, and processing speed can be increased.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the present invention, the instruction counter can be obtained independently of the control of the instruction buffer, so the instruction buffer that is no longer needed due to branch judgment can be immediately released, and the branch destination of the subsequent branch instruction can be Stream reading becomes possible, and branch instruction processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a pipeline processing type information processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the instruction processing operation of the information processing device shown in FIG. FIG. 3 is a diagram illustrating an example instruction stream. FIG. 3 is a block diagram showing the main parts of an example of a conventional pipeline processing type information processing device, and FIG. 4 is an example of an instruction stream for explaining the instruction processing operation of the information processing device of FIG. 3. FIG. In the figure, 11.31...first instruction buffer, 12.3
2...Second instruction buffer, 13.33...Third instruction buffer, 14.18.21.22.34.38.
40.41.42.46...Selector, 15.35.
...Instruction decoding circuit, 16.36... Branch judgment circuit, 17.37... Execution waiting instruction queue, 19°39.
. . . instruction address adder, 20 . . . instruction counter cue, 23 . . . instruction counter register. Figure 1

Claims (1)

[Scope of Claims] 1. In an information processing device using a pipeline processing method, each processing stage of instruction reading, decoding, operand reading, and execution is performed sequentially, and processing for each instruction is performed in an overlapping manner. Information characterized in that it has a plurality of instruction buffers that store a series of instructions as a stream, and an address buffer that holds an instruction read address for each stream and can be controlled independently of the instruction buffers. Processing equipment. 2. In a pipeline processing information processing device that sequentially performs the processing stages of instruction reading, decoding, operand reading, and execution, and overlaps the processing for each instruction, a series of instructions to be processed is processed. A plurality of instruction buffers that store instructions as streams, an address buffer that holds instruction read addresses for each stream and that can be controlled independently of the instruction buffers, and The first step is to find the instruction read address of the stream from the instruction length.
a control means; a second control means for determining an instruction read address of a branch destination stream when a branch instruction is executed;
When a branch instruction is determined, a third control means releases the instruction buffer that is no longer needed before determining a continuous next instruction address or a branch address, and enables storing a subsequent branch destination stream in the instruction buffer. An information processing device comprising: