JPS6023378B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly, to an information processing device that processes a plurality of instructions in an overlapping manner, and relates to speed-up processing of branch instructions in which a branch is taken or not taken depending on a comparison result. It is something.

FIG. 1 shows a schematic configuration of an information processing device, in which 1 is an instruction unit (1 unit) that decodes instructions;
is a storage control unit (SC unit) including storage
, 3 is an arithmetic unit (E unit) that executes arithmetic operations on operands specified by instructions.

When unit 1 reads an instruction from storage, it sends data and control information necessary for executing the instruction to E unit 3.

If the instruction is a branch instruction, or if the operand required to execute the instruction is a storage operand, 1 unit 1 issues a request to SC unit 2, and in the former case, the branch destination instructions are sent to 1 unit 1, In the latter case, necessary data is sent to the E unit 3. When the E unit 3 receives data and control information necessary for executing an instruction from the 1 unit 1 or the SC unit 2, it executes the operation specified by the instruction, stores the operation result in a given register or storage, and executes the instruction. Terminate. As is well known, the operating time of unit 1 and SC unit 2 is longer than the operating time of E unit 3 when executing an instruction.

This is because the access time for storage operands is longer than the calculation speed. Therefore, in high-speed processing devices, processing performance is improved by implementing so-called pipeline control in which multiple instructions are processed in an overlapping manner. FIG. 2 is a time chart showing a case in which general instructions other than branch instructions are consecutively executed under pipeline control, assuming that a storage request requires three times the calculation time.

In FIG. 2, the horizontal axis shows the machine cycle of the device, and the vertical axis shows the processing time of each unit in the device.
In this), D is address modification processing including instruction decoding,
A is the time for address conversion processing, L is the time for buffer storage or main storage read processing, and E is each time for instruction execution processing. Due to pipeline control, instruction a is the first
A storage operand read request is issued to the SC unit 2 in each cycle, the data is transferred to the E unit 3 at the end of the third cycle, and an operation is executed in the fourth cycle. Similarly, the storage operand of instruction b is read in the second to fourth cycles, and the operation is performed in the fifth cycle. Note that there are also instructions that require data such as general-purpose registers (GR) in addition to storage data as operands, and these can generally be read faster than storage data, but under general pipeline control, These data are also controlled to be sent to the E unit 3 during the same time period as the storage data. Now, let us consider the following branch instruction processing in such an information processing device.

The instruction format of this branch instruction is as shown in Figure 3, which adds the contents of GR indicated by the R field and the contents of the GR indicated by the R3 field, and adds the result to the GR indicated by the R field. Store. Then, the addition result is compared with the contents of the GR indicated by R3-1 when R3 indicates an even numbered GR, and when R3 indicates an odd numbered GR.
When it shows, compare it with the content of GR shown by R3,
If the addition result is smaller or equal, the process branches to the second operand address (the address obtained by adding the contents of GR specified by the & field and the contents of the ○2 field). When the addition result is larger, no branch is taken and the instruction following the branch instruction is executed. Further, contrary to the above, there is also a branch instruction in which a branch is executed when the addition result is larger, but not when the addition result is smaller or equal. Since both branch instructions have almost the same control, the former will be described in this section. The branch instruction shown in FIG. 3 is mainly used as follows.

Now, after storage address S, instruction groups a, b, c,
Assume that d, . . . ×, y, z, . . . are stored, and x is the branch instruction. The instruction group of instructions d to x after storage address S+3 is changed from the initial value m to the final value n by increment i.
When you want to repeatedly execute until , set the branch destination address of instruction x to S+3, and set the initial value m, R3 to the OR specified by the R field of instruction The increment i is stored in the even-numbered GR specified by the field (this is called GR2), and the final value n is stored in the GR specified by R31 (this is called GR3). As a result, the instruction d and subsequent instructions are executed, and in the instruction x, G
Add the content of RI and the content of OR2, and the result is (n+
i) is stored in GRI. If the result of this addition is less than or equal to the content (n) of GR3, a branch is made to the second operand address S+3 of instruction x, and instructions d and subsequent instructions are executed again. As a result, address S+3{(
Branches are performed {(n-m)/i} times, and instructions d to x are branched {(n-m)/i} times.
i} Executed eleven times. Branch instruction x is {(n-m)/i
}When executed for the eleventh time, the contents of GR1 are (n+i)
Therefore, no branch is taken and the next instructions y, z・
...is executed. Next, a conventional control system for the above-mentioned branch instruction will be explained with reference to FIGS. 4 and 5. FIG. 4 is a block diagram of the part necessary for controlling the branch instruction, and FIG. 5 is a time chart for explaining the operation. In Figure 5, a indicates the branch taken, b indicates the branch is not taken, x is the branch instruction, a, b, c, d are the branch target instruction group, and y is the instruction x.
shows the next instruction. In FIG. 4, a storage 101 stores instructions and operand data.

Instructions read from storage 101 are stored in instruction buffer register 102 or 103 through line 201. Instruction buffer registers 102 and 103 store a plurality of instructions, each storing a group of instructions currently being executed or a group of instructions to be branched to by a branch instruction. In the initial state, the currently executing instructions are in instruction buffer register 0.
If there is a branch instruction in the instruction group, the branch destination instruction group is stored in the instruction buffer register 103. Then, when the branch of the branch instruction is established, the instruction group stored in instruction buffer register 03 becomes the instruction group being executed, and if there is a branch instruction among them, the branch destination instruction group is stored in the instruction buffer register 03. 102. When one instruction is extracted from the instruction buffer register 102 or 103 on line 202 or 203, respectively (the configuration required for extraction control is not shown in the figure),
Lines 202, 203 depending on the value of flip-flop 104
One of them is selected by the select gate 106 and stored in the instruction register 07. That is, when the output line 204 of the flip-flop 104 is "0", the instruction on the line 202 is selected, and when the line 204 is "1", the instruction on the line 203 is selected and stored in the instruction register 107. Flip-flop 104 is initially set to "0". Assume now that the flip-flop 104 is "0" and a branch instruction x in the format shown in FIG. 3 is extracted from the instruction buffer register 02.

Once the instruction is stored in instruction register 107, the instruction code portion is input to instruction decoder 108 through line 205.
If the instruction stored in the instruction register 07 is a branch instruction, the instruction decoder 108 inverts the value of the flip-flop 104 through a line 210 and an inversion circuit 105. That is,
If it is "0", it is set to "1", and if it is "1", it is set to "0". In other words, as explained earlier, the branch instruction is mainly used to repeatedly execute a certain group of instructions multiple times, so the branch is more likely to be taken. Therefore, by predicting in advance that the branch will be taken and inverting the value of the flip-flop 104 (in this case, "1"), the fifth
As shown in the figure, as soon as the branch destination instruction a is read from the storage 101 and stored in the instruction buffer register 103, it is extracted from the branch destination instruction buffer register 103 and stored in the instruction register 107. That's what I do. The effect of predicting branch establishment will be discussed later. The instruction decoder 108 also sends a read request for the branch destination instruction to the storage control unit 10 through the line 211. At this time, control information indicating which of the instruction buffer registers 102 and 103 the instruction read from the storage 101 is to be stored is also sent to the line 211. In this case, branch instruction x is extracted from instruction buffer register 102, so branch destination instruction a is extracted from instruction buffer register 102.
3 is indicated by line 211. The & part of the branch instruction
As a result of selecting the one specified by the line 208 from the GR) group 109, the contents of the selected GR are added to the address adder 1.
It is input to the B input section of No. 14. R of instruction register 107
The third part is sent to select gate 112 through line 207, but for branch instruction x, select gate 11
The output of address adder 114 is set to "0", and "0" is input to the x input section of address adder 114. D of address adder 114
The D2 part of the instruction register 107 is input to the input part, and the data input to the B input part is added, and the result is shown on the line 21.
2 to the storage address register 115, and becomes the read address of the branch destination instruction. The R, part and R3 part of the instruction register 107 are respectively connected to the line 206.
, 207 to the instruction storage units 116 and 117. The above operations after the branch instruction is stored in the instruction register 107 are performed in the time period D of the first cycle in FIG.

When the storage control unit 10 receives the request to read the branch destination instruction, it starts reading the storage 101 .

As a result, the branch destination instruction a is read from the address specified by the storage address register 15, and is read out through the line 201, the instruction buffer register 103, and the select gate 106 in the time period D of the fourth cycle in FIG. The branch destination instruction a is stored in the instruction register 107 at the start point of the branch destination instruction a. On the other hand, the instruction storage units 116 and 117 store the branch instruction x at the start of the time period L of the third cycle in FIG.
The contents of R and R3 are set to GR read registers 19 and 12, and the GRs indicated by GR read registers 19 and 120 are selected from the GR group 109 by select gates 110 and 111, and the data is read. is output on lines 213 and 214.

The data on lines 213 and 214 are stored in the operation input registers 302 and 303 of the E' unit at the start of the time period E of the fourth cycle in FIG. calculation input registers 302 and 303
The arithmetic unit 304 adds the contents of and stores the result in the arithmetic output register 305. Also, the instruction storage section 117
The R3 part of the branch instruction x stored in
It is set to 07. When the content set in the register 307 is an even number, "1" is selected by the select gate 308, and when the content is odd, "0" is selected by the select gate 308, and the register 307 is
The contents of are added by an adder 309, set in a register 310, and sent to one unit through a line 215. 1
The unit converts the contents of line 215 to E in the fourth cycle of FIG.
is set in the GR read register 119 through the select gate 118 at the start of the time period, and the GR group 109
GR read register from among GR indicated by 19
is selected by the select gate 110, and the arithmetic input register 30 is selected at the start of the time period E of the fifth cycle in FIG.
Set to 2.

The other arithmetic input register 303 contains the result of the arithmetic operation in the fourth cycle of FIG. calculation output register 305 where the result) is stored.
The contents of are selected and set by the select gate 301. Then, in the fifth cycle of FIG. 5, the arithmetic input registers 302 and 303 are compared in magnitude (ie, subtracted) by the arithmetic unit 304. The result is the calculation output register 30
5, and the line 216 is set to E in the sixth cycle.
The signal is applied to the branch determination circuit 306 through the branch determination circuit 306. The branch judgment circuit 306 determines that the content of the calculation output register 305 is a positive value (0
It is determined whether the branch of the branch instruction x is taken or not depending on whether the value (including . Now, the result of adding R of branch instruction x and the contents of GR indicated by R3 is shown as R3 (when the contents of R3 part is an odd number) or R311 (when the contents of R3 part is an even number) In the case of a branch instruction that branches when the content of GR is less than or equal to the content of GR, the branch is established when the content of the arithmetic output register 305 is a positive value (including 0).

This means that the branch was predicted to take place in advance), so the output line 217 of the branch determination circuit 306 is not enabled, and
Thereafter, as shown in FIG. 5a, branch destination instructions a, b, . . .
... is processed. On the other hand, if the content of the calculation output register 305 is a negative value, the branch will not be taken, which contradicts the prediction. , the flip-flop 104 is inverted through the inverting circuit 105 and returned to its original state (in this case, it is set to "0"). Then, the instruction y following the branch instruction x is extracted from the instruction buffer register 102 and stored in the instruction register 107 through the select gate 106 at the start point D of the eighth cycle in FIG. 5b. Although not shown in FIG. 4, the branch destination instructions a to d are invalidated in the seventh cycle, as shown in FIG. 5b. The above is an explanation of the case where a branch of a branch instruction is predicted to be taken, but let me briefly explain the case where a branch is predicted not to be taken.
Figure 6 shows the time and processing time when branch failure is predicted and processed.
This is a chart in which a is a chart when a branch is taken, and b is a chart when a branch is not taken.

As is clear from a comparison with FIG. 5, when branch b is not taken, the instruction y to be processed next to the branch instruction x can be executed four cycles earlier in the case of the branch failure prediction shown in FIG. However, when branch a is taken, instruction a, which is processed next to branch instruction x, is 4 cycles later than in the branch failure prediction shown in FIG. As described above, the branch instruction is more likely to result in a branch being taken, so a method that predicts the branch taking is generally adopted, which increases the processing speed when the branch is taken. By the way, when processing a branch instruction in the format shown in Figure 3, the follower is the contents of the general-purpose register specified by the R, part of the instruction and the general-purpose register specified by the R3 part, as shown in Figure 5. The contents are added in the first cycle of the time period of E, and the result and the contents of the general-purpose register of R3 or R31 are added to the contents of the general-purpose register of E in the second
Comparisons were made between cycles, and branching was determined in the third cycle of E based on the results.

That is, in processing the branch instruction, all operations necessary for branch determination are performed in the calculation unit. For this reason,
It has the disadvantage that it is slow to determine whether a branch is taken or not, and the processing speed when branch prediction fails is slow. An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to provide an information processing apparatus that has the effect of improving the processing speed when a branch is not taken without reducing the processing speed when the branch is taken. It is about providing.

Therefore, the feature of this invention is that it has a register that stores the R part of the branch instruction, sets the time period D as two machine cycles, and compares the data at the same time as transferring the data to the arithmetic unit. , which improves the processing speed when the branch instruction is not taken.

Hereinafter, one embodiment of the present invention will be described in detail using the drawings. FIG. 7 is a block diagram of an embodiment of the present invention;
FIG. 8 is a time chart for explaining the operation. In FIG. 8, a shows the state when the branch is taken, and b shows the state when the branch is not taken. Since the configuration of FIG. 7 is almost the same as that of FIG. 4, only the parts that are different from FIG. 4 will be explained.

In FIG. 7, R, register 29, and comparison circuit 130 are added according to the present invention. R, register 2
9 input is R.9 of instruction register 07. The output is connected to B2 of the instruction register 07. Select gates 110 and 11 are connected to the input of the comparison circuit 130.
1 output lines 213 and 214 are connected, and the output thereof is connected to a branch determination circuit 131. The operation of the branch determination circuit 131 is the same as that of the branch determination circuit 306 in FIG. 4, but the branch determination circuit 306 in FIG. 4 is located in the E unit, whereas the branch determination circuit 131 in FIG. Located in 1 unit. Select gate 121 and adder 122 in FIG.
, address register 123, address stack registers 124-126, select gate 127, setup address register 28 and line 218 are not shown in FIG. These are not related to the operation of the instruction), are necessary for processing other instructions, and are not particularly added by the present invention. The instruction storage unit 116, select gate 118, GR read register 120, and E unit 301-305, 307-31 shown in FIG. 4 are not shown in FIG. 7 because they are not particularly related to the operation of the present invention. Now, assume that the flip-flop 104 is "0".

When the branch instruction x is extracted from the instruction buffer register 102 and stored in the instruction register 107 at the start point D of the first cycle in FIG. Ru. The instruction decoder 108 sends a read request for the branch destination instruction to the storage control unit 10 through the line 211, as in the conventional case. Control information indicating which of the instruction buffer registers 102 and 103 the branch destination instruction is to be stored in is also sent to the line 211. The branch destination address is calculated by the address adder 114 using the B2 part and D2 part of the instruction register 107, and is transferred to the storage address register 115. instruction register 0
The R section of 7 is stored in the R register 129. The above operation is performed in the time period D of the first cycle in FIG. Next, the contents of the R register 29 are set in the B section of the instruction register 07 at the start of the second cycle, thereby causing the select gate 113 to select one of the general purpose registers 109. Also, R2 of instruction register 07
Select one of the general-purpose register group 109 by the section.
The selection is made at gate 112. The contents of the general-purpose registers selected by select gates 112 and 113 are input to the x and B inputs of the address adder, respectively. “0” is input to the ◯ input section of the address adder 114.
As a result, the contents of the general-purpose register indicated by the R, section of the branch instruction and the contents of the general-purpose register indicated by the R3 section are added using the address adder 114, and the result is set in the address register 23. The contents set in address register 123 are stored in one of address stack registers 124-126 during time period A of the third cycle. Although three address stacks are shown in FIG. 7, this is to facilitate processing in the pipeline control system, and the number does not necessarily have to be three. At the end of D of the second cycle, the instruction decoder 108 inverts the flip-flop 104 through the output line 210 and the inversion circuit 105, and sets it to "1".

Also, during the time period marked with ○ in the second cycle, the instruction register 07
The R3 part is sent to the instruction storage unit 117. Then, in the time period A of the third cycle, the R3 part is input to the adder 122, and the other input of the adder 122 is set to "1" when the value of R3 is an even number, and "0" when it is an odd number. ” is selected by the selector gate 121 and input. The result is set in the GR issue register 119 at the start of L of the fourth cycle. Also at this time, address stack register 1
The above contents stored in one of the addresses 24 to 126 are selected by the select gate 127 and set in the setup address register 128. Then, in the time period L of the fourth cycle, the contents of the general-purpose register indicated by the GR input register 19 are selected by the select gate 110 and output on the line 213. Also, set up
The contents of address register 28 are output on line 214 through line 218 and select gate 111. The data on lines 213 and 214 are then transferred to the E unit at the end of L of the fourth cycle. At this time, line 213
The data on the lines 214 and 214 are connected to respective inputs of the comparison circuit 130, and the magnitudes of both data are compared, and the result is given to the branch determination circuit 131. The branch determination circuit 131 determines whether the branch of the branch instruction is established or not based on the output of the comparison circuit 130, and when the branch is not established, the output line 2
17 is valid at the start of the fifth cycle. When the branch is taken, that is, when the prediction is correct, the output line 217 of the branch determination circuit 131 is not made valid, and the branch destination instructions a, b, . . . are processed as shown in FIG. 8a. When the branch fails,
That is, when prediction fails, the output line 217 of the branch judgment circuit 131 is enabled at the start of the fifth cycle as shown in FIG.
is reversed and returned to its original state "0". Then, the instruction y following the branch instruction x is extracted from the instruction buffer register 102 and stored in the instruction register 07 at the start point D of the seventh cycle in FIG. 8b. Also, branch destination instructions a to c
are respectively invalidated during the sixth cycle. As explained above, the present invention is based on the G
The content of R and the content of GR indicated in the R3 section are added by an address adder, and the addition result is added to R3 or R31.
Since the content of the GR in the subroutine is sent to the E unit and simultaneously compared, it is determined whether the branch is taken or not. Therefore, all the above additions and comparisons of the subordinates are performed in the E unit to determine whether the branch is taken or not. Compared to the case
This has the effect that branch determination can be made one cycle earlier, thereby improving processing speed when a branch is not taken.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of an information processing device, FIG. 2 is a diagram showing a time chart of general instructions under pipeline control, and FIG. 3 is a diagram showing the instruction format of a branch instruction targeted by the present invention. , FIG. 4 is a block diagram of the part necessary to explain the operation of the follower of the branch instruction in FIG. 3, and FIGS.
4 is a diagram showing a time chart for explaining the operation of FIG. 4, FIG. 7 is a diagram showing an embodiment of the present invention, and FIG. 8 is a time chart for explaining the operation of FIG. 7. FIG. 100...Storage control unit, 101...
... Storage, 102, 103 ... Instruction buffer register, 104 ... Flip-flop, 10
5...Inversion circuit, 106, 110 to 113, 121
, 127...Select gate, 107...
・Instruction register, 108...Instruction decoder, 10
9...General-purpose register, 114...Address adder, 115...Storage address register, 117...Instruction storage section, 119...G
F read register, 122... Adder, 12
3...Address register, 124-126...Address stack register, 128...Setup register
Address register, 129...R, register, 130
... Comparison circuit, 131 ... Branch judgment circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1 Equipped with a plurality of instruction buffer registers each storing a plurality of instruction groups read from a storage device, and sequentially cutting out instructions from the selected instruction buffer register to the instruction register to overlap the plurality of instructions. In an information processing device that processes an instruction, the contents of the general-purpose register indicated by the first field of the instruction and the contents of the general-purpose register indicated by the second field (the first and second fields both form the first operand part) are The result of the addition is compared with the general-purpose register indicated by the contents of the second field or the contents of the general-purpose register whose number is +1, and based on the result, the second operand
In order to process a branch instruction that branches to an address, a register is provided to temporarily store the first field of the branch instruction. When it is decoded that the instruction extracted from the instruction register (referred to as a register) is the branch instruction, first, in the first cycle, a group of branch destination instructions at the second operand address of the branch instruction is read from the storage device. instruction buffer registers other than the first instruction buffer register (hereinafter referred to as the second instruction buffer register)
At the same time, the first field of the branch instruction is stored in the register (referred to as an instruction buffer register), and the contents of the register are set in the second operand field of the instruction register in the next second cycle. do,
The contents of the general-purpose register indicated by the operand field section and the contents of the general-purpose register indicated by the second field are added, the addition result is stored in the operand address register, and from the third cycle onward, the contents of the general-purpose register indicated by the second field are added. When the branch destination instructions in the second instruction buffer register are made valid and the branch destination instructions are read from the storage device and stored in the second instruction buffer register, instructions are transferred one after another from the second instruction buffer register to the instruction register. and processes the branch destination instruction, and then extracts the general-purpose register indicated by the addition result stored in the operand address register and the contents of the second field of the branch instruction, or the contents of the general-purpose register whose number is +1. is transferred to the arithmetic unit, and the contents are compared to determine whether the branch is taken or not, and when the branch is taken, the processing of the branch destination instructions in the second instruction buffer register continues to be valid, and the branch is executed. An information processing device characterized in that, when the instruction is not established, the instruction group in the first instruction buffer register is processed by making it valid again.