JPS62145430A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the processing time of program address revision by providing a means modifying the content of a register storing a program address depending on the stored control information and generating the address of an instruction executed next. CONSTITUTION:Stored operation designation information is decoded by an instruction decoder 50, and whether or not the information is an instruction of plural word lengths is discriminated, a control signal 501 is generated and stored in a word length register 110 and the information representing how many word lengths the instruction starting the processing has is stored in the register 110. Thus, the head address information of the instruction word executed next is generated by adding the storage information of the register 110 to the content of the program counter 70 being the instruction word head address in the process of execution. Further, the content of the counter 70 and the register 110 is transferred to an operation circuit 60 in the timing optimum in the instruction processing sequence to operate the next instruction address, the result of operation is stored in the counter 70 to apply the revision processing of the program address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a stored program control data processing device, and more particularly to a mechanism for updating program address values in accordance with the word length of an instruction being executed.

[Technology background]

A stored program controlled data processing device specifies a memory address using the contents of a counter that holds program address information, reads an instruction word from there, decodes the instruction word, and executes the corresponding data transfer, arithmetic operation, etc. are doing.

The factors that govern the processing speed of the device are the time required to read instructions (hereinafter referred to as instruction fetch) and the time required to read and process data.
This is the memory access time for writing. Therefore, when processing internal register information of a data processing device, the instruction word to be executed next is fetched in advance from the memory where processing data is not accessed, thereby improving the efficiency of memory access and increasing the processing speed. Thousands of so-called advance orders are being used.

In the above-mentioned speed-up method, the previously fetched instruction word is stored in a buffer register, and predetermined processing such as instruction decoding, data transfer, arithmetic operation, etc. is executed based on the instruction word in the buffer. However, if instructions that access memory as processing data are frequently executed, the previous method cannot fetch the instruction word from memory, so it is possible to pre-fetch the instruction word depending on the type of instruction to be executed and the program. state changes. In order to improve the efficiency of memory access and achieve high-speed processing without being affected by this state change, it is effective to increase the buffer storage capacity for pre-fetched instruction words. A device has been proposed.

In a data processing device equipped with an instruction buffer having a capacity of multiple words, a pointer (hereinafter referred to as a 7-etch pointer) that specifies a memory address from which an instruction word is read out and a pointer that specifies a memory address from which an instruction word is read out corresponds to the input and output of the buffer storage, and a pointer that specifies the memory address for reading out an instruction word, and a It is customary to include a class 2a hardware register including a counter (hereinafter referred to as a program counter) that holds addresses.

The former 7-etch pointer control is linked to the operation of prefetching an instruction word and storing it in an instruction buffer, and updates the address value of the instruction to be fetched next, and can be realized by a simple logic circuit. However, the latter program counter control involves updating counter information corresponding to the instruction word length, loading a branch address value when executing a branch instruction,
Complex processing is required that cannot be performed by simple addition processing, such as saving to the stack and post-closing in subroutine call and return instructions.

[Conventional technology and problems]

The block configuration of a basic seven-etch data processing apparatus is shown in FIG. 1 and will be described. The apparatus shown in FIG. 1 includes a memory 20 for storing programs and processing data, an instruction register 40 for holding commands to be executed, and a control signal 50 for decoding the commands in the command register 4o to each part of the apparatus.
An instruction decoder 50 that generates 0, an arithmetic circuit 60 that processes arithmetic and logical operations, a program counter 70 that holds program addresses, and a general-purpose register 80 that stores processing data such as data transfer and calculations and is used for multiple purposes. , a temporary register 90 that temporarily stores processing data, etc.
In addition, it consists of a fetch pointer 10 that holds the 7th and 7th fetch address for controlling the preceding 7th fetch, and an instruction buffer i0 that stores the instruction word information of the preceding fetch, and is connected between each part of the device via the data bus 100. Transfer data.

In general, in data processing devices, general-purpose register manipulation instructions have advantages over memory manipulation instructions, such as: (1) more types, (11) shorter instruction word length, and (11) shorter processing time. It is often used to process data.

When a general-purpose register manipulation instruction is executed, data is transferred between the arithmetic circuit 60 and the general-purpose register 80 via the data bus 100, the memory 20 is accessed, and the input/output line 202 is accessed.
Memory data is not transferred via the memory 20, and the instruction word can be read out to the data line 201 and stored in the instruction buffer 30 by addressing the memory 20 with the fetch pointer IO, and the execution of the instruction and the subsequent 7 etches of the instruction can be executed. The command processing time of the data processing device can be shortened by performing parallel processing.

If the storage capacity of the instruction buffer 30 is increased, the preceding 7 etchings will work effectively and the instruction buffer 30 will be able to maintain a state in which a sufficient number of commands to be executed are stored. However, in this state, memory 20. Arithmetic circuit 60, program counter 70, general purpose register 80. The execution time of the instruction processing sequence that performs data transfer and arithmetic operations between various parts of the device such as the temporary register 90 determines the instruction processing time.If a mechanism was provided that could shorten the instruction processing sequence. Instruction processing time can be further reduced.

Here, the instruction processing sequence is classified into execution of processing defined as an instruction function such as data transfer and calculation, and updating of a program address linked to instruction execution. The explanation will focus on address control.

In addition to word-length instructions that only specify an operating code, the instruction words of a data processing device include multiple-word instructions that include processing constants and address specification parts, and in both cases, the instructions are read one word at a time from the instruction buffer and executed. ing.

In the device shown in FIG. 1, the first word of the instruction, the operation specification part, is transferred from the instruction buffer 30 via the data line 301 and stored in the instruction register 40, and the processing constants and other words after the second word are transferred. The address designation part is read from the instruction buffer 30 and transferred to the temporary register 90 and memory 20 via the data line 302 and data bus 100, respectively. Here, in synchronization with reading from the instruction buffer 30, 1) the program counter 7 is read via the data bus 100;
0 is transferred to the arithmetic circuit 60, and Il) the arithmetic circuit 60
111) The operation result is transferred via the data bus 100 and stored in the program counter 70 to perform a series of program address update processing. .

In 1) and 111) of the address update processing, transfer is performed via the data bus 100, and during this time, instruction word information cannot be transferred from the instruction buffer 30 to the memory 20 or the tempo tree register 90, and the instruction information is transferred for different periods. As a result, the processing sequence and its processing time increase.

Therefore, if the number of times of processing for updating the program address can be reduced, the instruction processing time can be shortened, which is particularly effective for instructions with a plurality of word lengths.

Next, program address control in a call instruction for subroutine processing will be explained by showing a processing sequence below.

1) The first word of the instruction is transferred from the instruction buffer 30 to the instruction register 40, the instruction decoder 50 decodes it as a subroutine call instruction, and the contents of program callantaff 0 are transferred to the address corresponding to the second candy of the instruction. Update to value.

11) Transfer the second word of the instruction indicating the subroutine address from the instruction buffer 30 to the temporary register 90, and update the contents of the program counter 70 to the start address value of the next instruction word.

111) Store program color/in the stack area of memory 20.
The contents are transferred and stored, and saved in preparation for return from the subroutine.

IV) Transfer the contents of the temporary register 90 to the program counters 70 and 7 and pointer 10 and start fetching instructions of the subroutine program.

Here, if the contents of the program counter 70 can be updated to the next instruction word address value before the processing sequence it),
The program counter saving process of processing sequence 111) can be performed while leaving the second word of the instruction in the instruction buffer.

Furthermore, in processing sequence IV), it becomes possible to transfer the second word of the instruction, which is a subroutine address, from the instruction buffer, and the processing sequence 11) and the temporary register 90' become unnecessary.

[Purpose of the invention]

The present invention provides a mechanism that can update program counter information corresponding to the instruction word length in a short time at the optimal timing of the instruction processing sequence. In particular, the goal is to realize a high-speed data processing device by reducing instruction processing time, and to reduce the hardware required for instruction execution by holding information used in instruction processing in an instruction buffer until the optimal timing. The purpose is

[Structure of the invention]

In the present invention, it is determined whether the instruction information for the word length required at the start of instruction processing is stored in the buffer storage register, and the control information of the instruction that specifies the buffer storage determination is stored. It is characterized by modifying the contents of the register that holds the program address and generating the address value of the next instruction to be executed.

This is based on the knowledge that in a data processing device that fetches an instruction in advance and stores it in a buffer register, it is determined whether or not there is valid instruction information in the buffer register in order to determine whether the instruction can be processed.

[Embodiments of the invention]

FIG. 2 shows a block diagram of a data processing apparatus according to an embodiment of the present invention, and will be described in detail. In FIG. 2, a fetch pointer 10, a memory 20, an instruction buffer 30 . Instruction register 40. Instruction decoder 50, arithmetic circuit 60, program counter 70°, general-purpose register 80. data bus 1
00 and control key number 500 are the same as those in the basic device shown in FIG. 1, so a detailed explanation will be omitted and the explanation will focus on the relationship with command processing.

First, when the instruction processing ends, the instruction decoder 50 generates a control signal 500 indicating the end of the instruction processing to inform the instruction buffer 30, and the instruction decoder 50 outputs the control signal 500 indicating the end of the instruction processing.

The operation of the instruction word to be executed next from the file 30.

instruction register 40 via data line 301.
Store it in Next, the stored operation designation information is decoded by the instruction decoder 50 to determine whether it is an instruction with multiple chain lengths including processing constants and address designation parts,
A control signal 501 is generated to instruct determination as to whether all of the instruction words are stored in the instruction buffer, and the instruction buffer 3
The determination result signal 303 from 0 is determined to determine subsequent control.

If it is confirmed in the above judgment that the information required for processing execution is stored in the instruction buffer 30, the instruction decoder 50 sends a control signal corresponding to the processing of the instruction to be executed to each part of the data processing device. 500 to start processing instructions such as data transfer and calculation. If the instruction buffer 30 does not store all the instruction information, such as when there has been frequent processing data access to the memory 20 in previous instruction processing, and if this state is detected by the determination result signal 303, the instruction processing is performed. order 7 withholding the start of
Continuing the construction operation waits until the necessary command information is collected. In this data processing device, the control signal 501 instructing the determination is stored in the word length register 110 at the same time as the buffer storage state is determined, and information indicating how long the instruction to start processing is is stored in the word length register 110. long register 110
will be held. Therefore, by adding the information stored in the word length register 110 to the contents of the program counter 20, which is the instruction word start address value in the execution process, the start address information of the next instruction word to be executed can be generated. Furthermore, the program counter 20 and word length register 110 are
is transferred to the arithmetic circuit 6o via the data bus 100 to calculate the next instruction address, and the result is stored in the program counter 20 to update the program address.

Note that the transfer and arithmetic operation of data stored in the memory 20 and the general-purpose register 800, which are defined as instruction functions, are processed by transferring data to and from the arithmetic circuit 60, as in the first device.

When the operation specification information of the instruction word is transferred to the instruction register 40 and 15! in the instruction word! When the logical constants and addressing information are derived via data line 3023-, the information stored in instruction buffer 30 becomes unreliable.

In the embodiment shown in FIG. 2, when the above-mentioned conditions are satisfied during the execution process, the storage status of unnecessary information is cleared and the storage area is set to empty, and the instruction buffer 30 has an empty buffer storage area. The empty area is filled up and the buffer storage information is arranged, and at the same time, the advance fetch control signal 30 is activated.
4 to notify the fetch pointer l0IC. In the data processing device of the embodiment, the preceding seven-step control signal 304 indicating that there is space in the buffer storage area is output, and there is no processing data access to the memo IJ 20 from the control signal 500 generated by the instruction decoder 50. When this is detected, the memory 20 is addressed by the pointer 10, the instruction word is read out and stored in the instruction buffer 30, and the contents of the fetch pointer 10 are updated to the address value at which the next instruction should be fetched.

FIG. 3 shows the circuit configurations of the instruction buffer circuit 30 and instruction register 400 in the embodiment of the present invention shown in FIG. Components in FIG. 3 that are the same as those in FIG. 2 are given the same numbers. The circuit shown in FIG. 3 also includes an instruction register 40 and is capable of storing four-word instruction information, and registers 311, 312, and 313 buffer instruction words and shift them in a first-in first-out manner. Furi, pflop 321, 322, 32
3゜324 holds the status of whether or not valid instruction information is stored in the corresponding registers 311, 312゜313 and instruction register 40, respectively, and the set state indicates that valid information is stored in the corresponding register. The reset state indicates an empty state in which no valid information is stored. Gate circuit 331, 332, 333, 3
34 controls the 7-first-in/7-first-out shift when the instruction buffer, buffer write signal 341, buffer read signal 342, and instruction processing end signal 343 become active. The status selection circuit 350 selects any one of signals 321 to 324 indicating the states of the registers 311 to 313 and the instruction register 40 according to the specification of the control signal 501 generated by the instruction decoder 50, and determines the buffer state. It is transmitted to the instruction decoder 50 as a determination signal 303. When the status selection circuit 350 selects the 7-lip flop in the reset state, a determination result signal 303 indicating that there is no valid information in the corresponding register is generated.
is transmitted, the data processing device interrupts and suspends the instruction processing, and sets 79. Rough 0. If the option is selected, a determination result signal 303 indicating that there is valid information is transmitted;
Continue instruction processing.

First, an instruction processing end signal 343 is sent from the instruction decoder 50.
When the 70 lip 324 is generated, the 7 lip 70 tube 324 is reset and the corresponding instruction register 40 becomes empty. The gate circuit 334 determines that the instruction register 40 is empty and valid information is stored in the register 313 based on the values of FRI, PUFRO, and PUFRO 323 and 324, and transfers the stored information of the register 313 to the data line. 301 to the instruction register 40. At the same time as this operation, the flip 70 knob 314 corresponding to the instruction register 40 is set, and the register 313
The corresponding flop 313Fi resetting is done,
The instruction register 4o is in a state where no valid information is stored, and the register 313 is in a state where no valid information is stored, that is, it is in an empty state. When the register 313 becomes empty, the adjacent register 312
The gate circuit 332 determines whether valid information is stored in the register 313 and transfers the information to the register 313.
is in a state where valid information is stored (the flip-flop 323 is set) and the register 312 is in an empty state (the flip-flop 323 is set).
2 is reset)K.

Similarly, the states of the adjacent registers 312 and 311 are determined by the gate circuit 331, and the information of the register 311 is transferred to the register 3.
12 and sets the status of 7 lip flops and 321 and 322.

As a result of performing the above operations one after another between adjacent registers, the register 311 becomes empty (free).

The signal 304 indicating this state is transmitted to the 7 etch pointer 10 to prompt the instruction 7 etch, the instruction word is read from the memory 20, and the valid information is stored in the registers 311 to 313. control to maintain the current state.

In the process of processing the command, the second Wr! When using the subsequent information, that is, the information stored in the instruction buffers 311 to 313 as processing constants or addressing information, the instruction decoder 50 generates a buffer read signal 342 and the information in the register 313 is read as data via the data a 302. The bus 100 is routed to the bus 100. At the same time, the flip-flop 323 is reset through the gate circuit 333 based on the buffer read signal 342, and the register 313 is set to an empty state.

After that, as mentioned above, the presence or absence of valid information is determined between adjacent registers, information is transferred, and the data is transferred.

Controls the alignment of file memories.

To determine whether fetching of a multi-word instruction has been completed, the instruction decoder 50 generates a control signal 501 to instruct the status selection circuit 350 based on the operation designation information of the instruction decoder 40, and performs the process as shown in the table below. This is done by selecting the flip-flop signal shown and determining the state of the selected flip-flop.

The registers 311 to 313 and the instruction register 40 are always controlled to be filled with register information when an empty state occurs in the register in the middle.

To determine that valid information is stored in the register 311 by selecting the program 321, the register 312,
It can be determined that valid information is also stored in the register 313 and the instruction register 40, and it can be determined that all four-word long instructions have been fetched. Similarly, 7 lippflo,
3 @ corresponding to the selection of 322, 323, 324, respectively.
It is possible to determine the completion of 7 etches of long instructions, 2-word long instructions, and 1-word long instructions.

Here, the control signal 501 is a multi-bit coded signal, and the length of the judgment word for fetch completion is determined in accordance with the code. In other words, the control signal 501 is a signal indicating the instruction word length, and in the embodiment of FIG. 2, this information is stored in the word length register 110, the stored information is added to the contents of the program counter 70, and the next execution is performed. Generates the start address value of the instruction to be executed.

FIG. 4 shows the circuit configuration of the word length register 1100 of the embodiment. The word length register 110 inputs the control signal 501-0.501-1, 501-2, which is 3-bit information, detects with the OR gate 401 that the control signal is not a no-operation state, and outputs the control signal. 501-0.
The child circuit 40 carries the values of 501-1 and 501-2, respectively.
2,403,404, and when the data processing device performs arithmetic operations for program address modification, the latch circuit 402
The output of the constant generation circuit 405 is added to the output of ~403 to generate data corresponding to the bit width of the address and sent to the data bus 100.

In the device of the embodiment, instructions with a length of 1 to 4 words are assumed, and the binary code of the control signal 501 is associated with the number of judgment word lengths. A constant O generated by a constant generation circuit 405 is added to the upper bits of the constant O to generate word length information for the ', t'th address modification.

〔Effect of the invention〕

As explained above, according to the present invention, the start address of the next instruction to be executed can be generated with one operation even if the instruction is i several words long, and the processing time for updating the program address can be shortened, resulting in high-speed processing. data processing equipment can be provided. moreover,
It is possible to update the program address at any timing during the instruction execution process, such as when the instruction word information is unused and stored in the buffer register, and the optimal processing sequence can be created, making it easier to execute the instruction. The required hardware can be reduced, and a data processing device with excellent cost performance can be provided.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a data processing device that performs basic advance 7-etch control, FIG. 2 is a block configuration diagram of a data processing device according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. A circuit diagram of the instruction buffer and instruction register in
FIG. 4 is a circuit diagram of a word length register in one embodiment of the present invention. lO...Fetch pointer, 20...
Memory, 30...Instruction buffer, 40...
...Instruction register, 50 ...Instruction decoder, 6
0... Arithmetic circuit, 70... Program counter, 8G... General purpose register, 90...
... Temporary register, 100 ... Data bus, 110 ... Word length register, 201, 2t
)2゜301.302...Data line, 303,
304,341°342.343...Signal line,
500,501,501-0.501-1,501-2
...Control signal line, 311°312.313...
...Register, 321, 322, 323゜324・
・・・7ritsugu70. Pu, 331, 332, 333
゜334...Gate circuit, 350...
Selection circuit, 4Q1...OR gate, 402,
403, 404... Latch circuit, 405...
...Constant generation circuit. yf51TiJ foil 2 fig. 3 fig. 4 fig. bu 4ρ/

Claims (1)

[Claims] In a data processing device equipped with a buffer register that reads and stores an instruction word prior to execution of an instruction under stored program control, necessary instruction word information is stored in the buffer register based on control information of the instruction to be executed. means for determining whether or not the program address is present; means for storing control information specifying the determination; and generating an address value for the next instruction to be executed by modifying the contents of a register holding a program address using the stored control information. 1. A data processing device comprising means for: