JPH02235175A - Scalar data fetching system for additional type vector processor - Google Patents

Abstract

PURPOSE:To execute the overlapped processing of a vector loading instruction and a scalar data loading instruction and to improve a processing speed by connecting two or more adders for calculating an operand address and executing the operation of the succeeding instructions in parallel. CONSTITUTION:A vector loading instruction is supplied from an instruction buffer 1 to an operand address adder 6 and an instruction decoder 8 through a DB 2 and an AB 3 to command the start of a normal sequence instruction. An instruction pipeline control unit 10 drives the adder 6 and controls a multiplexer 11 so as to selects its output. When a buffer miss is generated during the period of vector loading, the succeeding scalar instruction is supplied to an adder 7 and a decoder 9 through a PDB 4 and a PAB 5 to command the start of the preceding sequence instruction. The unit 10 starts the adder 7 and controls the multiplexer 11 so as to select the output of the adder 7. Consequently, the processing speed of the additional type vector processor can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a scalar data fetch method in an additive vector processing device that enables redundant processing of a vector data load instruction and a scalar data load instruction in a vector data processing device, In the scalar data fetch method in additive vector processing devices, which stores vector load data in the vector register of the vector processing unit via the scalar processing unit, the operand At least two adders are provided for address calculations, and while the scalar processing unit is executing a vector load using one adder, the address calculation for the subsequent scalar instruction is performed using the other adder, and the address calculation for the subsequent scalar instruction is performed using the other adder. During the interlock due to interruption, the address of the subsequent scalar instruction is issued from the other adder, and the subsequent scalar instruction is configured to be executed. [Industrial Application Field] The present invention relates to a scalar data fetching method in an additive vector processing device that enables redundant processing of vector data load instructions and scalar data load instructions in a vector data processing device. Vector data processing devices attempt to improve processing speed by redundantly processing not only vector instructions but also scalar instructions. The above-mentioned overlapped processing can be achieved using conventional technology in devices where vector processing units and scalar processing units can operate independently of each other, but it is not possible in devices that perform vector loads and stores via scalar processing units. , this type of vector processing device requires redundant processing of scalar instructions and vector instructions. The present invention is related to this field. [Prior Art] Conventionally, in devices that perform vector loads and stores via a scalar processing unit, subsequent scalar load instructions are executed after the vector loads and stores are completed. [Problems to be Solved by the Invention] As mentioned above, in the conventional additive type vector processing device, a scalar load instruction or an RX type (operation between a register and a word specified by an index-qualified address in main memory) is required. Or RS type (operation between register and main memory)
The scalar instructions and vector load/store instructions could not be processed redundantly, which caused problems in terms of processing speed. An object of the present invention is to enable redundant processing of vector data load instructions and scalar data load instructions, and to improve the processing speed of an additive vector processing device. [Means for Solving and Accomplishing the Problems] The present invention, as explained using the block circuit diagram illustrated in FIG. In a scalar data fetch method in an additive vector processing device, at least two adders 6 and 7 are provided for operand address calculation, and while the scalar processing unit is executing a vector load using one adder 6, The address of the subsequent scalar instruction is calculated by the other adder 7, and the address of the subsequent scalar instruction is issued from the other adder 7 during the interpolation due to interruption of vector loading, and the subsequent scalar instruction is executed. do.

[For production]

If the above-described method is used, it becomes possible to obtain the operand address of the subsequent scalar instruction using the other of the adders that perform two operand address operations, and the scalar instruction can be executed. If this scalar instruction can be executed, the next vector operation instruction can also be processed redundantly. [Embodiment] FIG. 1 shows a partial block circuit diagram of a processing device that performs a scalar data fetch method in an additive vector processing device as an embodiment of the present invention.

Instruction processing in the processing unit includes decoding (D), address calculation (^), arithmetic (El), and interrupt check (C).
, and register write (D, A, E, C1 in order)
and is executed according to the five states of W. First, for example, a vector load instruction is transferred from the instruction buffer 1 in which instruction data is stored to the D state instruction buffer (
DB) 2 and A-state instruction buffer (AB) 3
The input signal is supplied to the input of the operand address adder 6 and the instruction decoder 8 via the . The instruction pipeline control unit 10 includes S
CU (Storage Control Unit) Adders 6, 7 and address bus multiplexer 1 upon receiving signals from interlock signal, interrupt operation enable signal, move-in-end signal, and instruction decoders 8 and 9
Control 1. Then, when loading vectors, adder 6
is operated so that the output of the adder 6 is selected by the address bus multiplexer 11. In this manner, the operand address is calculated during vector loading, and the vector loading process, that is, data transfer from the buffer storage device of the scalar processing unit to the vector register of the vector processing unit, is executed.

If a buffer miss occurs during vector loading,
That is, when a condition occurs such as data supplied to the buffer storage device of the scalar processing unit is not being transferred, the SCU interlock signal is issued and the scalar instruction following the vector load is transferred to the preceding D-state instruction buffer (PDB). ) 4 and the preceding A state instruction buffer (
PAB) 5 to the operand address adder 7 and instruction decoder 9, and simultaneously commands the activation of the preceding sequence instruction. The instruction pipeline control unit 10 in this case operates the adder 7 and controls the address bus multiplexer 11 to select the output of the adder 7.

In this way, when a vector load, which is a normal sequence instruction, is interrupted, a scalar load instruction that should be executed after the vector load is completed is activated via the preceding instruction buffer, and the operand address is calculated by the adder 7. , scalar load processing is executed. Furthermore, vector operation instructions following a scalar load can be executed continuously. The above-mentioned move-in-end signal is a signal supplied to determine acceptance or non-acceptance of an interrupt operation at the time of SCU interlock. Depending on the circuit configuration, an instruction address adder (not shown) may be used as the two adders for the operand address calculation.

FIG. 2 is a diagram explaining the flow of instruction processing in the embodiment of the present invention, and FIG. 3 shows a similar diagram of instruction processing using the conventional method for comparison.

In FIG. 2, as an example, vector load (VLD)
) command, each element e1 to el2 is processed as shown. If a buff error or the like occurs during the processing of element e5 and an SCU interlock is output, an interrupt will be performed if it is in an interrupt-enabled state, and a scalar load (
LD) instruction is activated in advance, and processing of the LD instruction is completed (represented by a block). Then, the subsequent vector operation (VAD) instructions (elements 1 to 12) are activated in advance and executed. In this way, VLD, LD, VAD
Instructions are processed redundantly.

In the conventional system shown in FIG. 3, even if an SCU interlock occurs, the LD instruction cannot be processed until the VLD instruction is completed, and the VLD, LD, and VAD instructions are sequentially processed in this order.

〔Effect of the invention〕

According to the present invention, it is possible to perform redundant processing of a vector load instruction and a scalar data load instruction, thereby improving the processing speed of an additive vector processing device.

[Brief explanation of the drawing]

FIG. 1 is a partial block circuit diagram of a processing device that performs an embodiment of the present invention, FIG. 2 is a diagram explaining the flow of instruction processing in the embodiment, and FIG. 3 is a diagram similar to FIG. 2 in a conventional example. This is a diagram. In the figure, 1... Instruction buffer, 2... D state instruction buffer, 3... A state instruction buffer, 4... Preceding D state instruction buffer, 5... Preceding A
State instruction buffer, 6,7...operand address adder, 8.98...!・Instruction decoder, lO...Instruction pipeline control unit, 11...
It is an address bus multiplexer.

Claims (1)

[Claims] In a scalar data fetch method in an additive vector processing device in which vector load data is stored in a vector register of a vector processing unit via a scalar processing unit, an adder (6, 7) for operand address calculation is provided. ), and the scalar processing unit loads the vector load into one adder (
6) is used to calculate the address of the subsequent scalar instruction by the other adder (7) during execution, and during the interlock caused by interrupting vector loading, the other adder (7) calculates the address of the subsequent scalar instruction during execution.
) A scalar data fetching method in an additive vector processing device is characterized in that the address of a subsequent scalar instruction is issued from a scalar instruction and the subsequent scalar instruction is executed.