JPS59220844A - Instruction reexecution control system - Google Patents

Abstract

PURPOSE:To retry an instruction where malfunction occurs and improve reliability by holding a vector instruction which is not executed even when a scalar instruction and a vector instruction are processed in parallel for the high speed execution of the instructions. CONSTITUTION:Scalar instructions and vector instructions are set up previously in a main storage device together. An instruction reexecution pointer register 26 controls the address of an instruction to be retried even if malfunction occurs to the instruction processed by a pipeline while the scalar instructions and vector instruction coexit and are processed sequentially. Namely, while the scalar instructions and vector instructions are processed in parallel for high-speed processing, a readout address register 35 points unexecuted instructions in an instruction word stack 29 unless the operands of both instructions do not coincide with each other. Consequently, the instructions pointed by the circuit 35 are read out of the circuit 29 even in case of malfunction and supplied through a selecting circuit 30 to a vector instruction decoding part 31 to be reexecuted.

Description

Detailed Description of the Invention (4) Technical Field of the Invention The present invention relates to an instruction re-execution control method, particularly to a data processing device comprising a scalar processing device and a vector processing device, which processes instructions based on pipeline processing. In a device that executes scalar instructions and vector instructions in parallel, when a malfunction occurs in the processing of the vector instructions,
The present invention relates to an instruction re-execution control method that automatically re-executes the malfunctioning instruction.

(2) Prior art and problems FIG. 1 shows an example of a general vector processing system, and FIG. 2 shows an example of instruction words for scalar instructions and vector instructions.

In the figure, 1 is a main storage device, 2 is a channel device, 3 is a scalar processing device, 4 is a vector processing device, 5 is a buffer storage device, 6 is a scalar register, 7 is a scalar arithmetic unit, 8 is a scalar instruction control unit, 9 is an interface register, lO
is a vector instruction control unit, 11 is a load/store pipe, 12 is a vector register, 13 is a vector adder,
14 represents a vector multiplier.

The scalar processing device 3 is a normal central processing unit (CPU) that fetches and executes instructions sequentially from the main storage device 1. The vector processing device 4 is a device that can simultaneously perform the same type of calculation on data of a large view. It is used as an auxiliary to the scalar processing device 3. The buffer storage device 5 is a device that speeds up access to the main storage device 1. Scalar register 6 is a group of registers for processing scalar data. The scalar operator 7 is
Under the control of the scalar instruction control unit 8, arithmetic processing is performed according to the instruction.

The scalar instruction control unit 8 controls fetching, decoding, and execution of instructions. If it is detected that the instruction is a vector instruction, the instruction and information necessary for instruction processing are passed to the vector instruction control unit 10 via the interface register 9. That is, the scalar instruction control section 8 can be considered to be a main instruction control section, and the vector instruction control section 10 can be considered to be a subordinate instruction control section. The vector instruction control unit 10
The vector instruction is decoded, and the vector adder 13, vector multiplier 14, etc. are activated according to the decoding result.

Load/store pipe 11 is an interface between main memory 1 and vector register 12. The vector register 12 is a register that holds a data group to be subjected to vector operations.

The instruction word of a scalar instruction, for example, as shown in FIG. 2(A), consists of an instruction code section OP, a first operand section R1, and a second operand section R2. Depending on the contents of the instruction code section OP, for example, the data of the first operand R1 notator and the second operand R2 are operated, and the result is the first operand R.
It is stored in 1.

The command word of the vector command is, for example, as shown in FIG. 2 (b), an instruction code part OP1 and an extended instruction code part EOP.

It has a first operand part R1, a second operand part R2, and a third operand part R3, and depending on the contents of the extended instruction code part EOP, for example, the data in the second operand part R2 and the data in the third operand part R3 can be changed. is calculated and the result is stored in the first operand section RIIC. Scalar instructions and vector instructions are distinguished by the code in the instruction code section OP.

In the device shown in FIG. 1, the instructions fetched from the main memory l include a mixture of scalar instructions and vector instructions. When these instructions are sequentially read out and processed one by one using a so-called pipeline method, if an error occurs in the processing of an instruction, it is sufficient to re-execute the instruction starting from the instruction in which the error occurred. However, when attempting to execute scalar instructions and vector instructions in parallel in the scalar processing device 3 and vector processing device 4, respectively, in order to process instructions at high speed, according to the conventional method, in the middle of instruction processing, There is a problem in that it is not possible to execute an instruction that causes a malfunction. The processing time for vector instructions is usually much longer than that for scalar instructions, so if a "C" malfunction occurs during the processing of a vector instruction, only the instructions after that vector instruction will be re-executed. I can't.

(Objective and Structure of the Invention The present invention aims to solve the above problems. In order to process instructions at high speed, even when scalar instructions and vector instructions are processed in parallel, unfinished vector instructions are retained. The purpose of this invention is to provide a method that makes it possible to retry an instruction that has malfunctioned.

Therefore, the instruction re-execution control method of the present invention has a main instruction control section and a subordinate instruction control section, and the fertile instruction control section is configured to provide instructions to the subordinate instruction control section according to the type of instruction. In a data processing device that passes information and executes instructions, 2) an instruction holding register that sequentially holds a plurality of pieces of information regarding the instructions passed from the main instruction control unit to the slave instruction control unit; It is provided with at least a stack address conflict register that points to an uncompleted instruction among the suspended instructions, holds the instruction in which a malfunction has occurred, and executes instructions from the i-nostar based on the stack address register. The feature is that the program can be downloaded and re-executed. This will be explained below with reference to the drawings.

(2) Embodiment of the Invention FIG. 3 shows the configuration of a simple embodiment of the invention, and FIG. 4 shows a time chart when scalar instructions and vector instructions are sequentially processed.
FIG. 5 shows a time chart for explaining in detail the present invention when scalar instructions and vector instructions are processed in parallel.

In the figure, numerals 6.8.9 and lO correspond to those in FIG. 1, 20 is an instruction fetching section, 21 is an instruction decoding section, 22 is an address operation section, 23 is an operand fetching section, 24 is an instruction execution section,
25 is an instruction fetch register, 26 is an instruction re-execution pointer register, 27 is a vector instruction fetch unit, 28 is a write address register, 29 is an instruction word stack, 3
0 is a selection circuit, 31 is a vector instruction decoder, 32 is an addition instruction control register, 33 is a multiplication instruction control register, 34
3 represents a load command control register, and 35 represents a read address register.

Scalar instructions and vector instructions are mixed and prepared in advance in the main memory. The instruction retrieval unit 20 receives the instruction f--
This circuit fetches instructions from the location on the main memory indicated by the register 25. The instruction fetched by the instruction fetching section 20 is passed to the instruction decoding section 21 in the next cycle. The instruction decoder 21 decodes the instruction code. If it is determined that it is a vector instruction as a result of decoding,
Store instruction information in interface register 9.

Also, if the vector instruction is, for example, the scalar accompaniment register 6
When the contents of the interface register 9 are needed, the contents are stored in the data section of the interface register 9.

The address calculation unit 22 calculates the real address of the operand. According to the obtained address, the operand fetch unit 23 fetches operand data necessary for executing the instruction.

The instruction execution unit 24 executes the instruction, and the processing of one instruction ends. The instruction re-execution pointer register 26 is a register that holds the address of the instruction following the instruction that has completed execution. By this register 26, ℃,
When the instructions processed in the pipeline are only scalar instructions, or when a mixture of scalar and vector instructions are processed sequentially, it is possible to manage the addresses of instructions that should be retried in the event of a malfunction. . The configuration of the scalar instruction control section 8 may be considered to be the same as the conventional one.

Since the vector instruction control section 10 is activated only when the fetched instruction is a vector instruction, the scalar instruction control section 8 can be regarded as a main instruction control section and the vector instruction control section 10 as a subordinate instruction control section.

The vector instruction fetching unit 27 is a circuit that fetches vector instructions from the interface register 9. The extracted instruction is sent to the instruction word stack 29 and selection circuit 30. The instruction word stack 29 is composed of a plurality of registers that hold vector instructions, and functions as a buffer at the interface with the scalar instruction control unit 8 and as an instruction storage unit for instruction retry, which will be described later. ing. The write address register 28 is a register that holds the address to be written next in the instruction word stack 29. The vector instruction information fetched by the vector instruction fetch section 27 is stacked on the instruction word stack 29 according to the write address register 28, and the write address register 28 is updated to point to the next address.

The selection circuit 30 is a circuit that selects either the vector instruction extractor 27 or the instruction word stack 29 and supplies the vector instruction to the vector instruction decoder 31.

The vector instruction decoder 31 is a circuit that decodes vector instruction codes, particularly extended instruction codes shown in FIG. As a result of decoding, if the instruction is a vector addition instruction, it is stored in the addition instruction control register 32, if it is a vector multiplication instruction, it is stored in the multiplication instruction control register 33, and if it is a vector data load instruction, it is stored in the load instruction control register 34, etc. , information for activating each instruction execution unit (not shown) is set. If the operands do not match, for example, vector addition, vector multiplication, and vector data loading can each be performed in parallel. Read address register 35 points to an uncompleted instruction on instruction word stack 29. The instruction is updated to point to the next instruction by the execution completion signal from the vector instruction execution unit. If a hard error occurs during processing of a vector instruction, the instruction pointed to by the read address e register 35 is read from the instruction word stack 29 and sent to the selection circuit 30.
The instruction is then supplied to the vector instruction decoding unit 31, and subsequent instructions from that instruction are re-executed. In addition,
Needless to say, parallel processing of a scat instruction and a vector instruction requires that their operands, especially the operands in the main memory to be written, do not match. Even if the retry is performed independently of the control unit 8, no problem will occur. Vector instruction processing is delayed, instruction word stack 2
9 becomes full, the search command control unit 8 is controlled to wait. This can be considered to be performed in the same way as normal buffer control.

In FIG. 4, SO through S3 represent search instructions, and vO through v2 represent vector instructions.

Each instruction has an instruction fetch cycle IF, an instruction decoding cycle D
Execution ends after one address operation cycle A1, operand fetch cycle OF, and instruction execution cycle E. In the case of a vector instruction, the address operation cycle A is followed by a vector instruction fetch cycle VF and a vector instruction decode cycle VD.

and processing cycles VA, VM of each vector instruction.

VL etc. are required. Even in vector instruction processing,
Formally, the operand cycle OF and instruction execution cycle E in the processing of the instruction are prepared. When processing Squash instructions and vector instructions sequentially,
As shown in FIG. 4, the execution of the next instruction is delayed until the execution of the previous instruction is completed. Instruction fetch register (
IFR) holds the address of the instruction to be fetched during pipeline processing. The instruction reexecution pointer register (IRP) holds the address of the earliest fetched instruction until execution of the instruction is completed.

Therefore, for example, if an error occurs during execution of the instruction vo at address 10404, the contents of the instruction re-execution pointer register are referred to, and the instruction is re-executed from the instruction vO at address 10404 to attempt recovery. The processing shown in FIG. 4 is the same as the conventional one.

When the data handled by the scan instruction and the vector instruction are different, the scan instruction and the vector instruction can be executed in parallel, as shown in FIG. 5, for example. That is, for example, the scan instruction S2 at address Mtle is 104I.
One execution is started after waiting for the completion of the vector instruction vO at address I and the vector instruction V1 at address 110. In addition,
For example, vector instruction 0 adds VAS (Vict,
or Add 5calor) instruction, and even if the scan instruction S2 is an instruction to update the scan register, the data in the scan register is sent via the gator section of the interface register 9 shown in FIG. Since it is held in the instruction word stack 29, it is not affected by the preceding execution of instruction S2.

For example, assume that a malfunction occurs during execution of the 10404 address command vO. At this time, according to the conventional method, the instruction re-execution pointer register (IRP) has already been set to 1.
269i location, the command cannot be retried even if IRP is used. Even if the IRP were to control the int to address 10404 in this case, the scan instruction S2 would be
, S3 will be executed twice, so if the input operand and the output operand are generally the same as shown in FIG. Become.

In the case of the present invention, if an error occurs during the execution of the vector instruction vO, only the vector instruction groups vO1v1 and v2 are re-executed. That is, at least until the execution is completed, the vector instructions VO, Vl, V2 and the data necessary for their processing are stored in the instruction word stack 2 shown in FIG.
9 and is held in the write address register (WA)
28 points to the next address ST3 of vector instruction (2). On the other hand, read address register (RA)
35 points to the stack Φ address STO of the instruction until the execution of the vector instruction vO is completed, so when there is an execution error of the vector instruction 0, the read address register (RA) is referenced and Recovery by re-execution will be attempted.

The explanation above has been given using the scalar instruction control section as the main instruction control section and the vector instruction control section as the slave instruction control section. The same can be applied to.

(G) As described in detail, according to the present invention, while processing instructions at high speed through parallel processing, the system can re-execute instructions that have malfunctioned in response to intermittent hardware failures caused by noise, for example. This makes it possible to improve the reliability of the system.

[Brief explanation of drawings]

Fig. 1 is an example of a general vector processing system, Fig. 2 is an example of instruction words for scalar instructions and vector instructions, Fig. 3 is a configuration of an embodiment of the present invention, and Fig. 4 is an example of scalar instructions and vector instructions. FIG. 5 shows a time chart for explaining the present invention in detail when scalar instructions and vector instructions are processed in parallel. In the figure, 8 represents a scalar instruction control section, 9 an interface register, 10 a vector instruction control section, 28 a write address register, 29 an instruction word stack, and 35 a read address register. Patent applicant Fujitsu Limited

Claims (1)

[Claims] A main instruction control unit and a slave instruction control unit are M, and the main instruction control unit passes information regarding the instruction to the slave instruction control unit according to the type of instruction, and the data processing device that executes the instruction receives the main instruction. An instruction holding register that sequentially holds a plurality of pieces of information regarding the instructions passed from the control unit to the slave instruction control unit, and a stack address that points to an uncompleted instruction among the instructions stored in the instruction holding register. The stack address and register are provided at least, and the stack address and
An instruction re-execution control method characterized in that instructions are retrieved and re-executed based on registers.