JPH0855033A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the clearance of a prefetch queue and the prefetch time of the instruction code of a changeover destination at the time of task changeover and to accelerate the task changeover. CONSTITUTION:A bus control unit 2A is provided with the plural pieces of the prefetch queues 21 to 24 and a bank selection register 16 and a bank selection part 17 select one of the prefetch queues 21 to 24 linked with the selection of a register bank.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus such as a microprocessor which has a plurality of register banks and performs a multitask task switching by switching the register banks.

[0002]

2. Description of the Related Art In recent years, especially in the pipeline type microprocessor architecture, one CPU is used.
On the other hand, a method is widely adopted in which a set of register banks including a plurality of registers is provided and a plurality of tasks (multitasks) are executed in a time-sharing manner by switching tasks for each instruction of the CPU.

Conventionally, in a microprocessor that uses this kind of register bank to perform multitask task switching, if there is only one instruction queue, the data in this queue that has been prefetched at each task switching is used. Since the data of the task to be switched next is fetched from another memory area after being saved in the stack area once, it is impossible to execute the task during this task switching period. Become.

Referring to FIG. 2 which is a block diagram showing a first information processing apparatus which is a conventional general pipeline type microprocessor, the conventional information processing apparatus shown in this figure is a CPU (not shown). An execution unit 1 for decoding and operating instructions and a bus control unit 2 for controlling the bus are provided.

The execution unit 1 decodes an instruction code and generates and outputs an instruction signal for each constituent element of the execution unit 1 from the result of the decoding, an instruction decoding unit 11
And a plurality of general-purpose registers 31 to 34.

The bus control unit 2 is a FIFO having a function of temporarily storing prefetched instruction codes and sequentially sending the stored instruction codes to the execution unit 1.
A prefetch queue 26 including a buffer is provided.

Next, the operation of the first conventional information processing apparatus will be described with reference to FIG. 2. The execution unit 1 and the bus control unit 2 can operate independently. That is, during execution of an instruction in the execution unit 1, the bus control unit 2 can prefetch an instruction code even if a bus activation request based on the execution result of this instruction is not issued. The prefetched instruction codes are sequentially stored in the prefetch queue 26. 1 in execution unit 1
When the execution of one instruction is completed, the prefetch queue 26
Transfers the next instruction code to the instruction decoding unit 11. As a result, the amount of data in the prefetch queue 26 decreases and the memory area becomes empty, so that the instruction code at the next address can be prefetched. Therefore, since the execution unit 1 can immediately receive and execute the next instruction code after finishing the execution of one instruction, the instruction can be always executed without waiting for the instruction code fetch time, and the program processing can be performed at high speed. can do.

However, when addresses are discontinuous when switching tasks in a multi-task operating system (OS), the processing currently being executed is interrupted and used by the task before switching until the branch destination program is executed. There is a problem that it is necessary to save / restore the data stored in the plurality of general-purpose registers 31 to 34 to / from the stack.

Japanese Unexamined Patent Publication No. 2-2534 which solves this problem
The conventional second information processing apparatus disclosed in Japanese Patent No. 40 discloses a register bank corresponding to a plurality of task execution queues for one CPU, a control register for controlling the execution order of these task execution queues, and a queue switching control. Section and
A plurality of tasks are time-divisionally parallel-processed by the plurality of task execution queues.

Referring to FIG. 3, which shows a second conventional information processing apparatus in common representation with FIG. 2 and common blocks are also denoted by common reference characters / numerals, reference is made to FIG. The second information processing device is the execution unit 1
Instead of the instruction decoder unit 11 common to FIG.
It includes a fourth four register banks 12 to 15, a bank selection register 16 for always selecting only one of the register banks 12 to 15, and a bank selection unit 17.

Each of the register banks 12 to 15 comprises a plurality of general-purpose registers, task execution address information, a stored data save area, and the like.

The operation of the second conventional information processing apparatus will be described with reference to FIG. 3. Here, as described above, there is a case in which four register banks are provided and the number of tasks to be processed is four. Take for example. The number of the register bank to be selected is shown in the bank selection register 16, and the data is decoded by the bank selection unit 17. By connecting the decoded output to each of the register banks 12 to 15, one register bank corresponding to the task is selected. Only the selected register bank can be used as a general-purpose register.

The first to fourth numbers of the register banks 12 to 16 and the four task numbers of the first to fourth tasks are 1 respectively.
Corresponding to the pair 1, task switching and register bank switching can be executed as follows. The task number being executed becomes the register bank number being used and is shown in the bank selection register. When switching a task, if the task number of the switching destination is set in the bank selection register 16, the register bank is switched according to the decoding result of the value of the bank selection register 16. Since each of the register banks 12 to 16 contains information on the execution address of the corresponding task, the next prefetch target address is also switched. At this time, since the execution addresses are discontinuous, the contents of the prefetch queue are cleared once, and the instruction code at the switched address is prefetched. This completes task switching.

Explaining an example of switching between tasks and register banks, the register bank used during processing of the first task is the first register bank 12. When the processing target task is switched from the first task to the third task, the register bank is also switched from the first register bank 12 to the third register bank 14. Also, when the task to be processed switches from the third task to the first task, the register bank is set to the third task.
Since the register bank 14 is switched to the first register bank 12, there is no need to save / restore the general-purpose register corresponding to each task, and the first task can be executed in the same general-purpose register state as when processing the first first task. It is possible to continue processing. Therefore, it is not necessary to save / restore the general-purpose registers used before task switching, and the task switching time can be shortened.

The prefetch queue described above can prefetch instruction codes only for consecutive addresses. Therefore, in the second conventional information processing apparatus,
All instruction codes that have been prefetched in the prefetch queue at the time of task switching are cleared, and a prefetch cycle for fetching the instruction code of this program is always performed before the execution of the next program after task switching.

[0016]

The first conventional information processing apparatus described above interrupts the processing currently being executed and executes the program of the switching destination when the addresses are discontinuous during task switching in the multitask OS. The task switching time becomes long because it is necessary to save / restore the data stored in the plurality of general-purpose registers used in the task before switching to the stack.

In the conventional second information processing apparatus which does not require saving / restoring the data stored in the general-purpose register to the stack, the instruction that has been prefetched in the prefetch queue due to the discontinuity of the address when switching the task. All the codes are cleared, and after the task switching, the prefetch cycle for fetching the instruction code of the program after this task switching is required before executing the next program.
After all, there was a drawback that the task switching time became long.

[0018]

An information processing apparatus according to the present invention includes N register banks including a plurality of general-purpose registers, and a register bank that selects one of the N register banks as a selected register bank. Selection means,
Instruction decoding means for decoding the instruction code and generating an instruction signal for processing corresponding to the decoding result, and temporarily holding the prefetched instruction code, and holding the held instruction code in the instruction decoding means in a predetermined order. In an information processing apparatus comprising: a bus control unit including a prefetch instruction code buffer unit for sending out, the bus control unit includes N prefetch instruction code buffer units, and the register bank selection unit selects the selected register bank. In conjunction with this, one of the N prefetch instruction code buffer means is selected as the selected prefetch instruction code buffer means.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the embodiment of this invention shown in FIG. The information processing apparatus of FIG. 2 has an execution unit 1A common to the second conventional information processing apparatus having four register banks 12 to 15, a bank selection register 16 and a bank selection unit 17, and a bank instead of the bus control unit 2. The bus control unit 2A includes four prefetch queues 21 to 24 to which the decode outputs of the selection unit 17 are respectively connected.

Next, the operation of the present embodiment will be described with reference to FIG. 1. Here, in addition to the four register banks similar to the conventional one as described above, four prefetch queues are provided and processed. The case where the number of tasks is four is taken as an example. Therefore, it is assumed that the task number, the register bank number, and the prefetch queue number are associated with each other, and that the task number being processed, the register bank used at that time, and the prefetch queue number match. .

Only one register bank to be used and one instruction prefetch queue are selected for one task from among the register banks 12 to 15 and the prefetch queues 21 to 24. The bank selection register 16 holds the currently executed task number, that is, the number of the register bank and the prefetch queue currently selected and used. The value of the bank selection register 16 is set to the bank selection unit 1
7, and selects only one used register bank and one prefetch queue in response to the supply of the output signal of the bank selection unit 17. Only the instruction prefetch queue selected in this way enables prefetching of externally supplied data and transmission of this prefetch data to the instruction decoding unit 11.

When the task is switched, the task number of the switching destination is set in the bank selection register 16 so that it is switched to the register bank and the prefetch queue having the same number as the task number according to the decoding result of the value of the bank selection register 16. Change Since the register bank contains information on the execution address of the corresponding task,
This execution address is also switched, and the task switching is completed.

At this time, the prefetch queue is switched for each task as well as the saving / restoring of the general-purpose register used by switching the register bank becomes unnecessary.
It is not necessary to clear the data in the prefetch queue each time the task is switched, as in the conventional case. In other words, if the execution target address is continuous when the task is switched and then returned to the processing of this task, the data prefetched and stored in the prefetch queue at the time of execution of the task before switching can be used as it is. .

For example, the value "1" is set in the bank selection register 16 during execution of the first task, and the value "1" is set.
In response to the supply of 1 ', the bank selection unit 17 outputs a selection signal S1 for selecting the first register bank 12 and the first prefetch queue 21. In response to the supply of the selection signal S1, each of the first register bank 12 and the first prefetch queue 21 used during the processing of the first task is selected.

Next, when the task to be processed is switched from the first task to the third task, the bank selection register 16
Set the value to '3'. As a result, the bank selection unit 17 outputs the selection signal S3 for selecting the third register bank 14 and the third prefetch queue 23 in response to the supply of the value "3" of the bank selection register 16. This selection signal S1
In response to the supply of
Register bank 14 and third prefetch queue 23
Switch to each. Here, the task to be processed is again the first
When returning to the task, first register bank 1
2. Switch to each of the first prefetch queues 21.

In the process of switching the task to be processed from the first task to the third task, and in the process of returning from the third task to the first task, the data in the first prefetch queue 21 is not cleared but held as it is. Not only the contents of the first register bank 12 but also the contents of the prefetch queue 21 can be used as they are when the first task is executed before the switching without saving / restoring the corresponding general-purpose register. That is, when the processing is returned to the first task, the instruction code held in the first prefetch queue 21 is the first code.
Since it is the instruction code of the program at the return address of the task, as soon as the task to be processed is switched to the first task, the portion following the execution portion of the program before switching can be continued.

This eliminates the need for prefetching the instruction code, which was required before the program was executed after the task switching, and the switching time of the task to be processed can be shortened.

[0028]

As described above, the information processing apparatus of the present invention is provided with N prefetch queues, and the register bank selection means interlocks with the selection of the selected register bank.
By selecting one of the prefetch queues, it is not necessary to clear the prefetch queue at the time of task switching and prefetch the instruction code before program execution, so that the execution time at task switching can be shortened. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention.

FIG. 2 is a block diagram showing a first conventional information processing apparatus.

FIG. 3 is a block diagram showing a second conventional information processing apparatus.

[Explanation of symbols]

 1, 1A execution unit 2, 2A bus control unit 11 instruction decoding unit 12 to 15 register bank 16 bank selection register 17 bank selection unit 21 to 24, 26 prefetch queue 31 to 34 register

Claims (3)

[Claims] 1. A N register bank including a plurality of general-purpose registers, a register bank selecting means for selecting one of the N register banks as a selected register bank, and an instruction code for decoding the decoding result. Instruction decoding means for generating a processing instruction signal corresponding to
An information processing apparatus comprising: a pre-fetch instruction code buffer means for temporarily holding the prefetched instruction code; and sending the held instruction code to the instruction decoding means in a predetermined order. The means includes N prefetch instruction code buffer means, and the register bank selection means selects one of the N prefetch instruction code buffer means in association with the selection of the selected register bank. An information processing device, characterized by being selected as means. 2. A bank selection register in which said register bank selection means stores a task number corresponding to one processing target task among N tasks, said selection register bank and said bank in response to supply of said task number. An information processing apparatus according to claim 1, further comprising a bank selection circuit which outputs a selection signal for selecting each of the selection prefetch instruction code buffer means. 3. The information processing apparatus according to claim 1, further comprising a first-in first-out buffer that outputs the instruction codes prefetched by the prefetch instruction code buffer means in an input order.