JPS63292232A - Microprogram controller - Google Patents

Abstract

PURPOSE:To realize fast branching, by constituting a control storage of two-port readout, reading out microinstruction in both cases where branching is performed and to branching is generated, and selecting two microinstructions in the same micro machine cycle as that of execution based on the result of the execution. CONSTITUTION:The titled controller is provided with a storage means 18 provided with at least two readout ports, address generating means 10 and 12 responding to those readout ports respectively, a selection means 14 which selects one of the outputs of plural readout ports, a control means 15 for the selection means 14, and a part to be controlled. The part to be controlled is controlled directly by the output of the selection means 14, or indirectly via a decoder, and the control means 15 of the selection means 14 is controlled by a signal outputted from the part to be controlled. It is possible to remove a delay slot required in a conventional device inevitably, and as a result, a microprogram controller having superior efficiency can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to the configuration of a device controlled using a microprogram, particularly to the configuration of a portion related to realization of branching.

Conventional Technology There are already many conventional examples of microprogram control methods, such as those described in detail in "Microprogramming" (Takanobu Baba, Shokodo, 1986).

FIG. 4 shows a conventional microprogram device. Fourth
In the figure, 1oO is a control memory ROM (CROM), 1
02 is a mapping PLA (MAP), 104 is a sequencer (SEQ), and 106 is a microinstruction register (MIR).
), 10aid: Microinstruction decoder (DEC), 1
10 is an execution unit (EU), 112 is a status register (
SR).

Further, FIG. 6 shows a timing chart of the microprogram device shown in FIG. 4. In FIG. 5, it is assumed that the microprogram device shown in FIG. 4 is operating with three pipeline stages: microinstruction fetch and decoding, execution, and output of result and status information. FIG. 6 shows the operation of three micromachine cycles.

Now, the operation of the microprogram device shown in FIG. 4 will be explained using FIGS. 4 and 5. In the first micromachine cycle, a first macroinstruction is input to the MAP 102 via the macroinstruction input terminal 101, and the CROM1 of the microprogram corresponding to the macroinstruction is
Outputs the starting address at 00. Here, the first
Assume that there is a microinstruction that instructs a branch based on the contents of macroinstruction 1jSR112. The 5EQ 104 receives the above starting address and outputs it as an address of the CROM 100. As a result, the CROM 100 outputs a microinstruction. The operations described above are performed in the first microinstruction fetch cycle after the first microinstruction is input.

In the second micromachine cycle, the first microinstruction controls EUllo either after being decoded by the DEC 108 or directly. The operation (EXl) 144 corresponding to the first microinstruction is
After being performed in lo, a status signal is output and SR1
Saved in 12. During this time, 31! :Q104 calculates the storage address of the next microinstruction.

The instruction fetched in this second micromachine cycle is at the time when the microaddress calculation was performed.In the first micromachine cycle, the status signal (S○) of the result of the immediately previous microinstruction execution (EXo) 134 is still present. Since 135 has not been obtained, the next consecutive address will be calculated. This method is known as a delayed branch method, and the microinstruction calculated here and placed at the next consecutive address is called a delay slot instruction.

The microaddress calculation in the next second micromachine cycle is performed by outputting the status signal (S○) 136 as a result of the execution (EXO) 134 in the first micromachine cycle from the 5R112 to the 5EQ10.
4, and the storage address of the branch destination microinstruction is calculated. During this time, the aforementioned delay slot instruction fetch (IF 2) 160 is performed.

In the next third micromachine cycle, the microinstruction at the branch destination is fetched (IF3) 160, and the microinstruction in the delay slot is executed (EX2).

In conventional microprogram controllers, branching is implemented in this way, which inevitably results in delay slots.

Problems to be Solved by the Invention In the microprogram control device according to the conventional technology described above, a delay slot always occurs to realize a branch, and there is no delay until the microinstruction at the branch destination address is actually executed. There is a delay of 1 microman cycle. This delay can occur if the pipeline is not locked and is still operating without any branches.
It is possible to apparently eliminate this problem by changing the execution order of microinstructions that use operands that have no data dependence. However, in cases where it is necessary to take frequent branches, or where there is not enough micromachine cycles from one branch to the next, and it is not possible to change the execution order of microinstructions as described above, the above method can be used. As such, it is not possible to eliminate the apparent delay in branching. In such cases, it is desirable to realize high-speed branching that essentially eliminates wasted micromachine cycles.

Means for Solving the Problems In view of the above problems, the present invention provides a control storage means for storing microinstructions with a two-read port configuration, so that when a branch is executed, the microaddress of the branch destination can be read. It simultaneously reads the stored microinstruction and the microinstruction stored at the next microaddress if no branch is taken, and captures the status signal output as a result of execution in the execution unit into the status register. A microprogram controller that selects one of the two microinstructions mentioned above within the same micromachine cycle for execution and makes it the actual microinstruction to be used in the next micromachine cycle. .

Effect By adopting the branching mechanism described above, it is possible to eliminate the occurrence of delay slots that were unavoidable in conventional microprogram control devices, and as a result, the branch destination is It becomes possible to execute the microinstruction at the address of , and even if there are frequent branches, an efficient microprogram control device that does not slow down the execution speed of the microinstruction due to wasted micromachine cycles can be realized. Further, the branching mechanism of the present invention can be applied to both conditional branching and unconditional branching, and branching in two directions can be easily realized.

Furthermore, by increasing the number of read ports of the control storage means, branching in multiple directions can be easily realized.

Embodiment FIG. 1 shows a microprogram control device according to a first embodiment of the present invention. In FIG. 1, 1o and 12 are microaddress generators A and B (MAGA, MAG), respectively.
B), 14 is a microword selector (MWS), 15
is a multiplexer, 16 is a microinstruction register (MI
R), 18 is a 2 read port control memory ROM (CRO
M), 20°22 are the first and second read address input terminals of CROM1B, 24.26 is CROM1o
8 first and second data output ports, 108 a microinstruction decoder (DI!:C), and 110 an execution unit (E
U), 2o is a data input terminal for the status signal 114 to EUllo, and 116 is a data output terminal from EUllo.

FIG. 2 shows the timing of the operation of the microprogram control device shown in FIG. Here, it is assumed that the system operates with three pipeline stages, similar to the timing of the conventional example shown in FIG.

FIG. 3 shows microinstructions of the microprogram controller shown in FIG. In FIG. 3, the first field is the execution unit (EU) 1100 control field (EUC
) 41, the second field is the control field (MUDR-Person) of the first microaddress generator (MA(,A)) 42, the third field is the control field of the second microaddress generator (MAGB) 12. Control field (ADH-B)
43, the fourth field is a microword selector (MW
S) 140 control field (MWSC) 43.

Now, the operation of the first embodiment of the present invention shown in FIG. 1 will be explained using FIGS. 1 to 3.

In the first micromachine cycle shown in FIG. 2, a first microinstruction fetch (11) 30 is executed. Next, in the second micromachine cycle,
Assume that a second microinstruction fetch (IF 2) 40 is executed.

In the second micromachine cycle, the microinstruction fetched in the first micromachine cycle is executed (1!:Xl)2a.

Each field of said first microinstruction is:
EUC41 instructs execution 37 of KUl 10, ADR
-A32 and ADR-B34 are supplied to a first microaddress generator A10 (MAGA) and a second microaddress generator B12 (MAGB), respectively, and their respective outputs are connected to two read port control storage ROMs.
(CROM) 18 is connected to a first address port 2o and a second address port 22. After the two data outputs DATA-A33 and DATA-836 of the two read port control storage ROM (CROM) 1B are output from the first data output port 24 and the second data output port 26, respectively, the multiplexer 1
5. Said multiplexer 15 is controlled by a microinstruction selector (MWS) 14. The microinstruction selector (MWS) 14 has an execution unit (ELT).
) 110 and the nwsc field 44 in the aforementioned microinstruction. Since the status signal output 118 is established at the end of the second micromachine cycle, the output 36 of the multiplexer 15 is
It is determined at the end of the micromachine cycle.

In the first embodiment of the present invention shown in FIG.
micro address generator (MAGA) 10 and second
Although each of the microaddress generators (M AGB ) 12 is independently controlled by microinstructions, any signal that can be used as a means for controlling the generation of microaddresses can be controlled by microinstructions. It goes without saying that the control field of the microaddress generator in the microinstruction can be deleted.

FIG. 6 shows a microprogram control device according to a second embodiment of the present invention. In FIG. 6, the execution unit (K U
) 110 is input to the microword selector (MWS) 14;
It is also input to the status register 112. The status information held in the status register 112 is input to a first microaddress generator (MAGA) 10 and a second microaddress generator (MAGB) 12. By adopting this configuration, a functional branch is executed by the first microaddress generator (MAGA) 10 and the This can be realized independently for each of the two microaddress generators (MAGB) 12, and in combination with the branching mechanism described in the first embodiment of the present invention, branching in multiple directions can be easily realized. In the second embodiment of the present invention shown in FIG.
-A field 42 and person DR-B field 43, respectively.

In the second embodiment, it is assumed that each of the first microaddress generator (MAGA) 10 and the second microaddress generator (MAGB) 12 adopts the function branching method. It goes without saying that only one microaddress generator may employ the function branching method.

As described above, the control memory has a two-port read configuration,
By reading the microinstructions for both cases in which a branch occurs and cases in which a branch does not occur, and selecting the above two microinstructions during the same micromachine cycle as execution based on the result of execution, the next micromachine cycle with a branch instruction is executed. The microinstruction at the branch destination can be executed from the micromachine cycle.

By configuring the control memory with two read ports, the amount of hardware increases only slightly, and efficient micro-branching can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprogram control device according to a first embodiment of the present invention, and FIG. 2 is a timing diagram of the operation of the microprogram control device according to a first embodiment of the present invention shown in FIG. 3 is a format diagram of microinstructions of the microprogram control device according to the embodiment of the present invention shown in FIG. 1, FIG. 4 is a block diagram of a conventional microprogram control device, and FIG. 6 is a diagram of a conventional microprogram control device. FIG. 6 is a block diagram of a microprogram control device according to a second embodiment of the present invention. 10.12...Micro address generator, 14
9. ...Micro word selector, 15...
Multiplexer, 18...2 read port control memory ROM, 20.22...first and second
address input terminal, 24.26...first and second data output terminal, 31.41.141.151
... Control signal, 108 ... Decoder,
110...Execution unit, 114...Data input terminal, 116...Data output terminal, 118...
...Status signal output. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 4 - K Niwa's O's Regret

Claims (2)

[Claims] (1) storage means having at least two read ports; address generation means corresponding to each of the read ports; selection means for selecting one of the outputs of the plurality of read ports; The control means for the selection means is provided with a control means for the selection means and a controlled section, the controlled section is controlled directly by the output of the selection means or indirectly via a decoder, and the control means for the selection means is controlled by the output of the selection means. , a microprogram control device characterized in that it is controlled by a signal output from the controlled section. (2) The microprogram control device according to claim 1, wherein at least one of the address generation means is controlled directly by the output of the selection means or via a decoder.