JPS59160239A - Information processing device - Google Patents

Abstract

PURPOSE:To process an arithmetic of a registered memory, which is continued (n) times, at a high speed by 2n machine cycle, by executing an address calculation of an operand describing part before decoding an operation code of a machine language instruction and branching it to a macro-instruction group. CONSTITUTION:When executing an instruction of a form 2, one instruction is executed by four machine cycles by executing a decoding D of an operation code and an address calculation A of an operation describing part, in parallel by the same machine cycle. Also, when executing a form 1 (branch instruction), the address calculation A of the operand describing part is executed before the decoding D, and a main storage device address of a branch destination is calculated first. In this way, an instruction of the branch destination is read out by the following machine cycle, and one machine cycle is shortened comparing with the case when there is no branching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprogram-controlled information processing device, and more particularly to an information processing device in which the number of microinstruction steps is reduced by advance control.

[Prior art]

A microprogram-controlled information processing device is programmed with a microinstruction set that specifies the basic operations of the processing device, stores this in a control storage device, and sequentially reads and executes the microinstructions from this to control the operation of the processing device. Realize. A microprogram control unit for realizing machine language instructions of a processing device is mainly composed of three parts. That is, as follows.

(1) Read machine language instructions from main memory.

(2) Decipher the read machine language instructions.

(3) Execute the decoded machine language instruction.

(2) involves the process of decoding machine language instructions and branching to the microinstruction execution routine corresponding to each instruction; (3)
In this example, there is a process of executing the operation section after calculating the address of the operand description section common to each instruction.

Machine language instructions are prepared to perform efficient processing depending on their use and purpose, and here, as shown in FIG. 1, examples of two formats are shown.

In both Format I and Format 2, the attributes of the operands differ depending on the operation code part, and the operands are divided into register contents, contents calculated by registers and displacement, or contents of the main storage device. Format 1 differs from Format 2 in that the first operand is implicitly determined to be the contents of a specific register or the contents of the main memory indicated by the register. This example is an instruction that performs an operation on the first and second operands,
Format 1 is a branch instruction, and format 2 is an operand description section 2.
In this example, the operand description part l points to the contents of the register and this is the first operand. be.

FIGS. 2 and 3 show time charts of the operation flow of microinstructions that implement Format 2 machine language instructions in one arithmetic unit. FIG. 2 shows the processing of a machine language instruction. This is an operation flow for repeatedly performing a two-operand operation E. In this operation flow, the arithmetic unit does not operate except for the operation E between the address calculation A1 operands.

Fig. 3 shows an improved version of this method that enables high-speed processing.

FIG. 3 shows the operation flow of microinstructions in which five machine language instructions are processed simultaneously with a two-machine cycle shift, thereby making it possible to efficiently read out the main memory and use the arithmetic unit. In order to achieve this, the hardware needs at least three instruction registers to store machine language instructions, and an operation register to perform operations between the machine language operands read out after decoding the machine language instructions. A storage control circuit is required.

As is clear from FIG. 3, the processing time for three instructions is reduced from 15 machine cycles to 10 machine cycles. If the information processing device that operates according to the operational flow shown in FIG. 3 uses a format I branch instruction, it operates according to the operational flow shown in FIG. 4. That is, if the second read machine language instruction is a branch instruction, the third read instruction must not be executed and the program must continue from the branch destination machine language instruction. This causes a disturbance in the operational flow and reduces the processing speed of calculations.

When one arithmetic unit is operated optimally, if a Format 2 machine language instruction is executed n times in succession, the operation should take 211 machine cycles. However, as shown in FIG. 3, in a conventional information processing device using one arithmetic unit, when a Format 2 machine language instruction is executed n times in succession, 2 n +
It took 4 machine cycles, and the information processing device could not be operated optimally.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus capable of solving such conventional problems and operating one arithmetic unit optimally to improve processing efficiency.

[Summary of the invention]

An information processing device of the present invention is a microprogram-controlled information processing device that performs advance control, and includes a plurality of selectors that select one by one a plurality of instructions read from a main storage device, and one instruction selected by the selector. The present invention is characterized in that a control means is provided for executing address calculation of the operand description section of the instruction in parallel with or prior to the decoding of the operation code section of the instruction.

In addition, when the address calculation of the operand description part of the instruction is executed prior to the decoding, specifying that the address calculation of the operand description part of the next read instruction is to be performed by a microinstruction that does not use an arithmetic unit. There are characteristics.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

FIG. 5 is an operation flowchart of a microinstruction of the Format 2 machine language instruction, and FIG. 6 is a schematic diagram of the eight-doware of the present invention that implements this microinstruction.

FIG. 5 is an operational flow in which two instructions are processed simultaneously with a shift of one machine cycle.

In the present invention, (1) when executing the Format 2 instruction,
By performing decode 0 of the operation code and address calculation of the operand description section in parallel in the same machine cycle, one instruction can be executed in four machine cycles, and (11) the above format l (that is, branch When executing an instruction), the address calculation (5) of the operand description section is performed before decoding 0, and by calculating the main memory address of the branch destination first, the branch is executed in the next machine cycle. Read the previous instruction and execute it in one machine cycle less time than if there were no branch,
is possible.

In FIG. 6, 1 is the main memory, 2 and 3 are input side and B side calculation registers, Φ is a memory address register, 5 is a program counter, 6 is a memory buffer register, 7, 8 are first and second instruction registers, 9 is a selector for address calculation, 10 is a selector for decoding machine language instructions, 11 is a decoder for address calculation, 12 is a decoder for decoding machine language instructions, 13
14 is an arithmetic unit, 14 is a microprogram adder circuit, 15 is a microinstruction address selector, 16 is a microinstruction address register, 17 is a control storage device, 18 is a microinstruction register, 19 is a selector for arithmetic control signals, 2
0 is a branch instruction selection decoder.

In FIG. 6, the second instruction held in the two instruction registers 7 and 8 is used to execute the decoding ◎ shown in (1) above and the address calculation of the operand description section in parallel. In addition to newly providing means 9.11.19 for selecting and decoding an instruction read out to control the address calculation of the operand description section,
A completion address calculation advance control designation field 0 is provided in the microinstruction read from the control storage device 17 to control the selector 19. In addition, in order to shorten the steps for the branch instruction shown in (n) above, a branch instruction selection decoder 20 is newly provided, and the previously obtained address calculation result of the operand description part is sent to the memory address register 4. It is controlled so that the program counter 5 is set without setting it to the program counter 5. This prevents the processing speed from decreasing due to branch instructions, and further reduces the processing time by one machine cycle compared to the normal case.

#! The operation shown in FIG. 6 will be explained in detail.

When the microinstruction reads the machine language instruction (IP of instruction 1)
When specified, the instruction l corresponding to program counter 5 is read from the main memory l, and the instruction l is read out from the main memory l.
Set in register 7.

Next, when the microinstruction specifies the machine language instruction read (IP of instruction 2), decode 0 of instruction 1, and address calculation of the operand description part of instruction 1, the main instruction register 8 is set for advance control. The instruction 2 read from the storage device 1 is set. Also, the instruction register 7 in which the instruction to be executed is currently set is set.
is selected by the selector 10, and based on this, a microinstruction address is created in order to branch to the start address of the microinstruction execution group of instruction 1.The decoder 12 decodes the operation code of instruction 1, and its output is processed as a microinstruction. The address selector 15 selects and sets the microinstruction address register 16. 16, 17.18
constitutes a microprogram control section, which accesses the control storage device 17 using the contents of the microinstruction address register 16 as an address, reads the microinstruction from the address area, and sets it in the microinstruction register 18. A microinstruction set in the microinstruction register 18 has three special fields (a
, b, O), one is a field (a) that specifies the address for reading the next microinstruction, the other is a field (a) that outputs a control signal for executing the operation, and the last One of them is field 0 which specifies advance control of address calculation for the next instruction.

When a microinstruction is set in the microinstruction register 18, at the same time, the instruction register 7 in which instruction 1 is set is selected by the selector 9, decoded by the decoder 11 that specifies the operation register and the operation content, and the operand is Outputs a control signal for calculating the address of the description section. At this time, the microinstruction specifies the preceding address calculation (instruction 20A), and the selector 19 selects the arithmetic control signal as the output of the decoder 11.

Next, the microinstruction reads the operand of instruction 1 (OF) and calculates the address of the operand description part of instruction 2 (8
), the contents corresponding to the address register 4 to which the operand address of the instruction l is set are read from the main memory 1 and set in the memory buffer register 6. Further, the instruction register 8 in which instruction 2 is set is selected by the selector 9, and as described above,
The selector 19 outputs a control signal for calculating the address (8) of the operand description part of instruction 2, and the address calculation is set to 0.
1) Do it. When the previous microinstruction specifies machine language instruction decoding 0, the selector 9 selects the instruction register 7 to set the next read machine language instruction.

Next, when the microinstruction specifies the execution of operation 1 of instruction 1, the read operand of instruction 2 (OF), and the decoding of instruction 2, the selector 19 outputs the operation control signal (1 )) and performs an operation according to the operation code of instruction 1 using memory buffer register 6 and register 2, which have set operands. Further, the contents corresponding to the address register 4 to which the operand address of the instruction 2 is set are read from the main memory 1 and set in the memory buffer register 6. At the same time, instruction 2 is decoded and instruction 2 is decoded as described above.
The first microinstruction of the microinstruction group corresponding to is set in the microinstruction register 18.

Next, when the microinstruction specifies the IP of instruction 3 to read the next machine language instruction (02) and the execution of operation E of instruction 2, the microinstruction sets instruction 3 in the instruction register 7 as described above, and at the same time The arithmetic control signal Cb) output from the instruction register 18 is sent to the selector 19.
is selected and the operation (■) of instruction 2 is performed.

Repeat this operation below.

The time chart for the repetition of this operation is shown in Figure 7(b).
Shown below. That is, FIG. 7(b) shows the case where instructions of format 2 are executed consecutively, and the total time to execute instructions 1 and 2 is 5 machine cycles, that is, 2]11+1
(n is the number of instructions) machine cycles, but since the arithmetic unit 13 is not available for instruction 3, it is read out with a delay of 3 machine cycles, and the total time for instructions 1 to 3 is 8 machine cycles. , that is, it will take 2n+2 machine cycles. However, if the arithmetic units 13 are provided on two sides, the process can be executed in two kamashin cycles. As described above, according to this embodiment, by calculating the address of the operand description section using a microinstruction before decoding the operation code of the machine language instruction, it is possible to execute h instructions of the Format 2 in succession. Moreover, it can be executed in a time of 2n machine cycles, which has the effect of increasing the efficiency of the processing device.

Next, FIG. 7 (a
). The difference between FIG. 7(a) and FIG. 7(b) is that
Since instruction 2 is a branch instruction, the operational flow is disrupted. What is unique to the branch instruction in the hardware that implements FIG. 7 (&) is that the branch instruction selection decoder 20 shown in FIG. The present decoder 20 controls the program counter 5 to set the address calculation result of the section, rather than the memory address register 4-, and the read operand to the instruction register 7. This makes it possible to minimize the reduction in processing speed caused by branch instructions.

That is, as shown in FIG. 7(,), when there is branch instruction 2, the total execution time of instructions 1 to 3 is 7 machines.
cycle, which is 2n+1 machine cycles.

[Effects of the Invention] According to the present invention, it is possible to #read the 2-version code of a machine language instruction and calculate the address of the operand description part before branching to the microinstruction group corresponding to the machine language instruction. Therefore, register/memory operations can be performed n times in succession in a time of tq 2 n machine cycles, which has the effect of speeding up the processing device.

[Brief explanation of drawings]

vlM is a diagram showing examples of two instruction formats of machine language instructions,
Figure 2 is a flow diagram of 11 microinstructions that realize the machine language instructions of format 2 in Figure 1, Figure 3 is a microinstruction operation flow diagram that improves Figure 2, and Figure 4 is the format of Figure 1. Figure 5 is a microinstruction operation flow diagram that realizes the machine language instructions in 1.
FIG. 7 is an operational flow diagram of microinstructions implementing the present invention, and FIG. 6 is a schematic configuration diagram of an information processing apparatus showing an embodiment of the present invention. l: Main memory, 2: A-side register for calculation, 3α5): B-side register for calculation, 4 = Memory address register,
5 Niprogram counter, 6: Memory buffer register, 7: Instruction register 1.8: Instruction register 2.9 Near address calculation selector, 1
0: Machine language instruction decoding selector, 11 Near address calculation decoder, 12: Machine language instruction decoding decoder, 13: Arithmetic unit, 14 = Microphone 07' program addition circuit, 15: Microinstruction address selector, 16; Microphone 4 Instruction address register, 17: Control storage device, 18: Microsi instruction register, 19: Arithmetic control signal selector, 20:
Branch instruction selection decoder. 06) H~ firefly value hate hate H~ no <ll! <p <P4g [phase]
order

Claims (1)

[Scope of Claims] α) In a microprogram-controlled information processing device that performs advance control, a plurality of selectors separately select a plurality of instructions successively read from a main memory, and a plurality of selectors selected by the selectors. One instruction operation
An information processing device comprising: control means for executing address calculation of an operand description section of the instruction in parallel with or prior to decoding of the code section. (2) When the control means executes address calculation in the operand description section of an instruction prior to decoding, the control means uses a microinstruction that does not use an arithmetic unit to write the operand description of the next instruction read using the arithmetic unit. 2. The information processing apparatus according to claim 1, wherein the information processing apparatus specifies to perform address calculation of the unit.