JPS58142464A - Microprocessor - Google Patents

Abstract

PURPOSE:To use more than groups of registers selectable in a selection field without increasing the number of bits of a program by providing a switching means which specifies a register in a register group on the basis of the address of an instruction and enables the register to be used. CONSTITUTION:Commands of a microprogram stored in a memory 1 are transferred to an arithmetic device 3 and an address control part 4. Those arithmetic device 3 and controller 4 are supplied with commands from an operation decoder 2 to control a D bus decoder 5 and B bus decoder 6 by their outputs. Further, the register group 8 which inputs the output of the arithmetic device 3 consists of registers 0, 1-F, and register groups 9 and 10 consists of registers 0. 1-3. The command of the decoder 2 are applied to respective bus decoders 5 and 6, which perform control to allowing the use of more than registers in the group 8 selectable in a selection field without increasing the number of bits of the program.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to microprocessors, and more particularly to increasing the number of registers available to a microprogram.

Prior art microprocessors generally have bit groups (hereinafter referred to as fields) for selecting registers. Conventional microprocessors have the disadvantage that they can only select registers within the range of the number that can be specified by the number of bits in the register selection field, which limits the number of registers that can be used.

OBJECTS OF THE INVENTION An object of the present invention is to provide a microprocessor that allows use of more register groups than can be specified in a register selection field.

The present invention is characterized in that a microprocessor uses a part or all of a register group whose number can be specified in a register selection field by replacing it with another register group. In general, the registers used differ depending on the type of processing, and each process occupies a set address area on the memory, so it would be effective if it were possible to switch the type of registers used depending on the memory address.

EMBODIMENT OF THE INVENTION AND ITS EFFECTS An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a block diagram of a microprocessor to which the present invention is applied. A memory 1 stores a microprogram, and an operation decoder 2 transmits instructions of the microprogram to an arithmetic unit 3 and an address control unit 4. The arithmetic unit 3 performs various calculations (e.g.,
(■, OR, ADD). Address control section 4
has the function of creating a jump address etc. in response to a command from the operation decoder 2, and creating the address of the microprogram in the memory 1 to be executed next. The D bus decoder 5 is a decoder that controls in which register the D bus 10, which is the output of the arithmetic unit 3, is stored, and the B bus decoder 6 controls which register is stored in the B bus, which is one input of the arithmetic unit 3-. This is a decoder that controls whether to output to 11. Register group 7 consists of 16 registers, and register group 8 and register group 9 consist of 4 registers. Memory address 12 is an address for memory 1,
In this embodiment, there are 12 pits, ie, memory 1 has 4 words. Memory bus 15 is an output from memory 1.

The function of the present invention as shown in FIG. 1 is that register 0125 in register group 7 is
1-11-21- (or 2-02- of register group 9)
12-22-5 and is selected as the B bus 11, and the D bus 10 is set, and the swapping of the register group is realized by the operation of the D bus decoder 5 and the B bus decoder 6. be done. D bus decoder 5
, B bus decoder 6, the microformat of the microprocessor to which the present invention is applied will be described with reference to FIG. In this embodiment, a 16-bit microprocessor is used. General instructions perform operations on registers and constants.

Register li This is the register specified in the B/D bus selection field. The types of operations include AND, OR, OR (exclusive OR), ADD, and, of course, it is possible to increase the types beyond these three. The result of the operation is B/
Stored in the same register selected by the D bus. In addition to this instruction, there are a jump instruction and a read or write instruction for the memory 1, but these will not be described since they are not directly related to this invention.

Next, details of the D bus decoder 5 and the B bus decoder 6 will be explained using FIG. 6. The signals 415 and 415 of the memory bus 13 are reversely polarized by the NOT circuits 17 and 18, and ANDed by the AND circuit 19, respectively. AND output 36 becomes 11' when bits 4.5 are both %0#. Bit 154 of memory address 12 is set to reverse polarity by the NOT circuit 35, and address bit 033 is set by the AND circuit 21.
and AND output 36. AND output 37 indicates that bits 4 and 5 of memory bus 13 are both %O1, that is, register 0°1.2.3. When selecting , bit 033 of address bus 12 is 1111 bit, ) 134 is %Ql'
When , it becomes %11.

In the AND circuit 22, five signals: address bit 033, address bit 134, and AND output 56 are ANDed. AND output 68 of AND circuit 22 is %O1 for memory bus 15, address bit 035, address bit 1.
'54 is %11 when both are 11#.

Ru. In AND circuit 23, address bit 053 and AND output 36 are ANDed, and furthermore, the output of AND circuit 25 is reversed in polarity in NOT circuit 59.

The negative output 40 of the negative circuit 69 becomes %11 when address bit O55 is %01 or bit 4 or 5 of the memory bus 13 is not 10I, that is, register 0.1.
, 2.5 is not selected. Decoders 24, 25.26 in the D bus decoder 5 are register groups 8, 9.7, respectively.
This is a D bus decoder for. The AND output 37 of the AND circuit 21 is input to the enable input of the decoder 24, the AND output 38 of the AND circuit 22 is input to the enable input of the decoder 25, and the NOT output 40 of the NOT circuit 39 is input to the enable input of the decoder 26. is input. Address bit 055.154 of memory address 12 is 1
101, that is, if memory 1 is divided into word-based pages and called page 0, page 1, page 2, and page 3, the operation is performed on page 2.
When O, 1, 2, and 3 are selected as the D bus, register group 8
The D bus is set to. addressby.

When 0 and 134 are 1111, that is, when an operation is performed on page 6 and register 0125 is selected as the D bus, the D bus is set in register group 9.

In cases other than the above, register group 7 is selected and the D bus is set. Multiplexer 27 in B bus decoder 6
The enable input of the AND output 57 of the AND circuit 21
is input, the AND output 38 of the AND circuit 22 is input to the enable input of the multiplexer 28, and the NOT output 4o of the NOT circuit 39 is input to the enable input of the multiplexer 29. When address bit 053 and bit 134 of address bus 12 are 1101, that is, page 2
When registers 0.1 and 2.3 are selected as the B bus when operating in When registers 0 and 12.5 are selected as the B bus while the register is in the B bus, register □ register group 9 is selected as the B bus. In cases other than the above, register group 7 is selected as the B bus. As described above, depending on the contents of the address bus 12, register group 8 or 9 is used instead of register 0125 of register group 7.
or a microprocessor.

Effects of the Invention According to the present invention, it is possible to easily increase the number of usable registers without increasing the number of bits of a microprogram, and it is possible to achieve high performance by simply adding simple hardware. This has the effect of realizing a microprocessor.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the microprocessor, FIG. 2 is a diagram showing the microphone program format, and FIG. 3 is a detailed block diagram of the D bus decoder and B bus decoder. 1...Memory, 5...Arithmetic number, 5...
D bus decoder, 6... B bus decoder, 7... Register group, 8... Register group, Busy 9... Register group, 24... Decoder, 25... Decoder, 2
6...f Cop-127...Multiplexer, 2
8...Multiplexer, 29...Multiplexer. Talent 1 diagram Talent Z diagram

Claims (1)

[Claims] t In a microprocessor where processing is performed by executing an instruction, there are a number of register groups used in the processing that exceed the number that can be specified in the field specifying the register of the instruction, and the number of registers in the register is specified by the address of the instruction. A microprocessor characterized by comprising register switching means for specifying and enabling a predetermined register.