JPH0683624A - Processor and its control method - Google Patents

Abstract

PURPOSE:To provide a processor and its control method which can suppress the increase of the power consumption in the case of parallel execution of plural processing operations such as the coding and decoding operations, etc. CONSTITUTION:An instruction memory 2 stores the instructions, and an instruction pointer 1 outputs an address signal to the memory 2. An instruction decoder 4 decodes the output of the memory 2 and outputs a control signal based on the contents stored in an instruction. The 1st and 2nd arithmetic parts 9 and 11 are controlled by the control signals given from the decoder 4. The 1st and 2nd data memories 10 and 12 store the data against both parts 9 and 11 respectively and are controlled by the address signal and the control signal of the decoder 4. A data pointer 7 is controlled by the control signal of the decoder 4 and an address signal that is used in common to both memories 10 and 12 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention uses two programs in one program.
The present invention relates to a control method of a processor that processes three different data and a processor.

[0002]

2. Description of the Related Art In recent years, applications of digital signal processors (hereinafter referred to as "DSP") are rapidly spreading. In addition, various specialized DSPs have been devised in the category of processors called DSPs. Eg ADPCM
(Adaptive Differential Pulse Code Modulation) method As an example of a DSP dedicated for voice codecs,
CCITT Standard 32 kbit / s ADPCMLSI Codec ”(Nishiya et al., IEEE Trans. ASSP-25, No.2, pp.219-225, Feb. 19
There are DSPs described in 87). This DSP has a multiplier 31, a shifter / normalizer 32, as shown in FIG.
ALU 33, instruction pointer 34, instruction ROM 35
And a data RAM 36 and a data ROM 37. The instruction pointer 34 gives an address to the instruction ROM 35. The instruction ROM 35 stores the ADPCM processing procedure. The data RAM 36 stores variable data.
The data ROM 37 stores fixed data.

This conventional DSP performs an encoding / decoding process by performing an arithmetic operation with an arithmetic unit such as a multiplier 31, a shifter / normalizer 32 and an ALU 33 according to the contents of an instruction ROM 35 indicated by an instruction pointer 34. It was a configuration to do.

[0004]

However, in the above-described conventional configuration, the general audio signal sample interval is 12
Both the encoding / decoding process must be performed within 5 microseconds by using one system of multiplier 31, shifter / normalizer 32 and ALU 33, so DSP must operate at a relatively high speed. . However, DSPs are generally made using CMOS devices, and the power consumption of CMOS devices is proportional to the operating frequency. Therefore, there is a problem that power consumption increases when encoding / decoding processing is performed by the conventional processor.

The present invention has been made in view of the above circumstances, and provides a processor control method and a processor capable of suppressing an increase in power consumption when a plurality of processes such as encoding / decoding processes are performed in parallel. The purpose is to provide.

[0006]

According to a first aspect of the present invention, an instruction is provided with a field for designating an arithmetic unit for executing the instruction, and a single arbitrary number of arithmetic units specified from a plurality of arithmetic units by one instruction. It is characterized by operating only. According to the invention of claim 2, a field is provided in an instruction to specify an arithmetic unit that executes the instruction, and one instruction operates only a specific arbitrary number of arithmetic units from a plurality of arithmetic units. It has a feature.

According to a third aspect of the present invention, an instruction has a field for designating an arithmetic unit to be subjected to a branch condition judgment, and a single instruction has an arithmetic result state of an arbitrary number of arithmetic units among a plurality of arithmetic units. The feature is that the branching operation that reflects only is performed. According to the invention of claim 4, a field for designating an arithmetic unit to be a branch condition judgment target is provided in the instruction, and only one arithmetic operation result state of a specific arbitrary number of arithmetic units among a plurality of arithmetic units is reflected by one instruction. It is characterized in that the branching operation is performed.

According to a fifth aspect of the present invention, processing procedure storing means for storing the processing procedure, control means for outputting a control signal based on the output from the processing procedure storing means, and an instruction by the control signal from the controlling means are provided. And a plurality of data storages for storing the operation data corresponding to each of the operation means, and operating based on the address signal and the instruction by the control signal from the control means. Means and address instruction means for outputting a common address signal to the plurality of data storage means based on an instruction by a control signal from the control means.

According to a sixth aspect of the present invention, based on an instruction memory that stores an instruction, an instruction pointer that outputs an address signal to the instruction memory, and the contents described in the instruction by decoding the output of the instruction memory. An instruction decoder that outputs a control signal, a plurality of arithmetic units controlled by the control signals from the instruction decoder, data corresponding to each of these arithmetic units, data is stored, and an address signal and a control signal from the instruction decoder are stored. And a data pointer controlled by a control signal from the instruction decoder to output an address signal common to all of the plurality of data memories.

According to a seventh aspect of the present invention, an instruction decoder selects a specific arithmetic unit described in an instruction from a plurality of arithmetic units, judges the state thereof, and branches if a branch condition is satisfied. Is characterized by being configured to point to the instruction pointer.

[0011]

According to the first aspect of the present invention, an instruction is provided with a field for designating an arithmetic unit for executing the instruction, and one instruction operates only a specific arbitrary number of arithmetic units among a plurality of arithmetic units. According to the second aspect of the present invention, a field is provided in the instruction to specify the arithmetic unit that executes the instruction, and one instruction operates only a specific arbitrary number of arithmetic units from the plurality of arithmetic units.

According to the third aspect of the present invention, an instruction has a field for designating an arithmetic unit to be a branch condition judgment target, and one instruction gives an arithmetic result of an arbitrary number of arithmetic units among a plurality of arithmetic units. The branch operation that reflects only the status is performed. According to the invention of claim 4, a field for designating an arithmetic unit to be a branch condition judgment target is provided in the instruction, and only one arithmetic operation result state of a specific arbitrary number of arithmetic units is selected from a plurality of arithmetic units by one instruction. Perform the reflected branch operation.

In the invention of claim 5, the processing procedure storing means stores the processing procedure. The control means outputs a control signal based on the output from the processing procedure storage means. The plurality of calculation means performs calculation based on an instruction given by a control signal from the control means. The plurality of data storage means store the calculation data corresponding to each of the plurality of calculation means, and operate based on the address signal and the instruction by the control signal from the control means. The address instructing means outputs a common address signal to the plurality of data storage means based on an instruction by the control signal from the control means.

In the invention of claim 6, the instruction memory is
Memorize instructions. The instruction pointer outputs an address signal to the instruction memory. The instruction decoder decodes the output of the instruction memory and outputs a control signal based on the contents described in the instruction. The plurality of arithmetic units are controlled by the control signal from the instruction decoder. Multiple data memories
Data is stored corresponding to each of the plurality of arithmetic units and controlled by an address signal and a control signal from the instruction decoder. The data pointer is controlled by a control signal from the instruction decoder and outputs an address signal common to all the plurality of data memories.

According to a seventh aspect of the invention, the instruction decoder selects a specific arithmetic unit described in the instruction from a plurality of arithmetic units, judges its state, and branches if a branch condition is satisfied. To the instruction pointer.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a processor according to an embodiment of the present invention. The processor includes an instruction pointer 1, an instruction memory 2, an instruction register 3, an instruction decoder 4, and an instruction decoder 4.
A first operation system 5, a second operation system 6, and a data pointer 7 are provided. The first operation system 5 includes a first operation unit 9 and a first operation unit 9.
The second arithmetic system 6 includes a second arithmetic unit 11 and a second data memory 12. The instruction pointer 1 supplies an address signal to the instruction memory 2. The instruction memory 2 stores instructions. The instruction register 3 temporarily holds the instruction from the instruction memory 2. The instruction decoder 4 decodes the instruction from the instruction register 3 and sends the first operation system control signal to the first operation system 5 and the second operation system control signal.
The operation system 6 is supplied with a second operation system control signal, and the data pointer 7 is supplied with a control signal. Further, the instruction decoder 4 decodes the instruction from the instruction register 3, the operation result state signal from the first operation unit 9 and the operation result state signal from the second operation unit 11, and when performing a program branch, the instruction A control signal is supplied to the pointer 1 to instruct to fetch the branch address from the instruction register 3.
The data pointer 7 includes a first data memory 10 and a second data memory 10.
An address signal is supplied to the data memory 12. The first arithmetic unit 9 performs an arithmetic operation on the contents of the first data memory 10 based on the first arithmetic system control signal from the instruction decoder 4. The second operation unit 11 performs an operation on the content of the second data memory 12 based on the second operation system control signal from the instruction decoder 4. The first data memory 10 receives the address signal from the data pointer 7 and receives the first operation unit 9 based on the first operation system control signal from the instruction decoder 4.
The data is output to and the data is received from the first calculation unit 9. The second data memory 12 is supplied with the address signal from the data pointer 7, outputs data to the second operation unit 11 based on the second operation system control signal from the instruction decoder 4, and also outputs the second operation unit 11 to the second operation unit 11. Receive data from.

FIG. 2 is an explanatory diagram of the instruction format. The operation designation field of the operation instruction is decoded by the instruction decoder 4, so that the instruction decoder 4 controls the first operation system 5 and the second operation system 6 by the first operation system. The signal and the second operation system control signal are output. The data pointer control field is decoded by the instruction decoder 4, so that the instruction decoder 4 outputs a control signal to the data pointer 7.
The first operation system designation bit is determined by the instruction decoder 4, and only when this bit is 1, the instruction decoder 4 outputs the first operation system control signal. The second operation system designation bit is determined by the instruction decoder 4, and only when this bit is 1, the instruction decoder 4 outputs the second operation system control signal. The branch designation field of the branch instruction is determined by the instruction decoder 4, and the instruction decoder 4 determines that this instruction is a branch instruction based on this field. The branch condition field specifies the branch condition. As the branching condition, an operation result status signal indicating the sign of the operation result and the zero determination result by the first operation unit 9 or an operation result status signal from the second operation unit 11 is used. Which operation result status signal is used? Whether to use is specified by the first operation system specifying bit and the second operation system specifying bit. The branch destination address is given from the instruction register 3 to the instruction pointer 1.

Next, the operation will be described. Now, the first operation system 5
Consider the case where the processing shown in FIG. 3 is performed by the second operation system 6. In this case, it is the third processing "2" that the different processing is performed between the first calculation system 5 and the second calculation system 6.
"Addition using address data" and "addition using address data 3" are the only other processings are the same in the first operation system 5 and the second operation system 6. In the concrete ADPCM codec processing, the encoding processing is performed by the first arithmetic system 5,
Decoding processing is performed by the second operation system 6. This is because the ADPCM codec locally performs exactly the same processing as the decoding processing during the coding processing, so that the coding processing and the decoding processing can proceed at the same time. When the processing shown in FIG. 3 is performed, the arithmetic instructions shown in FIG. 2 are stored in the instruction memory 2 in advance as shown in FIG. Figure 4
11, 10, 01 in each instruction 401 to 405 shown in
2, the left side bit corresponds to the second operation system specifying bit in FIG. 2, and the right side bit corresponds to the first operation system specifying bit in FIG. The instruction 401 at address 10 in FIG. 4 corresponds to the first process in FIG. 3, the instruction 402 at address 11 in FIG. 4 corresponds to the second process in FIG. 3, and the instruction at address 12 in FIG. 403 corresponds to the third processing of the first operation system 5 in FIG. 3, and the instruction 404 at address 13 in FIG. 4 is the second operation system 6 in FIG.
Corresponding to the third processing of the instruction 40 at the address 14 in FIG.
Reference numeral 5 corresponds to the fourth processing in FIG.

First, when the instruction pointer 1 points to the address 10, the instruction 401 at the address 10 is output from the instruction memory 2 and is latched in the instruction register 3. The instruction 4
01 is decoded by the instruction decoder 4, but the instruction 40
Since both the first operation system specifying bit and the second operation system specifying bit of 1 are 1, the instruction decoder 4 supplies the first operation system control signal to the first operation system 5 and the second operation system 6 To the second operation system control signal. Further instruction decoder 4
Instructs the data pointer 7 to decode the data pointer control field and output an address signal of 0. As a result, the first operation system 5 performs the addition processing by the first operation unit 9 using the data at the address 0 of the first data memory 10, and the second operation system 6 performs the second operation by the second operation unit 11. An addition process is performed using the data at address 0 of the data memory 12.

Thereafter, the instruction pointer 1 is incremented to be 11, and the first operation system 5 uses the data at the first address of the first data memory 10 by the first operation unit 9 in the same manner as described above. In the second operation system 6, the second operation unit 11 uses the data at address 1 of the second data memory 12 to perform the respective operations. Instruction pointer 1 after this
Is incremented to be 12, but the instruction memory 2
Since the instruction 403 at address 12 has only the first operation system designation bit being 1, only the first operation system control signal is supplied from the instruction decoder 4 to the first operation system 5. Therefore, the first operation system 5
Is used, and the first arithmetic unit 9 uses the data at address 2 of the first data memory 10 to perform the addition. During this time, the second operation system signal is not output, so the second operation system 6
In this case, no operation is performed, which is a so-called no operation.

After this, the instruction pointer 1 is incremented to 13 but the instruction 40 at the address 13 of the instruction memory 2 is incremented.
Contrary to the address 12, 4 has only the second operation system designation bit of 1, so that the addition is performed only in the second operation system 6. After this, the instruction pointer 1 is incremented to 14, but the instruction 405 at the address 14 of the instruction memory 2 has both the first operation system designating bit and the second operation system designating bit 1, so that the instruction memory 1 is again stored in the first memory. Both the 1st operation system 5 and the 2nd operation system 6 perform operations.

FIG. 5 shows a processing flow in which the above-described operations are arranged in time series. The instruction memory 2 stores only one program shown in FIG.
1, 402 and 405 are shared by the first operation system 5 and the second operation system 6 and executed. At this time, the first data memory 10 and the second data memory 12, which are separate memories, are used as the data memories, but the addresses are shared by the data pointer 7 and given the same address.

Next, the operation of the branch instruction shown in FIG. 2 will be described. When a branch instruction is stored in the instruction register 3, the instruction decoder 4 knows from the branch designation field that this instruction is a branch instruction. Then, the instruction decoder 4 judges the operation result status signal from the first operation system 5 or the second operation system 6 specified by the first operation system specifying bit and the second operation system specifying bit according to the condition indicated by the branch condition field. To do.
When branching as a result of the determination, the instruction decoder 4 supplies a control signal to the instruction pointer 1 to instruct the instruction pointer 1 to fetch the branch address from the instruction register 3, and thus branching is performed.

The instruction memory 2 for storing the instructions in this way
An instruction pointer 1 that outputs an address signal to the instruction memory 2, an instruction decoder 4 that decodes the output of the instruction memory 2 and outputs a control signal based on the contents described in the instruction, Data is stored corresponding to each of the first arithmetic unit 9 and the second arithmetic unit 11 controlled by the control signal, and the first arithmetic unit 9 and the second arithmetic unit 11, and the control from the address signal and the instruction decoder 4 is performed. An address signal common to both the first data memory 10 and the second data memory 12 which is controlled by a signal, and an address signal which is controlled by the control signal from the instruction decoder 4 and is common to both the first data memory 10 and the second data memory 12. Since the data pointer 7 for outputting is provided, by outputting the control signal from the instruction decoder 4 to the first operation system 5 or the second operation system 6 described in the instruction, Simultaneous processing of operations by the first computing system 5 and the second operation system 6, as well as independent processing in the two operation system 5,6 as needed can be easily. Therefore, the first
The operation speed of the processor can be slowed down compared to the case where the processing contents processed by the arithmetic system 5 and the processing contents processed by the second arithmetic system 6 are performed sequentially by one arithmetic system, and the system is a CMOS device. If it is built in, its power consumption can be satisfactorily reduced.

[0025]

As described above, according to the present invention, the processing procedure storage means for storing the processing procedure, the control means for outputting a control signal based on the output from the processing procedure storage means, and the control means A plurality of arithmetic means for performing an arithmetic operation based on an instruction by a control signal and arithmetic data corresponding to each of the plurality of arithmetic means are stored, and an operation is performed based on an address signal and an instruction by the control signal from the control means. Since there are provided a plurality of data storage means for performing and an address designating means for outputting a common address signal to the plurality of data storage means based on an instruction by a control signal from the control means, calculation by a plurality of computing means Simultaneous processing of the above, and independent processing by each arithmetic means as required can be easily performed. Therefore, the operation speed of the processor can be slowed down as compared with the case where the processing contents by a plurality of arithmetic means are sequentially performed by one arithmetic means, and the power consumption is reduced when the system is constructed by CMOS devices. It can be reduced well.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an instruction format of a processor.

FIG. 3 is an explanatory diagram of processing by a processor according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of contents of an instruction memory.

FIG. 5 is an explanatory diagram of a flow of operation of the processor in the embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional processor.

[Explanation of symbols]

 1 Instruction Pointer 2 Instruction Memory 4 Instruction Decoder 7 Data Pointer 9 First Operation Unit 10 First Data Memory 11 Second Operation Unit 12 Second Data Memory

Claims (7)

[Claims] 1. A processor, characterized in that an instruction is provided with a field for designating an arithmetic unit for executing the instruction, and that a single instruction operates only a specific arbitrary number of arithmetic units among a plurality of arithmetic units. Control method. 2. An instruction is provided with a field for designating an arithmetic unit that executes the instruction, and one instruction operates only a specific arbitrary number of arithmetic units from a plurality of arithmetic units. The processor to do. 3. A branch in which an instruction is provided with a field for designating an arithmetic unit to be subjected to branch condition determination, and a single instruction reflects only the arithmetic result state of a specific arbitrary number of arithmetic units among a plurality of arithmetic units. A method of controlling a processor characterized by causing an operation. 4. A branch in which an instruction is provided with a field for designating an arithmetic unit to be a branch condition judgment target, and a single instruction reflects only the operation result state of a specific arbitrary number of arithmetic units among a plurality of arithmetic units. A processor characterized by being configured to perform operations. 5. A processing procedure storage means for storing a processing procedure, a control means for outputting a control signal based on an output from the processing procedure storage means, and an operation based on an instruction by the control signal from the control means. A plurality of calculation means to perform, a plurality of data storage means for storing the calculation data corresponding to each of the plurality of calculation means, to perform an operation based on an address signal and an instruction by a control signal from the control means; An address instruction means for outputting a common address signal to the plurality of data storage means based on an instruction by a control signal from the control means. 6. An instruction memory for storing an instruction, an instruction pointer for outputting an address signal to the instruction memory, a decode of an output of the instruction memory, and a control signal output based on the contents described in the instruction. An instruction decoder, a plurality of arithmetic units controlled by control signals from the instruction decoder, data corresponding to each of the plurality of arithmetic units, data is stored, and controlled by an address signal and a control signal from the instruction decoder. A plurality of data memories, and a data pointer controlled by a control signal from the instruction decoder to output an address signal common to all the plurality of data memories. 7. The instruction decoder selects a specific arithmetic unit described in an instruction from a plurality of arithmetic units and judges the state thereof, and if the branch condition is satisfied, instructs the instruction pointer to perform a branch operation. 7. The structure according to claim 6, wherein
Processor described in.