JP2006012185A - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an instruction is executed as a non-operation instruction, use efficiency of hardware is poor and effective performance is lowered when conditions are not established in a conditional execution instruction. <P>SOLUTION: A processor decodes the number of instructions equal to or more than the number of mounted arithmetic units, decides executing conditions by an instruction issuance control part 31 before an execution stage, as regards an instruction whose conditions are false, invalidates the instruction itself, and performs allocation so that the arithmetic units (hardware) are effectively used by the succeeding valid instructions. A compiler performs scheduling so that the number of instructions whose executing conditions become true does not exceed the upper limit of parallelism of the hardware. The number of instructions itself to be arranged in parallel in each cycle can exceed the parallelism of the hardware. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a processor, and more particularly to a technique for improving performance by using an arithmetic unit efficiently in parallel processing.

  2. Description of the Related Art Along with high functionality and high speed of recent microprocessor application products, a microprocessor having high processing performance (hereinafter simply referred to as “processor”) is desired. In general, in order to increase the throughput of each instruction, one instruction is divided into several processing units (herein referred to as “stages”), and each stage is executed by separate hardware. A pipeline system that allows parallel processing is adopted. In addition to the spatial parallel processing such as the pipeline method, the VLIW (Very Long Instruction Word) method or the superscalar method that performs parallel processing at the instruction level in terms of time is intended to improve performance.

  One of the main factors that hinders improvement in processor performance is branch processing overhead. This overhead increases the penalty of instruction supply as the number of stages of the pipeline processing increases. Further, when instruction parallel processing is performed, the higher the degree of parallelism, the more frequently the branch instruction increases and the overhead becomes obvious.

  Therefore, as a conventional technique for eliminating this overhead, there is a conditional execution method in which information indicating an execution condition is added to each instruction, and an operation indicated by the instruction is executed only when the condition is satisfied. In this method, a condition flag corresponding to an execution condition added to each instruction at the time of execution is referred to. If the condition is not satisfied, the execution result of the instruction is invalidated, that is, executed as a no-operation instruction. .

  For example, if the processing of the flow including the conditional branch shown in FIG. 10 is described by a method in which information indicating the execution condition is added to each instruction, a program as shown in FIG. 11 is obtained. In FIG. 11, C0 and C1 indicate conditions added to the instruction. When the value of the corresponding condition flag is true, the instruction is executed, and when it is false, the instruction is an inoperative instruction. Run as. In this example, the comparison result of instruction 1 (comparison instruction) is first stored in C0. At the same time, a condition opposite to C0 is set for C1. Therefore, the operation is actually executed for one of the instruction 2 and the instruction 3, and the remaining one is executed as a no-operation instruction. As a result, branch processing becomes unnecessary, and the overhead of branch processing is solved.

  In the above-described conventional conditional execution method, if the condition is not satisfied, the instruction operates as a no-operation instruction, and the operation is not actually executed. Therefore, even though two instructions are described in parallel and two arithmetic units are used, only one arithmetic unit can be effectively used in practice. As a result, there is a problem that the effective performance is lowered with respect to the degree of parallelism described in the program.

  The present invention has been made in view of such problems, and an object thereof is to provide a processor that achieves effective use of hardware and has improved performance.

  In order to achieve the above object, a processor having the first feature of the present invention comprises: an instruction supply means for supplying a plurality of instructions; a decoding means for decoding each of the plurality of instructions; Execution condition information specifying a condition indicating whether or not to execute each instruction is specified in the instruction, and an instruction or a set of instructions for executing a valid operation is referred to by referring to the condition specified by the execution condition information. In a processor, comprising: an instruction issuance control means for determining; and an execution means for specifying an operation of each instruction in the plurality of instructions and executing one or a plurality of operations based on the specification. The instruction issuance control means determines whether the instruction is a valid instruction that needs to be executed or an invalid instruction that does not need to be executed by referring to the condition specified by the execution condition information. With respect to an instruction determined to be an invalid instruction, control is performed to delete the instruction itself before issuing the instruction to the execution means, and a valid instruction subsequent to the instruction is substituted for the instruction. It has a function to control to issue to the execution means. As a result, even when the condition of the conditional instruction is not satisfied, the no-operation instruction is not executed, and the arithmetic unit in the execution means is effectively used by the subsequent instruction. Can be improved.

  In the processor having the first feature of the present invention, the execution means includes execution result invalidation means for invalidating the execution result after executing the operation corresponding to the instruction. The instruction invalidation method selection means for selecting whether to delete the instruction itself before issuing to the execution means or invalidate the execution result by the execution result invalidation means. . This eliminates the need to stop the processor pipeline even when the condition flag used for execution condition determination is uncertain, and can improve performance.

  Further, in the processor having the first feature of the present invention, the instruction invalidation method selecting means refers to any instruction by referring to the condition flag valid information indicating whether or not the value of each condition flag is fixed. Decide whether to select an invalidation method, and if the condition flag validity information is decoded by the decoding means as an instruction to update the condition flag, the determinism of the condition flag is set to false and the execution When the instruction is executed by the means and the value of the condition flag is fixed, the value is set to true.

  In the processor having the first feature of the present invention, the instruction issuance control means detects a combination of instructions such that the functions of a plurality of instructions can be realized by a single instruction, and outputs the plurality of instructions. It is further provided with a function of combining such that it is handled as a single instruction. As a result, an instruction originally intended to use a plurality of arithmetic units can be executed by a single arithmetic unit, the utilization efficiency of the arithmetic units can be increased, and the effective performance can be improved.

  In the processor having the first feature of the present invention, the combination of the plurality of instructions is applied after the instruction is deleted before being issued to the execution means.

  In the processor having the first feature of the present invention, the instruction issuance control means is decoded by the decoding means when instructions having the same execution condition information are continuously arranged in each cycle. A plurality of instructions are classified in advance for each execution condition, and a condition flag is referenced for each classification to determine whether the instruction is a valid instruction that needs to be executed or an invalid instruction that does not need to be executed. It was decided. As a result, reference to the condition flag can be minimized, and the time required for determining instruction deletion can be reduced.

  In the processor having the first feature of the present invention, parallel execution boundary information indicating whether each instruction is a boundary for parallel execution is specified in the plurality of instructions, and the instruction issue control means Referring to the parallel execution boundary information, a function for detecting an instruction group to be executed in this cycle is further provided.

  Further, in the processor having the first feature of the present invention, the instruction issuance control means is an invalid instruction that does not need to be executed by all instructions before the boundary instruction detected by the parallel execution boundary information in the instruction. When deleted, the parallel execution boundary information of the boundary instruction is invalidated, and the new parallel execution boundary of the cycle is detected by referring to the parallel execution boundary information of the instruction after the boundary instruction. As a result, if all instructions placed in a cycle are deleted, the cycle itself can be skipped and the next cycle instruction can be executed, reducing the number of execution cycles. Can do.

  A processor having the second feature of the present invention includes an instruction supply means for supplying a plurality of instructions, a decoding means for decoding each of the plurality of instructions, and an instruction or a set of instructions for executing an effective operation. A processor comprising: an instruction issuance control means for determining the operation; and an execution means for specifying the operation of each instruction in the plurality of instructions and executing one or more operations based on the specification. The instruction issuance control means detects a combination of instructions such that a function of a plurality of instructions can be realized by a single instruction from the group of instructions decoded by the decoding means, and determines the plurality of instructions. It has a function of combining them so that they are handled as a single instruction. As a result, instructions that were originally scheduled to use multiple arithmetic units in the execution means can be executed by a single arithmetic unit, so that the utilization efficiency of the arithmetic units is increased and the effective performance is improved. Can do.

  In the processor having the second feature of the present invention, the instruction issuance control means detects a group of instructions that remain in the cycle without being executed, deleted or combined, and It is further provided with a function of controlling the instruction group to be issued in the next cycle. As a result, even if there is an instruction that is not issued in a certain cycle due to the occurrence of an exception or a failure of the compiling device, the execution can be continued accurately without causing a malfunction.

  According to the present invention, it is possible to provide a processor that achieves effective use of hardware and improves performance.

  Embodiments of a processor, a compiling device, and a compiling method according to the present invention will be described below in detail with reference to the drawings.

[Embodiment 1: Processor]
(Instruction format and architecture overview)
First, the structure of an instruction that is decoded and executed by the processor according to the present invention will be described with reference to FIGS. 1A to 1C are diagrams showing the instruction format of the processor. Each instruction of this processor has a fixed length of 32 bits, and each instruction holds 1-bit parallel execution boundary information (E: end bit) 10. This information indicates whether or not there is a parallel execution boundary between the instruction and the subsequent instruction. Specifically, when the parallel execution boundary information E is “1”, a parallel execution boundary exists between the instruction and the subsequent instruction, and when the parallel execution boundary information E is “0”, the parallel execution is performed. There will be no boundaries. A method of using this information will be described later.

  Each instruction holds 3-bit execution condition information (P: predicate) 11. The execution condition information P designates a condition flag in which a condition indicating whether or not to execute the instruction is stored among eight condition flags C0 to C7 (311) in FIG. 5 to be described later. When the value of the condition flag specified by the execution condition information P is “1”, the operation specified by the instruction is executed, and when the value of the condition flag is “0”, the operation is not executed.

  The operation is specified by a 28-bit portion obtained by removing the parallel execution boundary information E and the execution condition information P from the instruction length of each instruction. Specifically, in the “Op1”, “Op2”, and “Op3” fields, an operation code indicating the type of operation is displayed. In the “Rs” field, the register number of the register that is the source operand is set in the “Rd” field. Specifies the register numbers of the registers that will be the destination operands. In the “imm” field, an arithmetic constant operand is designated. In the “disp” field, a displacement is specified.

  Next, an outline of the architecture of the processor will be described with reference to FIGS. This processor is a processor premised on static parallel scheduling.

  As shown in FIG. 2A, four instructions are supplied in units of instruction supply units each having a fixed length of 128 bits (referred to herein as “packets”). As shown in FIG. 2B, the instructions are executed by executing instructions up to the boundary of parallel execution (referred to herein as “execution units”) in one cycle. That is, instructions up to the instruction whose parallel execution boundary information E is “1” are executed in parallel in each cycle. An instruction that has been supplied but not executed remains in the instruction buffer and becomes an object to be executed after the next cycle.

  In other words, in this architecture, instructions are supplied in units of fixed-length packets, and an appropriate number of instructions according to the degree of parallelism is issued in each cycle based on statically obtained information. become. By adopting this method, the no-operation instruction (nop instruction) generated in the normal fixed-length instruction VLIW method is completely eliminated, and the code size can be reduced.

(Processor hardware configuration)
FIG. 3 is a block diagram showing the hardware configuration of the processor according to the present invention. This processor is a parallel execution processor having two arithmetic units, and is roughly composed of an instruction supply unit 20, a decoding unit 30, and an execution unit 40.

  The instruction supply unit 20 supplies an instruction group from an external memory (not shown) and outputs the instruction group to the decoding unit 30. The instruction supply unit 20 includes an instruction fetch unit 21, an instruction buffer 22, and an instruction register 23.

  The instruction fetch unit 21 fetches a block of instructions from an external memory (not shown) through a 32-bit IA (instruction address) bus and a 128-bit ID (instruction data) bus, and holds the block in an internal instruction cache. An instruction group corresponding to the address output from the (program counter) unit 42 is supplied to the instruction buffer 22.

  The instruction buffer 22 includes two 128-bit buffers, and is used to store instructions supplied by the instruction fetch unit 21. Packets are supplied to the instruction buffer 22 from the instruction fetch unit 21 in units of 128 bits. The instruction stored in the instruction buffer 22 is output to an appropriate register of the instruction register 23.

  The instruction register 23 includes four 32-bit registers 231 to 234, and is used to hold an instruction sent from the instruction buffer 22. The configuration around the instruction register 23 is shown in more detail in another drawing.

  The decoding unit 30 decodes the instruction held in the instruction register 23, and outputs a control signal corresponding to the decoding result to the execution unit 40, and is roughly divided into an instruction issue control unit 31, an instruction decoder 32, and An instruction invalidation method selection unit 38 is included.

  The instruction issuance control unit 31 refers to the execution condition information P in the instruction and the condition flag corresponding to the instruction held in the four registers 231 to 234 of the instruction register 23, thereby obtaining the condition flag. For an instruction whose value is false, processing is performed such that the instruction itself is substantially deleted. However, only when the decoding unit 30 is selected by the instruction invalidation method selection unit 38. The instruction issuance control unit 31 controls the issuance of an instruction that invalidates the issuance of an instruction that exceeds the boundary of parallel execution by referring to the parallel execution boundary information E in the instruction. The instruction issue control unit 31 will be described in more detail in another drawing.

  The instruction decoder 32 is a device that decodes the instruction group stored in the instruction register 23, and includes a first instruction decoder 33, a second instruction decoder 34, a third instruction decoder 35, and a fourth instruction decoder 36. Each of these decoders 33 to 36 basically decodes one instruction in one cycle and gives a control signal to the execution unit 40. Also, the constant operand placed in the instruction is transferred from each instruction decoder to the data bus 48 of the execution unit 40.

  The instruction invalidation method selection unit 38 selects whether an instruction that has a condition flag set to false and does not need to be executed is invalidated by the decoding unit 30 or invalidated by the execution unit 40. Specifically, when the condition flag validity information 312 (FIG. 5) of the instruction issuance control unit 31 to be described later indicates that the condition flag of the instruction is valid, that is, confirmed, the decoding unit The invalid instruction is deleted at 30, and if not, the writing control unit 46 of the execution unit 40 invalidates the writing of the execution result of the instruction.

  The execution unit 40 is a circuit unit that executes a maximum of two operations in parallel based on the decoding result of the decoding unit 30, and includes an execution control unit 41, a PC unit 42, a register file 43, a first computing unit 44, a second computing unit 44, It comprises an arithmetic unit 45, a write control unit 46, an operand access unit 47, and data buses 48 and 49.

  The execution control unit 41 is a general term for control circuits and wirings that control the constituent elements 42 to 49 of the execution unit 40 based on the decoding result of the decoding unit 30. Timing control, operation permission prohibition control, status management, interrupt It has circuits such as control.

  The PC unit 42 outputs an address in an external memory (not shown) where an instruction to be decoded and executed next is placed to the instruction fetch unit 21 in the instruction supply unit 20.

  The register file 43 is composed of 64 32-bit registers (R0 to R63). The values stored in these registers are transferred to the first computing unit 44 and the second computing unit 45 via the data bus 48 based on the result of decoding by the instruction decoder 32, where they are operated, or After simply passing there, it is sent to the register file 43 or the operand access unit 47 via the data bus 49.

  Each of the first computing unit 44 and the second computing unit 45 includes an ALU and a multiplier that perform arithmetic logic operations on two 32-bit data, and a barrel shifter that performs shift operations, and the execution control unit 41. The calculation is executed under the control of.

  Only when the instruction invalidation method selection unit 38 selects to invalidate a certain instruction by the execution unit 40, the write control unit 46, when the content of the condition flag of the instruction is false, Control is performed so that the execution result is not written to the register file 43. As a result, with respect to the instruction, a result equivalent to that obtained when a no-operation instruction (nop instruction) is executed is obtained.

  The operand access unit 47 is a circuit that transfers operands between the register file 43 and an external memory (not shown). Specifically, for example, when “ld” (load) is placed as an operation code in an instruction, 1 word (32 bits) of data placed in the external memory passes through the operand access unit 47. When the data is loaded to the designated register of the register file 43 and “st” (store) is placed as the operation code, the stored value of the designated register of the register file 43 is stored in the external memory.

  The PC unit 42, register file 43, first computing unit 44, second computing unit 45, write control unit 46, and operand access unit 47 include a data bus 48 (L1 bus, R1 bus, L2 bus), as shown. , R2 bus) and data bus 49 (D1 bus, D2 bus). The L1 bus and R1 bus are connected to the two input ports of the first computing unit 44, the L2 bus and R2 bus are connected to the two input ports of the second computing unit 45, and the D1 bus and D2 bus are connected to the first computing unit 44 and Each is connected to the output port of the second computing unit 45.

(The peripheral configuration of the instruction register 23 and the operation of the instruction issuance control unit 31)
FIG. 4 is a block diagram showing a configuration around the instruction register 23. In the figure, broken arrows represent control signals.

  The instruction register 23 includes four 32-bit registers, an A register 231, a B register 232, a C register 233, and a D register 234. An instruction is supplied from the instruction buffer 22 to the instruction register 23.

  The first to fourth instruction decoders 33, 34, 35, and 36 each receive a 32-bit instruction, decode it, output a control signal relating to the operation of the instruction, and constants arranged in the instruction Output the operand. Reference numerals 50 and 51 in FIG. 4 denote constant operands of instructions whose execution has been determined.

  Further, a 1-bit no-operation instruction flag is input to the second to fourth instruction decoders 34, 35, and 36 as a control signal. When this flag is set to “1”, the decoder outputs a control signal corresponding to a no-operation command as an output. That is, by setting the no-operation instruction flag, the decoding of the instruction decoder can be invalidated.

  Then, the instruction issuance control unit 31 refers to the information in the instruction stored in the instruction register 23, generates a no-operation instruction flag for invalidating the decoding of the instruction after the parallel execution boundary, and the execution condition Of the execution instruction selectors 371 and 372 for selecting a valid instruction to be executed by the execution unit 40 and the execution instruction selectors 373 and 374 for selecting a control signal corresponding thereto. Control.

  FIG. 5 shows the configuration of the instruction issue control unit 31 and its peripheral circuits of this processor. The instruction issuance control unit 31 first refers to the parallel execution boundary information E in each instruction and determines how many instructions are to be issued in this cycle. Then, by setting the no-operation instruction flag of the instruction decoder corresponding to the instruction not issued in this cycle to “1”, the output of the decoder is made a control signal corresponding to the no-operation instruction. The generation of the no-operation instruction flag can be realized by a simple logic circuit (OR gate) 314, 315 as shown in the right half of the instruction issuance control unit 31 in FIG. At the same time, information on how many instructions remain without being issued is transmitted to the instruction buffer 22.

  More specifically, when the parallel execution boundary information E of the instruction in the A register 231 is “1”, the decoding of the second, third, and fourth instruction decoders 34, 35, and 36 is invalidated. If the parallel execution boundary information E of the instruction in the B register 232 is “1”, the decoding of the third and fourth instruction decoders 35 and 36 is invalidated. When the parallel execution boundary information E of the instruction in the C register 233 is “1”, the decoding of the fourth instruction decoder 36 is invalidated.

  Further, the instruction issuance control unit 31 refers to the execution condition information P in each instruction, and substantially deletes the instruction itself with respect to an instruction whose condition flag is false, that is, an instruction that does not need to be executed. The execution instruction selectors 371 to 374 in FIG. 4 are controlled. In this processor, a maximum of 4 instructions are decoded in each cycle, but the operation is actually executed at most 2 instructions. This solves the problem that when the execution condition is false, the non-operation instruction is executed in the execution unit 40, and the utilization efficiency of the computing units 44 and 45 is deteriorated.

  In order to realize this, the instruction issuance control unit 31 includes an execution instruction selection control unit 313. The execution instruction selection control unit 313 refers to the condition flag corresponding to the execution condition information P specified in the instruction among the eight condition flags (C0 to C7) 311 so that the operation does not need to be executed. The execution instruction selectors 371 to 374 are controlled so as to select the succeeding effective instruction without selecting the instruction. The unselected instruction itself will be substantially deleted. The condition flag 311 includes eight 1-bit registers C0 to C7, and is designated by decoding the 3-bit execution condition information P in each instruction. However, the value of the condition flag C7 is always “1”, and an instruction that is always executed designates C7 as an execution condition. Specification of C7 can be omitted in the description in the program.

  However, in the instruction that updates the condition flag, it is the execution stage, that is, the execution unit 40 that determines the condition flag. Therefore, if an instruction that updates a certain condition flag is executed in the previous cycle, the decoding stage of the next cycle, that is, The condition flag is not fixed in the decoding unit 30, and it cannot be determined whether or not the instruction can be deleted. In order to detect this state, condition flag valid information 312 is provided.

  The condition flag validity information 312 holds a 1-bit value indicating whether or not the value is valid for each condition flag, and the decoding unit 30 executes an instruction to update a certain condition flag. In this case, the valid information of the condition flag is set to “0”, and when the execution unit 40 completes updating the value of the condition flag, the valid information of the condition flag is set to “1”.

  The instruction issuance control unit 31 refers to the execution condition information P of each instruction and then refers to the condition flag validity information 312 to detect whether or not the value of the condition flag corresponding to each execution condition is valid. If it is not valid, that is, if the corresponding bit of the condition flag valid information 312 is “0”, the instruction itself is not deleted. The instruction is issued to the execution unit 40 as it is, and when the condition flag is fixed, writing of the execution result of the instruction is invalidated if necessary.

  When the value of the condition flag is valid, that is, when the corresponding bit of the condition flag validity information 312 is “1”, the 1 bit in the condition flag 311 designated by the execution condition information P of the instruction is referred to. When the value is “1”, the instruction is issued as it is to the execution unit 40, and when the value is “0”, the instruction itself is substantially deleted. The selectors 371 to 374 are controlled.

  That is, when the execution condition information P of a certain instruction is “0”, if the corresponding condition flag is updated in the immediately preceding instruction, the execution unit 40 invalidates the execution result of the instruction. In the decoding unit 30, the instruction itself is substantially deleted.

  FIG. 6 is a diagram showing the timing of pipeline processing when a specific instruction sequence is executed. Here, it is assumed that three instructions are executed one by one in order from the top. The first instruction is a comparison instruction that compares the contents of the register R0 with the contents of the register R1, sets "1" to the condition flag C0 if they match, and sets "0" otherwise. The next instruction is a subtraction instruction that subtracts the contents of the register R2 from the contents of the register R3 and writes the result to the register R3 only when the contents of the condition flag C0 is “1”. Only when the content of the flag C0 is “1”, this is an addition instruction for adding the content of the register R4 and the content of the register R5 and writing the result to the register R5.

  In FIG. 6, the timing of the instruction fetch stage (IF), decoding stage (DEC), and execution stage (EX) of each instruction is shown on the right side of each instruction. Here, it is assumed that the result of the first comparison instruction is false, that is, C0 becomes “0”.

  As can be seen from FIG. 6, at the decoding stage (DEC) of the first comparison instruction, it is detected that the instruction is to update C0, the valid information of C0 is set to “0”, and the execution stage (EX ), After the comparison result is confirmed, the valid information of C0 is set to “1”.

  Both the subsequent subtraction instruction and the addition instruction are executed under the condition of C0. However, for the subtraction instruction immediately after the comparison instruction, the instruction itself is deleted because the value of C0 is not valid at the stage of the decoding stage (DEC). First, it is issued to the execution stage (EX), and the execution result is invalidated at that stage. On the other hand, for the add instruction, since the value of C0 is fixed at the time of the decoding stage (DEC), the instruction itself is substantially deleted at the decoding stage (DEC) and is not issued to the execution stage (EX). . In this case, the free arithmetic unit can be used in the instruction subsequent to the addition instruction.

  If there is a remaining instruction that is not issued even after the instruction is invalidated by the control as described above, the instruction issuance control unit 31 transmits the number of remaining instructions to the instruction buffer 22 and is stored in the instruction buffer 22. Control is performed so that these instructions are not invalidated and transferred to the instruction register 23 again in the next cycle.

  In this way, by taking the instruction format as shown in FIG. 1 and adopting the configuration as shown in FIGS. 4 and 5, instruction issue control that effectively uses the arithmetic unit can be performed.

(Processor operation)
Next, the operation of the processor of this embodiment when a specific instruction is decoded and executed will be described.

  FIG. 7 is a diagram showing a part of a program including conditional execution. This program is composed of five instructions, and the processing content of each instruction is expressed in mnemonics. Specifically, the mnemonic “add” represents addition of a constant or register storage value and the register storage value, and the mnemonic “sub” represents subtraction of the constant or register storage value from the register storage value. The mnemonic “st” represents the transfer of the stored value of the register to the memory, and the mnemonic “mov” represents the transfer of the constant or the stored value of the register to the register.

  “Rn (n = 0 to 63)” indicates one register in the register file 43. The parallel execution boundary information E of each instruction is also indicated by “0” or “1”. Further, the condition flag specified by the execution condition information P is described in “[]” at the head of each instruction. An instruction that is not described is an instruction that is always executed.

  The operation of this processor for each execution unit will be described below. However, here, it is assumed that the value of the condition flag C0 is “1” and the value of C1 is “0” at the first time.

(Execution unit 1)
Packets including instruction 1, instruction 2, instruction 3 and instruction 4 are supplied from the external memory and transferred to the instruction register 23, respectively. Next, the instruction issue control unit 31 refers to the parallel execution boundary information E of each instruction. In this case, since the parallel execution boundary information of the instruction 3 is “1”, the decoding result of the fourth instruction decoder 36 is invalidated, that is, a non-operation instruction.

  Next, the instruction issue control unit 31 refers to the execution condition information P of each instruction. Since the execution condition flag of the instruction 1 is C0 and the value of C0 is fixed to “1”, the selection of the operand is controlled by the execution instruction selector 371 so that the instruction 1 is executed as the first instruction. The execution instruction selector 373 is controlled so as to select the decoding result. Next, since the execution condition flag of the instruction 2 is C1, and the value of C1 is “0”, the instruction 2 itself is substantially deleted and the operation is not executed. Since the subsequent instruction 3 is always executed, the selection of the operand is controlled by the execution instruction selector 372 so that the instruction 3 is executed as the second instruction, and the execution instruction selector is selected so as to select the decoding result. 374 is controlled. As a result, the instructions 1 and 3 are sent to the execution unit 40 as instructions to be executed, and the instruction 4 that has not been issued remains in the instruction buffer 22.

  In the execution unit 40, a value obtained by adding 1 to the stored value of the register R0 is stored in the register R0, and a value obtained by adding the stored value of the register R1 and the stored value of the register R2 is stored in the register R2.

(Execution unit 2)
The instruction 4 left in the instruction buffer 22 and the instruction 5 newly supplied from the external memory are sequentially transferred to the instruction register 23. Next, the instruction issue control unit 31 refers to the parallel execution boundary information E of each instruction. In this case, since the parallel execution boundary information of the instruction 5 is “1”, the decoding result of the third instruction decoder 35 and the fourth instruction decoder 36 is invalidated, that is, an inoperative instruction.

  Since both the instruction 4 and the instruction 5 are always executed instructions, the execution instruction selectors 371 to 374 send the instruction 4 as the first instruction and the instruction 5 as the second instruction to the execution unit 40. To control. Thus, all supplied instructions are issued.

  In the execution unit 40, the stored value of the register R0 is transferred to the address indicated by the register R3 in the external memory, and the stored value of the register R2 is transferred to the register R4.

  As described above, the program shown in FIG. 7 is executed in two execution units in this processor. In this processor, more instructions than the number of the arithmetic units 44 and 45 are decoded, and unnecessary instructions are deleted as appropriate, so that the arithmetic units 44 and 45 are efficiently used. Also in this example, in each cycle, two operations are executed in the execution unit 40, and the mounted computing units 44 and 45 are efficiently utilized.

(Comparison with a processor having a conventional instruction issue control unit)
Next, it is assumed that the processing shown in FIG. 7 is performed by a processor that issues all the conditional execution instructions to the execution unit and invalidates the execution unit as appropriate in the conventional technology. Compare with the processor according to the invention.

  FIG. 8 is a block diagram showing a peripheral configuration of an instruction register of a conventional processor. The conventional processor has two arithmetic units like the processor of the present invention, and the instruction format is the same as the instruction format of the processor of the present invention shown in FIG. Since the processors are two parallel processors, the instruction register 23a includes an A register 231a and a B register 232a, and the instruction decoder 32a includes a first instruction decoder 33a and a second instruction decoder 34a. 50a and 51a are constant operands. The instruction issue control unit 31a performs control to invalidate the decoding result of the second instruction decoder 34a in accordance with the parallel execution boundary information E of the instruction stored in the A register 231a.

  FIG. 9 is a diagram showing a program that causes the processing of the program shown in FIG. 7 to be executed by a processor having a conventional instruction issue control unit 31a. The program of FIG. 9 is the same as the program of FIG. 7 except for the parallel execution boundary information E. The parallel execution boundary information E is set so that a maximum of two instructions are issued simultaneously.

  The operation of the conventional processor for each execution unit will be described below. However, here, it is assumed that the value of the condition flag C0 is “1” and the value of C1 is “0” at the first time.

(Execution unit 1)
A packet including an instruction 1, an instruction 2, an instruction 3 and an instruction 4 is supplied from the external memory, and the instruction 1 and the instruction 2 are sequentially transferred to the instruction register 23a. Next, the instruction issue control unit 31a refers to the parallel execution boundary information E of the instruction 1 stored in the A register 231a. In this case, since the parallel execution boundary information E of the instruction 1 is “0”, the decoding result of the second instruction decoder 34a is not invalidated. Therefore, both instruction 1 and instruction 2 are sent to the execution unit. Instructions 3 and 4 that have not been issued are left in the instruction buffer.

  In the execution unit, C0 which is the execution condition flag of the instruction 1 is “1”, and therefore, a value obtained by adding 1 to the stored value of the register R0 is stored in the register R0. Since the execution condition flag C1 of the instruction 2 is “0”, the operation corresponding to the instruction 2 is not executed, or the result after execution is invalidated, and the non-operation instruction is executed as a result. It will be the same.

(Execution unit 2)
Instruction 3 and instruction 4 remaining in the instruction buffer are sequentially transferred to the instruction register 23a, and instruction 5 is newly supplied from the external memory. Next, the instruction issuance control unit 31a refers to the parallel execution boundary information E of the instruction 3 stored in the A register 231a. In this case, since the parallel execution boundary information E of the instruction 3 is “0”, the decoding result of the second instruction decoder 34a is not invalidated. Therefore, both instruction 3 and instruction 4 are sent to the execution unit. The instruction 5 that has not been issued remains in the instruction buffer 22.

  In the execution unit, since both the instruction 3 and the instruction 4 are instructions that are always executed, operations corresponding to these two instructions are executed. Specifically, a value obtained by adding the stored value of the register R1 and the stored value of the register R2 is stored in the register R2, and the stored value of the register R0 is transferred to the address indicated by the register R3 on the external memory.

(Execution unit 3)
The instruction 5 remaining in the instruction buffer is transferred to the instruction register 23a. Next, the instruction issue control unit 31a refers to the parallel execution boundary information E of the instruction 5 stored in the A register 231a. In this case, since the parallel execution boundary information E of the instruction 5 is “1”, the decoding result of the second instruction decoder 34a is invalidated. Therefore, only instruction 5 is issued. Thus, all supplied instructions are issued.

  In the execution unit, since the instruction 5 is an instruction that is always executed, an operation corresponding to the instruction 5 is executed. Specifically, the stored value of the register R2 is transferred to the register R4.

  As described above, the program shown in FIG. 9 is executed in three execution units in the processor having the conventional instruction issuance control unit 31a, and is executed in one execution unit more than in the case of the processor of the present invention. Will be. This is because in a processor having a conventional instruction issuance control unit 31a, if the condition of a conditional execution instruction is false, the instruction is executed as a no-operation instruction, and a built-in arithmetic unit is wasted. This is due to the fact that

[Embodiment 2: Compiling device]
Next, an embodiment relating to a compiling apparatus for generating a code to be executed by the processor in the above-described first embodiment and a compiling method thereof will be described.

(Glossary)
First, terms used here will be described.
-Object code A machine language program for the target processor that contains relocatable information. By performing concatenated editing and determining an undetermined address, it can be converted into an executable code.
• Predecessor An instruction that must be executed before an instruction can be executed.
-Execution group An instruction group that groups together those that can be executed in parallel in the same cycle by a compiling device.
Basic block A sequence of instructions that starts from the beginning and is always executed to the end. It means that the block is exited in the middle of the block or the block is not entered in the middle of the block.

(Target processor)
The processor targeted by the compiling apparatus is the processor described in the first embodiment. This processor generates an execution group by referring to the parallel execution boundary information E given by the compiling device, and does not determine whether or not parallel execution is possible in hardware. Therefore, the compiling device guarantees that instructions that can be executed simultaneously are correctly arranged between parallel execution boundaries, that is, in execution groups. The restrictions on instructions that can be placed between parallel execution boundaries are:
(1) The total number of instructions in the parallel execution group does not exceed 4 (instruction decoder restrictions);
(2) Of the instructions in the parallel execution group, the number of instructions that are actually executed by the execution unit does not exceed 2 (restriction on the number of executed instructions),
(3) Among the instructions in the parallel execution group, the sum of the target processor resources actually used by the execution unit does not exceed 2 ALU units, 1 memory access unit, and 1 branch unit (constraints on computing units).
It is. An instruction can be executed in parallel only if these three constraints are met.

(Compile device configuration)
FIG. 12 is a block diagram showing a configuration of the compiling apparatus and related data according to the second embodiment of the present invention. The compiling device is a program processing device that generates object code 130 from source code 120 written in a high-level language, and includes a compiler upstream unit 100, an assembler code generation unit 101, an instruction scheduling unit 102, and an object code generation unit 103. .

  The compiler upstream unit 100 reads the high-level language source code 120 stored in the file format, performs syntax analysis and semantic analysis, and generates an internal format code. Further, if necessary, the internal format code is optimized so that the size of the finally generated executable code and the execution time thereof are shortened.

  The assembler code generation unit 101 generates assembler code from the internal format code generated and optimized by the compiler upstream unit 100.

  The processing in the compiler upstream unit 100 and the assembler code generation unit 101 is not the main point of the present invention, and is equivalent to the processing performed in a conventional compiling apparatus, and thus detailed description thereof is omitted.

(Instruction scheduling unit 102)
The instruction scheduling unit 102 analyzes, for the assembler code generated by the assembler code generation unit 101, analysis of exclusiveness between conditions added to the instruction, analysis of dependency between instructions, rearrangement of instructions (arrangement of instruction order). And parallel execution boundaries are added, and the assembler code is parallelized for the target processor. The instruction scheduling unit 102 includes a condition exclusiveness analysis unit 110, a dependency relationship analysis unit 111, an instruction relocation unit 112, and an execution boundary addition unit 113.

  In the instruction scheduling unit 102, the conditional exclusiveness analysis unit 110 operates first. Thereafter, the dependency analysis unit 111, the instruction relocation unit 112, and the execution boundary addition unit 113 operate for each basic block. The detailed operation of each part is as follows.

  The condition exclusivity analysis unit 110 analyzes the condition flag exclusivity and generates a condition exclusion information table for each basic block and each condition flag update instruction. The condition exclusion information table is an array having information on whether or not a condition is exclusive for all combinations of condition flags. A specific example of the conditional exclusion information table will be shown later (FIG. 16). Here, an information table in which all combinations of condition flags are not exclusive is called a non-exclusive table.

  FIG. 13 is a flowchart showing a processing procedure in the condition exclusivity analysis unit 110. The conditional exclusiveness analysis unit 110 searches downward in the intermediate code in the compiling device corresponding to each instruction, and sets a conditional exclusive information table for the top of each basic block and each conditional flag update instruction. Go.

  First, a valid table Tv that is currently valid is initialized with a non-exclusive table (step S11). Thereafter, each basic block is searched downward (step S12).

  If there is only one preceding basic block of the basic block as a result of the determination on a basic block (step S13), the valid table Tv is set in the basic block head table (step S14). Since the exclusive relationship at the time cannot be specified, a non-exclusive table is set in the basic block head table (step S15).

  Next, each instruction in the basic block is searched (step S16). When an instruction for updating a condition flag such as a comparison instruction is found (step S17), it is determined whether the instruction is an instruction for setting an exclusive condition at the same time (step S18). An instruction for setting an exclusive condition at the same time corresponds to a comparison instruction for updating the condition flags C0 and C1 of the instruction 1 in FIG.

  In the case of an instruction for setting an exclusive condition at the same time, first, all portions corresponding to the condition flag to be updated by the instruction in the valid table Tv are set to false, and then the condition set to exclusive by the instruction Only set the flag set to true. Then, the valid table Tv is set in the exclusive information table for the instruction (step S19).

  In the case of an instruction that does not set an exclusive condition at the same time, since the exclusivity regarding the condition flag updated by the instruction is lost, all portions corresponding to the condition flag updated by the instruction in the valid table Tv are set to false. Then, the valid table Tv is set in the exclusive information table for the instruction (step S20).

  The above is repeated for each basic block (steps S21 and S22). As a result, it is possible to hold information regarding the exclusivity of the condition flag at each point in time for all the instructions that set the head of all the basic blocks and the condition flag.

The dependency relationship analysis unit 111 analyzes the dependency relationship between instructions included in the processing target and expresses the dependency relationship as a dependency graph. There are the following three types of dependency relationships between instructions. Any instruction having any dependency relationship changes the meaning of the program if the original instruction order is changed. Therefore, it is necessary to maintain the dependency relationship even when the instructions are rearranged.
Data dependency A dependency between an instruction that defines a resource and an instruction that references the same resource.
• Inverse dependency A dependency between an instruction that references a resource and an instruction that defines the same resource.
Output dependency A dependency between an instruction that defines a resource and an instruction that defines the same resource.

  The dependency relationship analysis unit 111 generates a node (section) corresponding to each instruction included in the processing target, and an edge (arrow) corresponding to each instruction, and generates a dependency graph. To do. At this time, even if it is between two instructions that depend on the resource to be referenced and defined, if it is guaranteed that the execution conditions of each instruction are exclusive, that is, they cannot be satisfied at the same time, the two instructions are both Since a resource cannot be referenced or defined, there is no dependency between the two instructions. Therefore, no edge is generated between nodes corresponding to these two instructions.

  In order to realize this, it is necessary to detect whether or not the execution condition of the two instructions is exclusive with respect to the preceding instruction A and instruction B using the exclusive information table set by the condition exclusiveness analysis unit 110. . FIG. 14 shows an algorithm for detecting this exclusivity.

  First, the execution condition flag of the instruction A is set to Cn (step S31). Then, in order to obtain valid exclusive information at the time of execution of the instruction A, the search is performed upward from the instruction A, and when the instruction for updating the condition flag is found or when the head of the basic block is reached, it corresponds. The exclusive information table is set as a valid table Tv (step S32).

  Next, in order to follow the path to the instruction B, the search is performed downward from the instruction A (step S33). When the instruction B is found (step S34), the exclusive table Tv at that time is referred to determine the exclusive relationship between the condition flag Cn and the execution condition of the instruction B, and the process ends (step S35). When an instruction for updating a condition flag other than Cn is found (step S36), the validity table Tv is updated with the exclusive information table corresponding to the instruction and the process continues (step S37). If an instruction for updating the condition flag Cn is found (step S38), the exclusiveness cannot be guaranteed, and false is returned (step S39). The above is repeated (step S40).

  In this way, both the definition and reference relationship of resources and the exclusivity of execution conditions are analyzed, and a dependency relationship between instructions is constructed.

  As a specific example, application results of the condition exclusiveness analysis unit 110 and the dependency relationship analysis unit 111 with respect to the assembler code illustrated in FIG. 15 will be described.

  FIG. 16 is a diagram showing a condition exclusion information table corresponding to the assembler code instruction 2 (comparison instruction) in FIG. The condition exclusion information table is an array indicating the exclusion for all combinations of the condition flags C0 to C7. In this case, the instruction 2 sets that the condition flag C0 and the condition flag C1 are exclusive.

  FIG. 17 is a diagram illustrating a dependency graph that is an output of the dependency relationship analysis unit 111. In FIG. 17, the solid line indicates the data dependency relationship, and the broken line indicates the reverse dependency relationship. Since the instruction 2 (comparison instruction) refers to the register R0 updated by the instruction 1, there is data dependency, and the instruction 3 and the instruction 4 refer to the condition flags C0 and C1 updated by the instruction 2, so the data dependency There is. Here, since the instruction R3 updates the register R2 and the instruction 4 refers to the register R2, at first glance, it seems that there exists a data dependency from the instruction 3 to the instruction 4. However, since C0 and C1, which are the execution conditions of the respective instructions, are set as exclusive conditions by the instruction 2, the two instructions can be executed together by referring to the conditional exclusion information table shown in FIG. It is determined that this is not possible, and there is no dependency between these two instructions.

  Returning to the description of FIG. 12, the instruction relocation unit 112 rearranges the processing target instructions using the dependency graph generated by the dependency analysis unit 111 and generates a parallel assembler code for the target processor. To do. Details of the processing of the instruction rearrangement unit 112 are as follows.

  FIG. 18 is a flowchart showing a processing procedure in the instruction relocation unit 112. The instruction rearrangement unit 112 repeats the following processing of loop 1 (steps S52 to S60) for all nodes of the dependency graph generated by the dependency relationship analysis unit 111 (steps S51 and S61).

  First, the instruction rearrangement unit 112 extracts nodes that can be placement candidates at the present time from the dependency graph and sets them as a placement candidate node set (step S52). Here, the nodes that can be placement candidates are nodes that are “all predecessors have been placed”.

  Next, the instruction rearrangement unit 112 repeats the following processing of loop 2 (steps S54 to S58) for all candidate nodes of the arrangement candidate node set (steps S53 and S59).

  First, a node (hereinafter simply referred to as “best node”) that is considered to be best arranged at the present time is extracted from the candidate arrangement node set (step S54). A method for determining the best node will be described later. Subsequently, it is determined whether or not the best node can actually be arranged (step S55). If possible, the best node is provisionally arranged (step S56). In order to make effective use of the effect of deleting the instruction itself at the decoding stage of the processor described above, this determination is performed while taking into account the exclusivity of the execution condition between the already provisionally arranged node and the best node. It is determined depending on whether the constraint, the constraint on the number of executed instructions, and the constraint on the instruction decoder are satisfied. In consideration of the condition exclusivity, the result of the condition exclusivity analysis unit 110 is used. However, it is also considered that the instruction itself executed under the execution condition is not deleted in the next cycle of the instruction that updates the execution condition flag. That is, in this case, the possibility of arrangement is determined purely by the restriction of the arithmetic unit and the number of execution instructions without considering the exclusivity of the execution conditions.

  Subsequently, the node set temporarily arranged at present is checked, and it is determined whether or not an instruction can be arranged (step S57). If it is determined that the placement is impossible, the loop 2 is terminated and the process proceeds to step S60.

  When it is determined that placement is possible, it is determined whether or not a node that can be a new placement candidate has occurred due to the placement of the best node, and if a new placement candidate is created, this is added to the placement candidate node ( Step S58). In step S58, a node that can be newly set as a placement candidate is a node having “only the best node (currently planned to be placed) as a predecessor and the dependency relationship with the best node being inversely dependent or output dependent”. That is, a node that can be a new placement candidate here can be executed in the same cycle as the best node, but cannot be executed in a cycle before the best node.

  After the loop 2 ends, the nodes included in the temporary arrangement node set are determined (step S60). Specifically, an instruction corresponding to a node included in the temporary arrangement node set is extracted from the original instruction sequence and rearranged in a new instruction sequence to be passed to the execution boundary adding unit 113. At this stage, a part of the arrangement candidate nodes is collected and confirmed as a group of instructions to be executed simultaneously.

  Next, the method for determining the best node in step S54 will be described. The best node heuristically selects an instruction that can execute the entire instruction to be processed in the shortest time with reference to the dependency graph and the temporary arrangement area. Here, in the current dependency graph, the one having the shortest total execution time of instructions up to the end of the dependency graph is selected. If there are many instructions that match this condition, the instruction with the earlier instruction order is taken as the best node.

  Returning to FIG. 12 again, the execution boundary adding unit 113 sets the parallel execution boundary information E for each end of the instruction group whose arrangement is determined in step S60 of the instruction relocation unit 112.

  The object code generation unit 103 converts the assembler code output from the instruction scheduling unit 102 into an object code 130 and outputs the object code 130 as a file.

(Compiler operation)
Next, operations of characteristic components of the compiling apparatus will be described using specific instructions.

FIG. 19 shows assembler code generated by inputting source code to the compiler upstream section 100 and passing through the assembler code generation section 101. The instruction scheduling unit 102 receives the code shown in FIG. 19 as an input. The meaning of each instruction included in FIG. 19 is as follows.
Instruction 1... Compares whether the value stored in the register R0 matches the constant 0, sets true / false to the condition flag C0, and sets the opposite condition to the condition flag C1.
Instruction 2 ... Only when the value of the condition flag C0 is true, the stored value of the register R1 and the stored value of the register R2 are added and stored in the register R2.
Instruction 3 ... Only when the value of the condition flag C1 is true, the stored value of the register R2 and the stored value of the register R3 are added and stored in the register R3.
Instruction 4 ... Only when the value of the condition flag C0 is true, the stored value of the register R1 and the stored value of the register R3 are added and stored in the register R3.
Instruction 5: Only when the value of the condition flag C1 is true, the stored value of the register R3 and the stored value of the register R4 are added and stored in the register R4.
Instruction 6: Only when the value of the condition flag C0 is true, the stored value of the register R2 and the stored value of the register R4 are added and stored in the register R4.
Instruction 7: Only when the value of the condition flag C1 is true, the stored value of the register R3 and the stored value of the register R5 are added and stored in the register R5.

  Hereinafter, the operation of the instruction scheduling unit 102 will be described. First, the condition exclusiveness analysis unit 110 and the dependency relationship analysis unit 111 are activated to generate a dependency graph. In the code example of FIG. 19, the definition and reference relationship of resources are analyzed while considering that the condition flags C0 and C1 generated by the instruction 1 are exclusive after the instruction 2. FIG. 20 shows the generated dependency graph.

  Next, the instruction relocation unit 112 is activated. Explaining along the flowchart of FIG. 18, first, in the first cycle, an arrangement candidate node set is generated (step S52). From the dependency graph of FIG. 20, here, only instruction 1 is a placement candidate node. Next, the best node is extracted (step S54). Here, instruction 1 is automatically selected. Then, in the arrangement possible determination step (S55), it is determined that the arrangement is possible. Further, in the placement state determination step (S57), it is determined that the placement is still possible, but since there is no instruction to be added in the placement candidate node addition step (S58), the placement node determination step (S60) Thus, the first cycle is determined to issue only instruction 1.

  In the next cycle, instruction 2, instruction 3 and instruction 4 become placement candidate nodes. Instruction 2 and instruction 3 are selected as the best nodes in order and temporarily arranged. Next, the instruction 4 is selected as the best node, and the placement possible determination step (S55) is entered. Here, the determination considering the condition exclusiveness is performed, but since the values of the execution conditions C0 and C1 are updated in the immediately preceding cycle, the instruction decoding stage using the execution conditions of C0 and C1 in this cycle. Deletion in is not performed. Therefore, since the instruction 2 and the instruction 3 that have already been temporarily arranged are not deleted, it is determined that the instruction 4 cannot be issued simultaneously, that is, cannot be arranged due to the limitation of the arithmetic unit mounted on the hardware. Thus, in the second cycle, the instruction 2 and the instruction 3 are determined to be issued.

  In the next cycle, instruction 4, instruction 5, instruction 6 and instruction 7 become placement candidate nodes. Instruction 4 and instruction 5 are selected as the best nodes in order and temporarily arranged. Next, the instruction 6 is selected as the best node, and the placement possible determination step (S55) is entered. Here, the determination considering the condition exclusivity is performed. When the instruction 6 actually executes the operation, that is, when the execution condition flag C0 of the instruction 6 is true, the condition flag C1 is false. Therefore, the instruction 5 having the execution condition of C1 does not execute the operation. Do not use the calculator. Therefore, since the combination of the instruction 4 and the instruction 6 satisfies the restrictions of the arithmetic unit, it is determined that the instruction 6 can be arranged. Next, the instruction 7 is selected as the best node. However, when the instruction 7 executes the operation as described above, the instruction 4 and the instruction 6 are deleted. It is determined that the instruction 7 can be arranged. Thus, in the third cycle, it is decided to issue the instruction 4, the instruction 5, the instruction 6 and the instruction 7. Since there are no unallocated nodes, the processing of the instruction rearrangement unit 112 is completed.

  Finally, the execution boundary adding unit 113 is activated. Here, the parallel execution boundary information E is set to the last instruction of the instruction group arranged by the instruction relocation unit 112. Specifically, “1” is set to the parallel execution boundary information E of the instruction 1, the instruction 3 and the instruction 7, and “0” is set to the parallel execution boundary information E of the remaining instructions.

  Thus, the process of the instruction scheduling unit 102 is completed. Subsequently, the object code generation unit 103 is activated and the object code is output.

  FIG. 21 shows the final execution format code. The actual execution format code is a bit string collected in 128-bit units. The execution format code shown in FIG. 21 is executed in three execution groups by a processor having two arithmetic units according to the present invention.

(Comparison with conventional compilation equipment)
Next, assuming that the assembler code shown in FIG. 19 is compiled by a conventional compiling device that does not have the configuration of the compiling device of the present invention, the assembler code is compared with the compiling device according to the present invention. The target processor is assumed to be a processor including two arithmetic units as in the processor of the present invention.

  The conventional compiling apparatus has a difference in the instruction relocation unit. First, in the first cycle, only instruction 1 is issued due to the dependency. In the next cycle, instruction 2, instruction 3 and instruction 4 are candidates, but only instruction 2 and instruction 3 are issued due to the limitation of two arithmetic units in one cycle. In the next cycle, instruction 4, instruction 5, instruction 6 and instruction 7 are candidates, but only instruction 4 and instruction 5 are issued due to the limitation of the arithmetic unit. In the next cycle, instruction 6 and instruction 7 are candidates, and both instructions are issued to satisfy the constraints of the arithmetic unit. In this way, instruction rearrangement is completed. Specifically, the execution boundary adding unit sets “1” to the parallel execution boundary information E of the instruction 1, the instruction 3, the instruction 5, and the instruction 7, and “0” to the parallel execution boundary information E of the remaining instructions. Set. This completes the instruction scheduling process.

  FIG. 22 shows the execution format code generated as a result. The execution format code shown in FIG. 22 is executed in four execution groups by a processor having two arithmetic units.

  When FIG. 21 and FIG. 22 are compared, in the generated code of the conventional compiling device (FIG. 22), the execution group is increased by one as compared with the generated code of the compiling device of the present invention (FIG. 21). That is, the number of execution cycles is increased by one cycle. The reason why the number of execution groups has increased in this way is that the instruction scheduling unit 102 of the present invention is not adopted, so that all instructions are handled as being issued to the execution stage and are installed in hardware. This is because it can only be arranged with the number of computing units as the upper limit. On the other hand, in the compiling device according to the present invention, it is possible to arrange instructions in a number equal to or greater than the number of arithmetic units installed in hardware in consideration of invalidation of the instruction itself, and effectively use the arithmetic units. can do.

  The compiling apparatus shown in this embodiment can be realized by a computer by putting the processing procedure of the compiling apparatus shown in this embodiment into a recording medium such as a flexible disk, hard disk, CD-ROM, MO, and DVD.

  Further, the execution format code generated by the compiling device shown in the present embodiment can be put in a recording medium such as a flexible disk, a hard disk, a CD-ROM, an MO, a DVD, or a semiconductor memory.

[Embodiment 3: Processor]
Next, an embodiment of a processor that is an extension of the processor of the first embodiment will be described.

  Most of the hardware configuration of this processor is the same as that of the processor of the first embodiment described above, but there is a limitation on the arrangement of execution condition information of the instruction group arranged in the execution group. Specifically, there is a restriction that instructions having the same execution condition are always arranged consecutively in one execution group. The compiling device according to the fourth embodiment to be described later generates code according to this restriction. As a result, the configuration of the instruction issuance control unit differs as a processor.

(Configuration and operation of instruction issue controller)
FIG. 23 shows the configuration of the instruction issuance control unit 140 and its peripheral circuits of the processor of this embodiment. Most parts of the instruction issuance control unit 140 in FIG. 23 are the same as those of the processor of the first embodiment shown in FIG. The difference is that the control method of the execution instruction selection control unit 141 and the instruction coupling unit 142 are added after the execution instruction selection control unit 141.

  First, the execution instruction selection control unit 141 performs control to substantially delete the instruction itself for an instruction whose execution condition is false, as described in the first embodiment. Unlike the case of Form 1, restrictions are added in the order of instruction arrangement, so that they are actively utilized. Specifically, since there is a restriction that instructions having the same execution condition information are successively arranged in the instruction arrangement order, first, the decoded instruction group is classified for each execution condition. This classification can be easily performed due to the restriction of the instruction arrangement order.

  Next, whether or not the value of the execution condition flag is fixed at “0” is checked for each classified execution condition. The instruction group whose execution condition is the condition flag fixed at “0” is controlled to be deleted together, and the instruction group to be actually issued to the execution unit 40 is determined. As a result, the number of condition flag checks can be minimized, the possibility of deletion of a plurality of instructions can be detected simultaneously, and instructions to be issued to the execution unit 40 can be detected quickly and easily.

  Next, after the execution instruction selection control unit 141 deletes the instruction, the instruction group is input to the instruction coupling unit 142. Here, it is detected whether or not a plurality of instructions can be combined as one compound instruction with respect to an instruction group that is actually executed by the execution unit 40. The control signal is changed to the new compound instruction, the operands are combined, and the subsequent instruction is controlled to be deleted in the same manner as the execution instruction selection control unit 141. In this way, the instruction combining unit 142 outputs control signals and operand data corresponding to two instructions corresponding to the number of arithmetic units mounted as hardware, and transfers them to the execution unit 40. Each of these instructions may be a composite instruction of a plurality of instructions.

(Processor operation)
Next, a specific operation of this processor will be described with reference to FIG. FIG. 24 is a diagram illustrating an example of a program including a conditional execution instruction. This program is composed of four instructions, and the notation is the same as the program of FIG. The mnemonic “lsr” represents a logical right shift of the stored value of the register.

  The operation of this processor for each execution unit will be described below. However, here, it is assumed that the value of the condition flag C0 is “0” and the value of C1 is “1” at the first time.

(Execution unit 1)
Packets including instruction 1, instruction 2, instruction 3 and instruction 4 are supplied from the external memory and transferred to the instruction register 23, respectively. Next, the instruction issuance control unit 140 refers to the parallel execution boundary information E of each instruction. In this case, since the parallel execution boundary information E of the instruction 1, the instruction 2, and the instruction 3 is all “0”, the decoding result of the instruction decoder is not invalidated.

  Next, the instruction issue control unit 140 refers to the execution condition information P of each instruction, and the execution instruction selection control unit 141 selects an instruction to execute the operation. Instruction 1 is an instruction that is always executed. Since the execution condition flag of the instruction 2 is C0 and the value of C0 is fixed at “0”, the instruction 2 itself is substantially deleted and the operation is not executed. Since the execution condition flags of the subsequent instruction 3 and instruction 4 are both C1, the condition flag C1 is referred to only once, and since the value of C1 is fixed at “1”, both the instruction 3 and the instruction 4 are executed. set to target. In this way, the instruction 1, the instruction 3 and the instruction 4 are sent to the next instruction combination unit 142.

  The instruction combining unit 142 determines whether or not a composite instruction can be generated for all combinations of input instruction groups. In this case, it is detected that the shift addition instruction can be generated by combining the instruction 1 (shift instruction) and the instruction 4 (addition instruction). Then, the control signal and operand corresponding to shift addition are sent to the execution unit 40 as the first instruction, and the control signal and operand corresponding to instruction 3 are sent as the second instruction, respectively. Thus, all supplied instructions have been issued.

  In the execution unit 40, a value obtained by logically shifting the stored value of the register R3 by the value stored in the register R1 and adding the stored value of the register R2 is stored in the register R2, and 1 is added to the stored value of the register R0. The stored value is stored in the register R0.

  As described above, the program shown in FIG. 24 is executed in one execution unit in this processor. In this processor, after deleting the instruction itself according to the determined execution condition, it tries to combine the instructions into one composite instruction. This makes it possible to increase the actual calculation efficiency. Further, by using the restriction that instructions having the same execution condition are continuously arranged, the processing for selecting an instruction for actually executing an operation at the decoding stage is speeded up.

[Embodiment 4: Compiling device]
Next, an embodiment relating to a compiling device that generates code to be executed by the processor and a compiling method thereof according to the third embodiment will be described.

  The configuration of the compiling device is mostly the same as that of the compiling device of the second embodiment described above, but there is a limitation on the arrangement of instructions in one execution group depending on the execution conditions. And that it takes into account the combination of instructions in the decoding stage of the processor. Specifically, the configuration of the instruction scheduling unit is different.

(Instruction scheduling part)
The instruction scheduling unit of the compiling device according to the present embodiment includes a condition exclusiveness analysis unit, a dependency relationship analysis unit, an instruction relocation unit, and an execution boundary addition unit, similar to the instruction scheduling unit 102 according to the second embodiment. However, the only difference is the rearrangement method of the instruction rearrangement unit.

  FIG. 25 shows a flowchart of the instruction rearrangement unit of the compiling device of this embodiment. The processing procedure of the instruction relocation unit of the compiling device according to the present embodiment is mostly the same as the processing procedure of the instruction relocation unit 112 of the compiling device according to the second embodiment. The difference is that the arrangement order is adjusted after the arrangement node is determined. Specifically, among steps S71 to S82 in FIG. 25, the arrangement possibility determination (step S75) and the arrangement order adjustment (step S81) are different from the flow shown in FIG.

  Similar to the compiling device of the second embodiment, a dependency graph is generated through the condition exclusivity analysis unit and the dependency relationship analysis unit, and then moved to the instruction relocation unit. Then, the instruction rearrangement is performed based on the dependency graph in consideration of the condition exclusivity. After selecting the best node in step S74, the provisional arrangement is performed when the arrangement possibility determination is performed in step S75. With respect to the completed node group and the best node, the arrangement possibility determination is performed in consideration of not only the exclusivity of the execution conditions but also the possibility of instruction combination for all combinations. That is, when two nodes can be combined, the two nodes are combined and treated as one instruction, and an arrangement possibility determination is performed.

  Further, after the nodes that can be arranged in the cycle are determined in step S80, the arrangement order is adjusted in step S81. Specifically, the node groups that can be arranged in the cycle are classified for each execution condition, and the arrangement order of the nodes is adjusted so that nodes having the same execution condition are always arranged continuously. This simplifies control in hardware.

(Compiler operation)
With reference to FIG. 26, the operation of the characteristic components of the compiling apparatus will be described using specific instructions. FIG. 26 shows an example of assembler code generated through the compiler upstream section and the assembler code generation section. The instruction scheduling unit receives the code shown in FIG. 26 as an input. The meaning of each instruction included in FIG. 26 is as follows. However, it is assumed that the condition flags C0 and C1 are in an exclusive relationship with the instruction before the instruction 1.
Instruction 1... Logically shifts the stored value of register R3 by the amount stored in register R1.
Instruction 2 ... Only when the value of the condition flag C1 is true, 1 is added to the stored value of the register R0 and stored in the register R0.
Instruction 3 ... Only when the value of the condition flag C0 is true, 1 is subtracted from the stored value of the register R0 and stored in the register R0.
Instruction 4 ... Only when the value of the condition flag C1 is true, the stored value of the register R1 and the stored value of the register R2 are added and stored in the register R2.

  The operation of the instruction scheduling unit will be described below. First, the condition exclusiveness analysis unit and the dependency relationship analysis unit are activated, and a dependency graph is generated. In this example, the definition and reference relationship of resources are analyzed while considering that the condition flags C0 and C1 are exclusive.

  Next, the instruction relocation unit is activated. Describing along the flowchart of FIG. 25, first, an arrangement candidate node set is generated (step S72). Here, only the instruction 1 is a placement candidate node. Next, the best node is extracted (step S74). Here, instruction 1 is automatically selected. And in arrangement | positioning possibility determination (step S75), it determines with arrangement | positioning being possible. Further, in the arrangement state determination (step S77), it is determined that the arrangement is still possible. Then, in the placement candidate node addition (step S78), the command 2, the command 3, and the command 4 are added to the placement candidate nodes as the commands to be added.

  And it returns again and takes out the best node (step S74). Here, first, the instruction 2 is selected and it is determined that it can be arranged (step S75).

  Thereafter, the best node is retrieved again (step S74). Here, instruction 3 is selected. Since the execution conditions of the instruction 2 and the instruction 3 are exclusive, it is determined that the restriction of the two arithmetic units is satisfied and the arrangement is possible (step S75).

  Further, the best node is retrieved again (step S74). Here, the remaining instruction 4 is automatically selected. Then, the arrangement possibility determination is performed (step S75). When it is assumed that the execution condition C0 is true, only the instruction 1 and the instruction 3 are valid, so that the restriction of the arithmetic unit is satisfied. On the other hand, if it is assumed that the execution condition C1 is true, the three instructions of the instruction 1, the instruction 2 and the instruction 4 are valid. Here, the possibility of combining instructions is examined for all of these combinations. Here, it is determined that the instruction 1 and the instruction 4 can be combined to form a shift addition instruction provided in the hardware, and as a result, the two instructions become valid, and therefore can be arranged. Determined.

  As described above, all the instructions are arranged in the first cycle, and the arrangement node is determined (step S80). Next, each node is classified according to execution conditions, and the arrangement order is adjusted (step S81). Specifically, since the execution conditions of the instruction 2 and the instruction 4 are the same in C1, the arrangement order of the instruction 1, the instruction 2, the instruction 4, and the instruction 3 is set so that the instruction 2 and the instruction 4 are continuously arranged. Rearrange in order. This completes the processing of the instruction relocation unit.

  Finally, the execution boundary adding unit is activated. Here, parallel execution boundary information is set to the last instruction of the instruction group arranged by the instruction relocation unit. Specifically, “1” is set to the parallel execution boundary information of the instruction 3 and “0” is set to the parallel execution boundary information of the remaining instructions. This completes the process of the instruction scheduling unit.

  As described above, in the compiling device according to the present embodiment, the instruction sequence shown in FIG. 26 is compiled so as to be executed by one execution group. Here, the effect of considering the combination of instructions at the decoding stage of the processor in the arrangement possibility determination (step S75) appears. Further, by adjusting so that instructions having the same execution condition are continuously arranged, it is possible to simplify the control when selecting an effective instruction in the decoding stage of the processor.

  The compiling apparatus shown in this embodiment can be realized by a computer by putting the processing procedure of the compiling apparatus shown in this embodiment into a recording medium such as a flexible disk, hard disk, CD-ROM, MO, and DVD.

  Further, the execution format code generated by the compiling device shown in the present embodiment can be put in a recording medium such as a flexible disk, a hard disk, a CD-ROM, an MO, a DVD, or a semiconductor memory.

  The processor and the compiling device according to the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. The modifications are listed below.

  (1) In the processor and compiling apparatus of the above embodiment, it is assumed that a fixed-length instruction is executed, but the present invention is not limited to such an instruction format. Even if a variable-length instruction format is adopted, the significance of the present invention is maintained.

  (2) In the processor and the compiling device of the above embodiment, it is assumed that there are two arithmetic units, but the present invention is not limited to this number of arithmetic units. The significance of the present invention is maintained even if a processor having one arithmetic unit or three or more arithmetic units is assumed.

  (3) In the processor and compiling apparatus of the above embodiment, it is assumed that the compiling apparatus statically extracts instruction parallelism, but the present invention is not limited to this instruction parallel processing system. For example, the significance of the present invention is maintained even if a superscalar method that dynamically extracts instruction parallelism by hardware is adopted. In this case, the parallel execution boundary information E may be removed from the instruction format of the present invention, and all processes depending on this information may be performed while being dynamically detected by the instruction issue control unit.

  (4) In the instruction rearrangement unit of the compiling device of the above embodiment, the sum of execution times until the end of the dependency graph is used as the best node determination method in step S54 in FIG. However, it is not limited to this selection criterion. For example, a specific path may be preferentially selected from among a plurality of execution flows. In this case, the priority of an instruction having a specific execution condition is raised at the time of taking out the best node (step S54). As a result, scheduling specialized for a specific execution path such as a path with high execution frequency can be performed.

  (5) In the instruction issue control unit of the processor of the above embodiment, the decoding result of the instruction after the instruction in which the parallel execution boundary information E that appears first is “1” is always invalidated. There is no. In the execution instruction selection control unit in the instruction issuance control unit, if there is no instruction that is determined to be transferred to the execution unit before the first parallel execution boundary information E that is “1”, The entire cycle may be deleted, and an instruction group up to an instruction whose parallel execution boundary information E that appears next is “1” may be an issue target in this cycle. That is, only when there is at least one instruction determined to execute a valid operation before the instruction whose parallel execution boundary information E is “1”, the instruction is regarded as a boundary for parallel execution and thereafter Invalidate the result of decoding the instruction. If not, ignore the parallel execution boundary information E of the instruction and detect the new parallel execution boundary by referring to the parallel execution boundary information E of the subsequent instruction. do it. As a result, the number of execution cycles can be further reduced.

  As described above, according to the present invention, it is possible to provide a processor that achieves effective use of hardware and improves performance, and in particular, improves performance by efficiently using arithmetic units in parallel processing. This is useful as a technique for achieving this.

(A)-(c) is a figure which shows the structure of the command which the processor which concerns on Embodiment 1 of this invention performs. (A) And (b) is a figure which shows the concept of the supply and issue of the command in the processor. It is a block diagram which shows the hardware constitutions of the processor. It is a block diagram which shows the structure around the instruction register of the processor. It is a figure which shows the command issue control part of the processor, and its peripheral circuit structure. It is a figure which shows the timing of the pipeline at the time of executing an instruction sequence in the processor. It is a figure which shows a part of program containing a conditional execution instruction. It is a block diagram which shows the structure around the instruction register of the processor which has the conventional instruction issue control part. It is a figure which shows the program which performs the process of the program of FIG. 7 with the processor which has the conventional command issue control part. It is a figure which shows the flow of the process containing a conditional branch. It is a figure which shows the program which described the process of the flow of FIG. 10 by the conditional execution system. It is a block diagram which shows the structure of the compilation apparatus in Embodiment 2 of this invention, and related data. It is a flowchart which shows the process sequence of the condition exclusiveness analysis part in the compilation apparatus. It is a flowchart which shows the processing procedure of the execution condition exclusiveness detection between two instructions in the same compiling apparatus. It is a figure which shows an example of an assembler code. It is a figure which shows the condition exclusion information table corresponding to the instruction 2 of the assembler code of FIG. 16 is a dependency graph corresponding to FIG. It is a flowchart which shows the process sequence of the instruction rearrangement part in the compiling apparatus. It is a figure which shows an example of an assembler code. It is a dependence graph corresponding to FIG. It is a figure which shows the execution format code corresponding to FIG. It is a figure which shows an example of the execution format code at the time of scheduling the code of FIG. 19 with the conventional compilation apparatus. It is a figure which shows the instruction | indication issue control part of the processor which concerns on Embodiment 3 of this invention, and its peripheral circuit structure. It is a figure which shows a part of program containing a conditional execution instruction. It is a flowchart which shows the process sequence of the instruction rearrangement part in the compilation apparatus which concerns on Embodiment 4 of this invention. It is a figure which shows an example of an assembler code.

Explanation of symbols

10 Parallel execution boundary information (E)
11 execution condition information (P)
20 Command supply unit (command supply means)
21 instruction fetch unit 22 instruction buffer 23 instruction register 231 A register 232 B register 233 C register 234 D register 30 decoding unit 31 instruction issue control unit (instruction issue control means)
311 Condition flag 312 Condition flag valid information 313 Execution instruction selection control units 314 and 315 Logic circuit 32 Instruction decoder (decoding means)
33 First instruction decoder 34 Second instruction decoder 35 Third instruction decoder 36 Fourth instruction decoders 371 to 374 Execution instruction selector 38 Instruction invalidation method selection unit (instruction invalidation method selection means)
40 execution unit (execution means)
41 execution control unit 42 PC (program counter) unit 43 register file 44 first arithmetic unit 45 second arithmetic unit 46 write control unit (execution result invalidating means)
47 Operand access section 48, 49 Data bus 100 Compiler upstream section 101 Assembler code generation section 102 Instruction scheduling section (instruction scheduling means)
103 Object code generation part 110 Condition exclusivity analysis part (condition exclusivity analysis means)
111 Dependency Analysis Unit (Dependency Analysis Unit)
112 Instruction relocation unit (command relocation means)
113 Execution boundary adding unit (execution boundary adding means)
120 Source code 130 Object code 140 Instruction issue control section (command issue control means)
141 Execution Instruction Selection Control Unit 142 Instruction Coupling Unit

Claims (10)

Command supply means for supplying a plurality of commands;
Decoding means for decoding each of the plurality of instructions;
An instruction or instruction for executing a valid operation by specifying execution condition information for specifying a condition indicating whether or not to execute each instruction in the plurality of instructions and referring to the condition specified by the execution condition information Instruction issue control means for determining a set of
A processor comprising an execution means for specifying an operation of each instruction in the plurality of instructions and executing one or a plurality of operations based on the specification;
The instruction issue control means determines whether the instruction is a valid instruction that needs to be executed or an invalid instruction that does not need to be executed by referring to the condition specified by the execution condition information. With respect to an instruction determined to be a correct instruction, the instruction is controlled to be deleted before the instruction is issued to the execution means, and a valid instruction subsequent to the instruction is executed instead of the instruction. A processor having a function of controlling to be issued to a means. The processor of claim 1, wherein
The execution means includes execution result invalidation means for invalidating an execution result after executing an operation corresponding to the instruction.
Each instruction further includes instruction invalidation method selection means for selecting whether the instruction itself is deleted before being issued to the execution means or whether the execution result is invalidated by the execution result invalidation means. A processor characterized by that. The processor of claim 2, wherein
The instruction invalidation method selection means determines which instruction invalidation method to select by referring to condition flag valid information indicating whether or not the value of each condition flag is fixed,
When the condition flag valid information is decoded by the decoding means as an instruction to update the condition flag, the determinism of the condition flag is set to false, and the instruction is executed by the execution means and the condition flag is A processor that is set to true when the value of is determined. The processor of claim 1, wherein
The instruction issue control means further has a function of detecting a combination of instructions such that the functions of a plurality of instructions can be realized by a single instruction, and combining the plurality of instructions so as to handle them as a single instruction. A processor characterized by that. The processor of claim 4, wherein
The combination of the plurality of instructions is applied after deletion of an instruction before issuance to the execution means. The processor of claim 1, wherein
When the instructions having the same execution condition information are continuously arranged in each cycle, the instruction issue control means classifies the plurality of instructions decoded by the decoding means for each execution condition in advance, A processor characterized by referring to a condition flag for each classification to determine whether it is a valid instruction that needs to be executed or an invalid instruction that does not need to be executed. The processor of claim 1, wherein
Parallel execution boundary information indicating whether each instruction is a boundary for parallel execution among the plurality of instructions is specified,
The instruction issue control means further has a function of referring to the parallel execution boundary information of each instruction and detecting a group of instructions to be executed in this cycle. The processor of claim 7, wherein
The instruction issue control means, when all instructions before the boundary instruction detected in the parallel execution boundary information in the instruction are deleted as invalid instructions that do not need to be executed, the parallel execution boundary of the boundary instruction A processor characterized by detecting a new parallel execution boundary of the current cycle by invalidating information and referring to parallel execution boundary information of an instruction after the boundary instruction. Command supply means for supplying a plurality of commands;
Decoding means for decoding each of the plurality of instructions;
An instruction issue control means for determining an instruction or set of instructions for executing a valid operation;
A processor comprising an execution means for specifying an operation of each instruction in the plurality of instructions and executing one or a plurality of operations based on the specification;
The instruction issuance control means detects a combination of instructions such that a function of a plurality of instructions can be realized by a single instruction from the group of instructions decoded by the decoding means, and determines the plurality of instructions. A processor having a function of being combined so as to be treated as a single instruction. The processor of claim 9, wherein
The instruction issue control means detects a remaining instruction group that is neither an execution target, a deletion target, nor a connection target in this cycle, and sets these instruction groups as a target of issue in the next cycle or later. A processor further having a function of controlling.

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