JPS62115541A - Microinstruction branch address generating system - Google Patents

Abstract

PURPOSE:To generate quickly a head address of a microinstruction by reading the next byte directly when it is judged that an operation code part is bridged over the next type from the content of the most significant byte. CONSTITUTION:A machine word instruction read from a main storage device 1 is set to an instruction fetch register FR 2. The operation code of a machine word instruction in an FR0 is read via a changeover circuit 6, becomes a low- order type of a microinstruction address 4 and an address of a BF instruction enters a high-order part. When the operation code of the machine word instruction is a 2-byte instruction briged over an FR1, the presence of the 2-byte instruction is identified as the execution result of the microinstruction by the FR0. When the BFF instruction of the microinstruction is coded, a level of a signal A goes to '1' and the changeover circuit 6 selects the FR1. Then the microinstruction address using the content of the fR1 as a low-order byte and using an address of the BFF instruction as a high-order byte is generated.

Description

[Detailed Description of the Invention] [Summary] The invention is configured such that a logical operation related to the execution of one instruction (machine language instruction) is realized by executing a plurality of microinstructions, and the first address of the plurality of microinstructions is Conventionally, in information processing devices, the most significant byte of the opcode part of the instruction to be executed is generated based on the contents of the most significant byte or the most significant byte and the byte next to the most significant byte. When it is determined that the opcode includes the next byte after the most significant byte depending on the contents, an arithmetic system is used to shift the contents of that byte to the position of the most significant byte, read the contents again, and based on this, Since control was performed by generating the start address of a microinstruction, the processing speed was slow and the processing performance of the arithmetic system was affected. In order to solve these conventional drawbacks, the present invention selects either the most significant byte of the opcode part of the instruction to be executed or the byte located next to the byte and outputs its contents. When it is determined from the contents of the most significant byte that the opcode section spans the next byte, the first address of the microinstruction can be quickly generated by directly reading the next byte. This technology discloses a technology related to a control method that can be controlled.

[Industrial Application Field] The present invention relates to controlling the execution of machine language instructions in an information processing device, and in particular, to a method for realizing logical operations related to the execution of machine language instructions using a plurality of microinstructions (microsteps). This relates to the generation method of the start address of the microstep in the case of a case.

[Prior Art] In information processing devices, logical operations such as decoding and executing machine language instructions are realized by a combination of a limited number of basic operations such as accessing the main memory, shifting, and operations using adders. Ru.

Such basic operations may be realized by a hardware logic circuit or by executing several instructions called microinstructions that perform basic logic operations.

The latter case in which logical operations related to the execution of machine language instructions are performed by executing a plurality of microinstructions is hereinafter referred to as a microprogram method, and a collection of a plurality of microinstructions is also referred to as a microstep.

In the microprogram type information processing apparatus as described above, a method is often adopted in which a start address of a microstep to be operated is generated from an operation code of a machine language instruction to be executed.

In other words, the start address of the microstep that realizes the logical operation related to the execution of each machine language instruction is determined corresponding to the opcode of each machine language instruction, so by decoding or modifying the opcode, you can quickly The start address of the microstep can be generated.

When generating the address, the opcode of the machine language instruction is set in the instruction fetch register (hereinafter also referred to as PR register), and its most significant byte (F RO) is
A method is adopted in which an address is generated from the contents of the address.

Further, generation of such an address is performed by a microinstruction called a BF instruction.

FIG. 2 is a diagram explaining the above-mentioned conventional microinstruction address generation system, in which 1 is the main memory, 2 is the FR register, 3 is the arithmetic circuit, 4 is the microinstruction address, and 5
represents a microinstruction.

In FIG. 2, a machine language instruction read from main memory 1 is set in FR register 2, and the contents of its most significant byte FRO are read, thereby generating the address of the microinstruction.

[Problems to be Solved by the Invention] Not only the most significant byte but also the next byte (FRl in FIG. 2) may be used as an operation code for a machine language instruction (hereinafter also referred to as a 2-byte instruction). this is,
This is because when there are many types of instructions, one byte of FRO may not be enough to represent the numerical value for addressing.

Conventionally, when an opcode straddles FRI, by executing a BP instruction with the contents of FRO, it is identified that it is a 2-byte instruction, and the arithmetic circuit 3 in FIG. and move the contents of PR register 2 1 to the left.
F moved to the FRO position by byte shifting
This method relied on a method of generating a microinstruction address by executing the BF instruction again with the contents of Rl.

In this conventional method of generating a microinstruction address from the opcode of a machine language instruction, the problem is that it takes a very long time because the complicated control described above has to be performed in the case of 2-byte instructions. There was a point. Also, when shifting the contents of FRl to the FRO position, since an arithmetic circuit is used, other microinstructions (for example, address calculation using machine language instruction operands, etc.)
There was a problem that the processing of

In view of these conventional problems, it is an object of the present invention to provide an information processing device that can quickly generate a microinstruction address without using an arithmetic circuit even in the case of a 2-byte instruction. It is an object.

[Means for solving the problem] According to the present invention, this object is achieved by executing a logical operation related to the execution of one instruction by executing a plurality of microinstructions, as described in the claims. an information processing device configured as shown in FIG. means for selecting either the most significant byte of the opcode portion of the instruction to be executed or the next byte of the most significant byte and outputting the content thereof; This is achieved by a microinstruction branch addressing method that is characterized by selecting a byte and using the value of the byte to generate the start address of the microinstruction to be executed.

[Embodiment] FIG. 1 is a diagram illustrating an address generation system according to an embodiment of the present invention, in which 1 to 5 are the same as in FIG. 2, and 6 represents a switching circuit.

In FIG. 1, machine language instructions read from main memory 1 are set in FR register 2. In FIG. Then, the contents of FRO (opcode of machine language instruction) are read out via switching circuit 6 and become the lower byte of microinstruction address 4.

Further, the upper part of the microinstruction address 4 contains the address of the BF instruction. In addition to the BF instruction, a BFF instruction is also prepared as an address generation instruction.

If the operation code of the machine language instruction is a 1-byte instruction with only FRO, the target microstep can be immediately executed using the address generated in this way.

If the opcode of the machine language instruction is a 2-byte instruction that straddles the FRI, it is identified as a 2-byte instruction as a result of the execution of the microinstruction by the FRO. Then, when the BFF instruction is coded as a microinstruction, the "A" signal becomes "1", and at this time, the switching circuit 6 selects FRI. Then, a microinstruction address is generated in which the content of the FRI is the lower byte and the address of the BFF instruction is the upper byte.

[Effects of the Invention] As described above, according to the system of the present invention, in an information processing apparatus configured to realize logical operations related to the execution of machine language instructions by operations of a plurality of microinstructions,
Even if the opcode of a machine language instruction spans 2 bytes, it is possible to quickly generate the start address of the microinstruction, and since no arithmetic circuit is used to generate the address, it is easy to process other microinstructions. It has the advantage of having no influence.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining an address generation method according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional microinstruction address generation method. 1... Main storage device, 2... FR register, 3...
Arithmetic circuit, 4...Microinstruction address, 5...Microinstruction, 6...Switching circuit agent Patent attorney Sada Igeta - Mi. ---Ippa

Claims (1)

[Claims] It is configured such that the logical operation related to the execution of one instruction is realized by executing multiple microinstructions, and the first address of the multiple microinstructions is the most significant byte or the most significant byte of the opcode part of the instruction to be executed. and the contents of the byte next to the most significant byte.The information processing device selects either the most significant byte of the opcode section of the instruction to be executed or the byte next to the most significant byte, and A microcontroller comprising: means for outputting contents; the means selects a byte next to the most significant byte of the operation code section, and uses the value of the byte to generate a start address of a microinstruction to be executed. Instruction branch address method.