JP2637070B2 - Micro instruction start address generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The logic operation related to the execution of one instruction (machine language instruction) is implemented by executing a plurality of microinstructions, and the start addresses of the plurality of microinstructions are In an information processing apparatus that is generated based on the most significant byte of the operation code portion of the instruction to be executed or the content of the most significant byte and the content of the byte next to the most significant byte, conventionally, the content of the most significant byte of the instruction to be executed is When the operation code determines that the next byte of the most significant byte is also included in the operation code, the contents of the byte are shifted to the position of the most significant byte using the arithmetic system, and the content is read out again. Since the control for generating the head address of the instruction is performed, the processing speed is slow, and the processing capability of the arithmetic system is affected. The present invention solves such a conventional drawback by selecting either the most significant byte of the opcode portion of the instruction to be executed or the byte located next to the byte and outputting the content. When it is determined from the contents of the most significant byte that the opcode portion extends to the next byte, the head address of the microinstruction can be quickly generated by directly reading out the next byte. A technique relating to a control method is disclosed.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of execution of a machine language instruction of an information processing apparatus, and in particular, implements a logical operation related to execution of a machine language instruction by a plurality of micro instructions (micro steps). The method relates to the generation method of the head address of the micro step in the case.

2. Description of the Related Art In an information processing apparatus, logical operations such as decoding and execution of a machine language instruction are realized by a combination of a limited number of basic operations such as access to a main storage device, a shift, and an operation by an adder. You.

Such a basic operation may be realized by a hardware logic circuit, or may be realized by executing some instructions for performing a basic logical operation called microinstructions.

The latter case in which the logical operation related to the execution of the machine language instruction is performed by executing a plurality of microinstructions is hereinafter referred to as a microprogram method, and a group of a plurality of microinstructions is also referred to as a microstep.

As described above, a microprogram type information processing apparatus often adopts a method of generating a head address of a microstep to be operated from an operation code of a machine language instruction to be executed.

In other words, since the start address of the microstep that implements the logical operation related to the execution of each machine language instruction is determined corresponding to the operation code of each machine language instruction,
By decoding or modifying the opcode,
The start address of the microstep can be generated quickly.

When generating the address, a method is adopted in which the operation code of the machine language instruction is set in an instruction fetch register (hereinafter also referred to as an FR register), and the address is generated from the contents of the most significant byte (FR0). The generation of such an address is performed by a micro instruction called a BF instruction.

FIG. 2 is a diagram for explaining the conventional microinstruction address generation method described above, wherein 1 is a main memory, 2 is an FR register, 3 is an arithmetic circuit, 4 is a microinstruction address, and 5 is a microinstruction. I have.

In FIG. 2, the machine language instruction read from the main memory 1 is set in the FR register 2 and its most significant byte
The contents of FR0 are read, thereby generating the address of the microinstruction.

[Problems to be Solved by the Invention] Not only the most significant byte but also the next byte (FR1 in FIG. 2) may be used as an operation code of a machine language instruction (hereinafter also referred to as a two-byte instruction). This is because when there are many types of instructions, the numerical expression for addressing may not be sufficient with only one byte of FR0.

Conventionally, when the operation code straddles FR1, by executing the BF instruction with the contents of FR0, it is identified that the instruction is a 2-byte instruction, and the arithmetic circuit 3 in FIG. The method relies on shifting the contents of the FR register 2 to the left by one byte and executing the BF instruction again with the contents of FR1 moved to the position of FR0 to generate a microinstruction address.

In such a conventional method of generating a micro-instruction address from an operation code of a machine-language instruction, in the case of a 2-byte instruction, the complicated control as described above must be performed, which takes a very long time. There was a point. In addition, when shifting the contents of FR1 to the position of FR0, there is a problem that the processing of other microinstructions (for example, address calculation using operands of machine language instructions) is affected because the arithmetic circuit is used. there were.

In view of such a conventional problem, the present invention does not use an arithmetic circuit even in the case of a 2-byte instruction,
It is an object of the present invention to provide an information processing device capable of quickly generating a micro instruction address.

[Means for Solving the Problems] According to the present invention, this object is attained by the means described in the “claims”.

That is, the present invention is configured such that the logical operation related to the execution of one instruction is realized by executing a plurality of microphone instructions, and the head address of the plurality of microinstructions indicates the operation code of the instruction to be executed. In the information processing device generated based on the most significant byte or the most significant byte and the content of the byte next to the most significant byte, the content of the most significant byte of the operation code portion of the instruction to be executed is output or Means for switching whether or not to output the content of the byte next to the byte, and from the execution result of the microinstruction using the content of the most significant byte of the opcode portion of the instruction output from the means, the byte next to the most significant byte is provided. When it is determined that a packet is also necessary, the above means should select the byte next to the most significant byte of the opcode portion and execute the operation using the value of the byte. A microinstruction head address generation method for generating a start address of Micro instruction.

Embodiment FIG. 1 is a diagram for explaining an address generation method according to an embodiment of the present invention, wherein 1 to 5 are the same as those in FIG. 2, and 6 indicates a switching circuit.

In FIG. 1, a machine language instruction read from a main storage device 1 is set in an FR register 2. Then, the contents of FR0 (the operation code of the machine language instruction) are read out via the switching circuit 6, and this is the lower byte of the microinstruction address 4. The address of the BF instruction is placed in the upper part of the micro instruction address 4. The BF instruction is a pattern of an instruction type of the microinstruction. In this case, the microaddress in which the present microinstruction is described is included in the upper part of the instruction address 4. The timing at which the micro address of the BF instruction enters the upper part of the instruction address 4 can be the time when the BF instruction is issued.

Also, besides the BF instruction,
Instructions are also provided. The BFF instruction is also a pattern of the instruction type of the micro instruction like the BF instruction. When the BFF instruction is issued, the micro address in which the BFF instruction is described may be placed in the upper part of the instruction address 4.

Microinstruction 5 enters upper part of instruction address 4
This is the micro address of the BF instruction or the micro address of the BFF instruction. By setting the micro address as the upper address in the head address of the macro instruction, it is possible to determine from which part of the memory where the micro instruction is stored the part for storing the head address of the macro instruction.

If the operation code of the machine language instruction is a one-byte instruction consisting of only FR0, the intended microstep can be immediately executed by using the address generated in this way.

If the operation code of the machine language instruction is a two-byte instruction straddling FR1, it is identified that the instruction is a two-byte instruction as a result of execution of the micro instruction by FR0. And when the BFF instruction is coded by the micro instruction, the “A” signal becomes “1”
At this time, the switching circuit 6 selects FR1. Then, a microinstruction address is generated in which the contents of the FR1 are set to the lower byte and the address of the BFF instruction is set to the upper byte.

[Effects of the Invention] As described above, according to the method of the present invention, in an information processing apparatus configured to implement a logical operation related to execution of a machine language instruction by operations of a plurality of microinstructions, Even if the operation code of is two bytes long, the head address of the microinstruction can be quickly generated, and the operation circuit is not used in generating the address, which affects the processing of other microinstructions. There is an advantage that there is no.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an address generation system according to one embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional microinstruction address generation system. 1 ... Main storage device, 2 ... FR register, 3 ... Operation circuit, 4 ... Micro instruction address, 5 ... Micro instruction, 6 ... Switching circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takato Noda 1015 Uedanaka, Nakahara-ku, Kawasaki City Inside Fujitsu Limited (72) Inventor Kenichi Abo 1015 Uedanaka, Nakahara-ku, Kawasaki City Fujitsu Limited (72) Invention Person Masayoshi Takei 1015 Kamiodanaka Nakahara-ku, Kawasaki City Inside Fujitsu Limited (72) Inventor Kazuyasu Nonomura 1015 Kamiodanaka Nakahara-ku Kawasaki City Inside Fujitsu Limited (72) Ryoichi Nishimachi 1015 Kamiodanaka Nakahara-ku Kawasaki City Fujitsu Limited (72) Inventor Yasutoshi Sakurai 1015 Uedanaka, Nakahara-ku, Kawasaki City Fujitsu Limited (56) References JP-A-54-23342 (JP, A) JP-A-57-106957 (JP, A)

Claims (1)

(57) [Claims] The present invention is configured so that a logical operation related to execution of one instruction is realized by executing a plurality of microphone instructions, and a start address of the plurality of micro instructions is the last address of an operation code section of an instruction to be executed. In an information processing device generated based on the contents of the upper byte or the most significant byte and the content of the byte next to the most significant byte, the contents of the most significant byte of the opcode portion of the instruction to be executed are output or the most significant byte is output. Means for switching whether to output the contents of the next byte of the instruction, and from the execution result of the microinstruction using the contents of the most significant byte of the opcode portion of the instruction output from the means, the next byte of the most significant byte If it is determined that the operation is necessary, the means selects the next byte after the most significant byte of the operation code section and executes the microphone to be executed using the value of the byte. Microinstruction head address generation method and generates the first address of the instruction.