JPS6049935B2 - Microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for generating a start address of a routine from a macro instruction in an information processing apparatus using microprogram control.

FIG. 1 shows an example of the configuration of a device for generating a start address of a microprogram routine from a macro instruction used in a conventional microprogram control information processing device.
In Figure 1, 1 is an instruction register (IR) that stores macro instructions, and 2 is an address conversion circuit (A
C), 3 is a microinstruction register (μIAR) that stores the address of a microinstruction, 3a is +1
circuit, 4 is a control memory that stores the microprogram (
CM). The address conversion circuit 2 receives the instruction code OP from the instruction register 1 and generates the start address of the microprogram routine. Usually, the address conversion circuit 2 is realized by a decoder circuit using wired logic, a read-only memory (ROM), a programmable logic array (PLA), or the like. In such a configuration, when the start address of a microprogram routine is generated from a macro instruction that includes an instruction code and an address modification code that specifies an address modification method for an operand, the following problem occurs.

Since the address modification code is input in addition to the instruction code (OP) as an input to the address conversion circuit 2, the number of gates or the memory capacity of the address conversion circuit 2 has increased. Furthermore, since it is necessary to support several types of address modification methods, such as register indirect modification and index modification, address modification is performed for the source operand and the destination operand, respectively. A method that executes a macro instruction with address modification, a method of providing a microprogram routine in the control memory that executes register indirect modification, index modification, etc. for each macro instruction, or a method of creating a subroutine from the microprogram routine and using the macro instruction A method is known in which a subroutine is linked to a subroutine using a subroutine jump instruction or return instruction each time it is executed. However, the former method has the disadvantage that the microprogram routine that executes address modification becomes redundant and increases the memory capacity, while the latter method requires a jump instruction, which increases the processing time of macro instructions and increases the memory capacity. The disadvantage was that it also increased. SUMMARY OF THE INVENTION Accordingly, the present invention aims to improve the above-mentioned drawbacks of the prior art, and its purpose is to provide a microprogram control method that can reduce both processing time and memory capacity.

A feature of the present invention to achieve this object is to provide an address conversion circuit for executing macro instruction operations and an address conversion circuit for address modification. The purpose is to generate the start address of the microprogram routine by switching the conversion circuit. Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diaphragm of a configuration example of a device for generating a start address of a microprogram routine from a macro instruction according to the present invention. The same reference numbers in FIG. 2 as in FIG. 1 indicate the same parts. 5 is an instruction register (IR) for storing macro instructions; 6 is a first address conversion circuit that receives the instruction code (0P code) of the macro instruction; It outputs an output signal 8 that distinguishes whether the instruction is a macro instruction accompanied by address modification or not.

A second address conversion circuit 7 receives the address modification code (M) of the macro instruction, and outputs the start address 10 of the microprogram routine for calculating the effective address of the operand and fetching the operand.

11 is reset by a signal (EOI) that specifies the end of a microprogram routine that executes a fetch of a macro instruction, and a signal (EOA) that specifies the end of calculation of an execution address of an operand and execution of a fetch of an operand.
This is a flip-flop that is reset by .

13 is an AND circuit which receives the output signal 8 and the flip-flop 11, and a switching circuit consisting of a COAND circuit 1, an AND circuit 15, and an OR circuit 16 switches between the first address 9 and the first address 10.

In this configuration, when the execution of the fetch of the macroinstruction is finished, the microinstruction generates the (EOI) signal to set the flip-flop 11 and output signal 12.
becomes the logic level ゜゛HighFl゛.

When the macro instruction involves address modification, the address conversion circuit 6 sets the output signal 8 to the logic level "High".Therefore, the output of the AND circuit 13 has the logic level ゜゜Hjgh.
Therefore, the start address 10 generated from the address conversion circuit 7 is selected as the start address of the microprogram routine. Once the effective address of the operand has been calculated and the operand has been fetched, the microinstruction generates the (EOA) signal to reset flip-flop 11 and output signal 12 to a logic level 1.
At this time, the output of the AND circuit 13 becomes the logic level ゜゜10w゛, so the first address 9 generated from the address conversion circuit 6 is selected as the first address of the microprogram routine, and the operation of the macro instruction is executed. If the macro instruction does not involve address modification, the address translation circuit 6 sets the output signal 8 to the logic level "L0w". At this time, the output of the AND circuit 13 becomes the logic level ゜゜L0w゛ regardless of the logic state of the output signal 12 of the flip-flop 11, so the first address 9 generated from the address conversion circuit 6 is selected as the first address of the microprogram routine. Then, the operation of the macro instruction is executed. As explained above, a first address conversion circuit for executing macro instruction operations and a second address conversion circuit for address modification are provided, and the two address conversion circuits are switched according to the instruction code of the macro instruction to perform the microprogram routine. By generating the start address of , the microprogram routine for executing operations and the microprogram routine for modifying addresses can be modularized, and the microprogram routine for address modification can be shared by each macro instruction.

Furthermore, no subroutine jump or return instruction is required to link the two microprogram routines. Therefore, there are advantages in that the control memory capacity can be reduced and the processing speed of macro instructions can be increased. Furthermore, switching between the two address conversion circuits described above is performed by the AND of the output signal indicating the presence or absence of address modification and the switching signal provided in a predetermined field of the macro instruction. Since the fetch routine can be shared, the control memory capacity can be reduced. Note that the above two address conversion circuits can be realized by a decoder circuit configured with wired logic, a ROM (read-only memory), a PLA (programmable logic array), or the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional starting address generator for a microprogram routine, and FIG. 2 is a block diagram of a device for generating a starting address for a microprogram routine according to the present invention. 1... Instruction register (IR) for storing macro instructions, 2... Address conversion circuit, 3... Micro instruction address register (μIAR)
), 3a...+1 circuit, 4...Control memory (CM)
, 5... instruction register, 6... first
Address conversion circuit, 7...Second address conversion circuit, 8
, 9, 10... Output signal, 11... Flip-flop, 12... Output signal, 13, 14, 15... AND circuit, 16... OR circuit.

Claims (1)

[Claims] 1 In a microprogram-controlled information processing device,
A microprogram control method that generates the start address of a microprogram routine from a macroinstruction through the following steps; (a) A microprogram routine that executes arithmetic operations of the macroinstruction from the instruction code of the macroinstruction using the first address conversion circuit. A first start address and a first output signal including information regarding whether or not the macro instruction requires address modification are output; (b) the second address conversion circuit converts the address modification code of the macro instruction into The second microprogram routine that performs the calculation of the execution address of the operand and the fetching of the operand.
Outputs the start address and (c) is set by a signal that specifies the end of the microprogram routine that executes the fetch of the macro instruction, and specifies the end of the microprogram routine that executes the calculation of the execution address of the operand and the fetch of the operand. An output is taken from the flip-flop that is reset by the signal, (d) an AND circuit calculates the AND of the output of the flip-flop and the first output signal, and (e) the output of the AND circuit determines the logical product of the first output signal. The first address and the second first address are switched to generate the first address of the microprogram routine.