JPH04355832A - Microprogram controller - Google Patents

Abstract

PURPOSE:To add a new instruction and to extend and change the function of an instruction without requiring the circuit change of an instruction decoder. CONSTITUTION:A micro RAM 101 where extended micro instructions are stored, a mask address register 102, an extended micro address register 103 where an extended micro address corresponding to the mask address is held, a comparing circuit 104 which compares the mask address and the micro address with each other, an external terminal 106 which designate whether the micro instruction should be switched to the extended micro instruction or not, and a selecting circuit 110 which switches the comparison result of the comparing circuit 104 and the micro address inputted to a micro pointer 6 by setting of the external terminal 106 are provided, and thereby, it is easily selected whether the extended micro instruction should be used or not, and the extended micro instruction is easily tested.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram control device for a microprocessor that controls arithmetic processing using microinstructions, and more particularly to a microprogram control device having means for switching functions of microinstructions.

0002

2. Description of the Related Art FIG. 2 is a block diagram showing the configuration of a conventional microprogram control device. In FIG. 2, 1 is a micro-ROM as a micro-instruction storage means for storing micro-instructions, 2 is a micro-instruction read out from the micro-ROM 1, 3 is a micro-instruction register that holds micro-instructions 2, and 13 is a micro-instruction register for storing micro-instructions 2. Among them, the arithmetic control microinstruction that controls the arithmetic unit, 4 designates a microdecoder that decodes the arithmetic control microinstruction 13, 5 designates the control signal decoded by the microdecoder 4, and 6 designates the entry in which the microinstruction 2 is stored. Micro address, 7 is a micro pointer that stores micro address 6, 8 is a micro incrementer that increases the micro address stored in micro pointer 7 by 1, 9 is a micro next address that specifies the next micro address among micro instructions 2 , 10 is a micro next address register that stores micro next address 9, 11 is a micro stack register that stores a return destination micro address when executing a subroutine with a micro instruction, 1
2 is a micro address bus for storing a micro address for accessing the micro ROM 1 in the micro pointer 7;

Next, the operation of the conventional microprogram control device will be explained. First, I will briefly explain microinstructions. One microinstruction is divided into a part that controls the arithmetic unit and a part that controls reading of the next microinstruction. The part that controls reading the next microinstruction includes reading the microinstruction at the next microaddress, jumping to the specified microaddress,
There are operations such as jumping to a subroutine and returning from a subroutine. In the part that controls the arithmetic unit,
Transfer, addition, subtraction, etc.

The instruction code is fetched from an external memory (not shown) and decoded by an instruction decoder (not shown). Based on this decoding result, a microaddress for implementing the operation of that instruction is generated. This microaddress is output to the microaddress bus 12 and stored in the micropointer 7. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro ROM 1 and stored in the micro instruction register 3.

When executing the microinstruction at the next microaddress, that is, when the microinstruction does not branch, or when one instruction is processed by one microinstruction, the part that controls the arithmetic unit of microinstruction 2 (the arithmetic control The microinstruction 13) is inputted from the microinstruction register 3 to the microdecoder 4, decoded by the microdecoder 4, and generates a control signal 5 for controlling an arithmetic unit and the like. Then, the microaddress 6 for processing the next instruction is input from the microaddress bus 12 to the micropointer 7, and a new microinstruction 2 is read from the microROM 1.

When one instruction is processed by a plurality of microinstructions, microinstruction 2 is read from microROM 1 and held in microinstruction register 3. At the same time, the microaddress of the micropointer 7 is incremented by 1 by the microincrementer 8. The +1 microaddress is stored in the micropointer 7. This +
The next microinstruction 2 is read from the microROM 1 using the microaddress 6 which is set to 1.

When the microinstruction 2 indicates a branch, the micronext address 9 of the microinstruction 2 held in the microinstruction register 3 is set to the micronext address register 10.
Enter. At the same time, the arithmetic control microinstruction 13 is input from the microinstruction register 3 to the microdecoder 4. The microdecoder 4 generates the control signal 5 as described above. Micropointer 7 has microaddress bus 1
2, the macro next address is transferred from the micro next address register 10. The next microinstruction is executed at microaddress 6 by micropointer 7
Read from OM1.

When microinstruction 2 indicates a subroutine branch, micronext address 9 of the microinstructions held in microinstruction register 3 is input to micronext address register 10 . At the same time, the arithmetic control microinstruction 13 is transferred from the microinstruction register 3 to the microdecoder 4.
is input. Furthermore, the micro address 6 of the micro pointer 7 is incremented by 1 by the micro incrementer 8 and stored in the micro stack register 11 as the return destination address of the micro subroutine. The microdecoder 4 generates the control signal 5 as described above. Micro pointer 7
The macro next address is transferred from the micro next address register 10 through the micro address bus 12. The next microinstruction is read from the microROM 1 at microaddress 6 by this micropointer 7.

When the microinstruction 2 indicates a return from a microsubroutine, the return destination address of the subroutine is stored in the micropointer 7 from the microstack register 11 via the microaddress bus 12 as the next microaddress. The next microinstruction 2 is read from the microROM 1 at the microaddress 6 by the micropointer 7.

0010

A conventional microprogram control device reads and executes microinstructions stored in a microROM. Therefore, when adding new instructions or expanding or changing the functions of the instructions, it is necessary to add a new micro ROM. Then, in order to be able to generate micro-addresses for the micro-ROM with an instruction decoder added, a major circuit change was made.
The problem was that the development period was extended.

[0011] This invention was made in order to solve the above-mentioned problems, and it is possible to add new instructions or expand or change the function of an instruction in a short development period without the need to change the circuit of the instruction decoder. The purpose of the present invention is to provide a microprogram control device that can perform the following steps.

0012

[Means for Solving the Problems] A microprogram control device according to the present invention includes a microinstruction storage means (micro ROM 1) for storing microinstructions, and an expanded microinstruction storage for storing extended microinstructions obtained by extending the above-mentioned microinstructions. (a micro RAM 101), a micro pointer 7 that holds a micro address for accessing the micro instruction storage means, and a mask address storage means (a mask address memory) that stores a mask address for extending the micro instruction to the extended micro instruction. register 102), extended microaddress storage means (extended microaddress register 103) for storing an extended microaddress corresponding to the mask address, and address comparison means (comparison circuit 104) for comparing the mask address and the microaddress. , an external terminal 106 for setting whether or not to use the extended microinstruction;
It is provided with selection means (selection circuit 110) for selecting the micro address and the extended micro address according to the comparison result of the set value to the external terminal and the address comparison means and outputting the selected micro address to the micro pointer 7.

[0013]

[Operation] The micro-instruction storage means (micro-ROM 1) stores micro-instructions, and the extended micro-instruction storage means (micro-RAM 101) stores extended micro-instructions which are expanded micro-instructions. The micropointer 7 holds a microaddress for accessing the microinstruction storage means, and the mask address storage means (mask address register 1
02) stores a mask address for expanding a microinstruction to an extended microinstruction. The extended micro address storage means (extended micro address register 103) stores the extended micro address corresponding to the mask address, and the address comparison means (comparison circuit 104) compares the mask address and the micro address. The external terminal 106 is used to set whether or not to use the extended microinstruction, and the selection means (selection circuit 110) selects the microaddress and the extended microaddress according to the comparison result of the setting value to the external terminal 106 and the address comparison means. is selected and output to the micropointer 7.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of a microprogram control device according to an embodiment of the present invention. Figure 1
Components corresponding to those shown in FIG. 2 are given the same reference numerals, and their explanations will be omitted. In Figure 1, 1
01 is a micro RAM as an expansion microinstruction storage means for storing expanded microinstructions obtained by expanding and changing microinstructions, and 102 is a mask address memory storing mask addresses for expanding and changing microinstructions into expanded microinstructions. mask address register as a means,
103 is an extended micro address register as an extended micro address storage means for storing an extended micro address corresponding to a mask address; 104 is an address for comparing the micro address output to the micro address bus 12 and the mask address of the mask address register 102; A comparison circuit as a comparison means, 105 is a comparison circuit 10
A match signal generated when the comparison results match in 4,
106 is an external terminal for setting whether to use extended microinstructions, 107 is an extended microinstruction enable signal set to the external terminal 106, and 108 is a match signal 1.
05 and the extended microinstruction enable signal 107, 109 is the microaddress selection signal that is the output of the AND circuit 108, and 110 is the external terminal 1.
06 and the comparison result of the comparator circuit 104, the microaddress of the microaddress bus 12 and the extended microaddress of the extended microaddress register 103 are selected and outputted to the micropointer 7.

Next, the operation of this embodiment will be explained. First, I will briefly explain microinstructions. One microinstruction is divided into a part that controls the arithmetic unit and a part that controls reading of the next microinstruction. The part that controls reading of the next microinstruction includes operations such as reading the microinstruction at the next microaddress, jumping to a specified microaddress, jumping to a subroutine, and returning from a subroutine. The parts that control the arithmetic units include transfer, addition, subtraction, etc.

The operation when the external terminal 106 is set to use extended instructions will be explained. The instruction code is fetched from an external memory (not shown) and decoded by an instruction decoder (not shown). A microaddress for implementing the operation of the instruction is generated based on the decoding result. This microaddress is microaddress bus 12.
is output to. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. Match signal 105 and extended microinstruction enable signal 107
If the AND is taken and a match signal 105 is generated, the external terminal 106 is set to use the extended microinstruction, so the selection signal 109 selects the output of the microaddress register 103 and transfers it to the micropointer 7. Enter. The micro RAM 101 is accessed by the micro address 6 stored in the micro pointer 7,
Microinstruction 2 corresponding to microaddress 6 is output from microRAM 101 and stored in microinstruction register 3. If the match signal 105 is not generated, the selection signal 109 selects the micro address on the micro address bus 12 and inputs it to the micro pointer 7. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro address 6
A microinstruction 2 corresponding to the microinstruction 2 is output from the microROM 1 and stored in the microinstruction register 3.

When executing the microinstruction at the next microaddress, that is, when the microinstruction does not branch, or when one instruction is processed by one microinstruction, the arithmetic control microinstruction 13 of the microinstruction 2 is stored in the microinstruction register. 3 to a micro-decoder 4, the micro-decoder 4 decodes the control signal 5, and generates a control signal 5 for controlling an arithmetic unit and the like. Then, a microaddress for processing the next instruction is generated by the decoder and output to the microaddress bus 12. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. The match signal 105 and the extended microinstruction enable signal 107 are ANDed, and if the match signal 105 is generated, the external terminal 106 is set to use the extended microinstruction, so the selection signal 109 is set to the microaddress. The output of register 103 is selected and input to micropointer 7. The micro RAM 101 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro RAM 101 and stored in the micro instruction register 3. If the match signal 105 is not generated, the selection signal 109 causes the micro address bus 12 to
select the micro address and input it to the micro pointer 7. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is written to the micro RO.
It is output from M1 and stored in the microinstruction register 3.

When one instruction is processed by a plurality of microinstructions, microinstruction 2 is read out from microRAM 101 and held in microinstruction register 3. At the same time, the microaddress of the micropointer 7 is incremented by 1 by the microincrementer 8. The +1 microaddress is stored in the micropointer 7. The next microinstruction 2 is read using the microaddress 6 which is incremented by one.

When the microinstruction 2 indicates a branch, the micronext address 9 of the microinstruction 2 held in the microinstruction register 3 is set to the micronext address register 10.
Enter. At the same time, the arithmetic control microinstruction 13 is input from the microinstruction register 3 to the microdecoder 4. The microdecoder 4 generates the control signal 5 as described above. In the next step, micro next address register 1
The microaddress stored in 0 is output to the microaddress bus 12. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. If the match signal 105 and the extended microinstruction enable signal 107 are ANDed and the match signal 105 is generated, the external terminal 106 is set to use the extended microinstruction, so the selection signal 109 is set to use the extended microinstruction. The output of the address register 103 is selected and input to the micropointer 7. The micro RAM 101 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro RAM 101 and stored in the micro instruction register 3. If the match signal 105 is not generated, the selection signal 109 causes the micro address bus 1 to
Select micro address 2 and input it to micro pointer 7. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is transferred to the micro R.
It is output from OM1 and stored in the microinstruction register 3.

When microinstruction 2 indicates a subroutine branch, micronext address 9 of the microinstructions held in microinstruction register 3 is input to micronext address register 10 . At the same time, arithmetic control microinstruction 1
3 is input from the microinstruction register 3 to the microdecoder 4. Furthermore, the micro address 6 of the micro pointer 7 is incremented by 1 by the micro incrementer 8 and stored in the micro stack register 11 as the return destination address of the micro subroutine. The microdecoder 4 generates the control signal 5 as described above. In the next step, the microaddress stored in the micronext address register 10 is output to the microaddress bus 12. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. If the match signal 105 and the extended microinstruction enable signal 107 are ANDed and the match signal 105 is generated, the external terminal 106 is set to use the extended microinstruction, so the selection signal 109 is set to the extended microinstruction enable signal 107. The output of register 103 is selected and input to micropointer 7. The micro RAM 101 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro RAM 101 and stored in the micro instruction register 3. If the match signal 105 is not generated, the selection signal 109 selects the micro address on the micro address bus 12 and inputs it to the micro pointer 7. Micro ROM by micro address 6 stored in micro pointer 7
1 is accessed, and microinstruction 2 corresponding to microaddress 6 is output from microROM 1 and stored in microinstruction register 3.

When the microinstruction 2 indicates a return from a microsubroutine, the return destination address of the subroutine is output from the microstack register 11 to the microaddress bus 12 as the next microaddress. This microaddress and the contents of the microaddress register 102 are compared by a comparator 104. If the match signal 105 and the extended microinstruction enable signal 107 are ANDed and the match signal 105 is generated, the external terminal 106 is set to use the extended microinstruction.
Selection signal 109 is extended micro address register 103
select the output and input it to the micropointer 7. The micro RAM 101 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is accessed from the micro RAM 10.
1 and stored in the microinstruction register 3. If the match signal 105 is not generated, the selection signal 109 selects the micro address on the micro address bus 12 and inputs it to the micro pointer 7. The micro address 6 stored in the micro pointer 7
OM1 is accessed, and microinstruction 2 corresponding to microaddress 6 is output from microROM1 and stored in microinstruction register 3.

The operation when the external terminal 106 is set not to use extended instructions will be explained. The instruction code is fetched from an external memory (not shown) and decoded by an instruction decoder (not shown). A microaddress for implementing the operation of the instruction is generated based on the decoding result. This microaddress is microaddress bus 1
2 is output. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. Match signal 105 and extended microinstruction enable signal 10
7 and the external terminal 106 is set not to use extended microinstructions, so the selection signal 109 is generated regardless of whether the match signal 105 is generated or not.
selects a micro address on the micro address bus 12 and inputs it to the micro pointer 7. The micro address 6 stored in the micro pointer 7
OM1 is accessed, and microinstruction 2 corresponding to microaddress 6 is output from microROM1 and stored in microinstruction register 3.

When executing the microinstruction at the next microaddress, that is, when the microinstruction does not branch, or when one instruction is processed by one microinstruction, the part that controls the arithmetic unit of microinstruction 2 (the arithmetic control micro The instruction 13) is inputted from the microinstruction register 3 to the microdecoder 4, decoded by the microdecoder 4, and generates a control signal 5 for controlling an arithmetic unit and the like. Then, a microaddress for processing the next instruction is generated by the decoder and output to the microaddress bus 12. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. The match signal 105 and the extended microinstruction enable signal 107 are ANDed, and the external terminal 106 is set not to use extended microinstructions, so the selection signal is not generated regardless of whether the match signal 105 is generated. 109 is micro address bus 1
Select micro address No. 2 and input it to micro pointer 7. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro ROM 1 and stored in the micro instruction register 3.

When one instruction is processed by a plurality of microinstructions, microinstruction 2 is read out from microROM 1 and held in microinstruction register 3. At the same time, the micropointer 7 is set by the microincrementer 8.
The microaddress of is incremented by +1. The +1 microaddress is stored in the micropointer 7. This +1
next microinstruction 2 by microaddress 6
Reads out.

When the microinstruction 2 indicates a branch, the micronext address 9 of the microinstruction 2 held in the microinstruction register 3 is set to the micronext address register 10.
Enter. At the same time, the arithmetic control microinstruction 13 is input from the microinstruction register 3 to the microdecoder 4. The microdecoder 4 generates the control signal 5 as described above. In the next step, micro next address register 1
The microaddress stored in 0 is output to the microaddress bus 12. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. The match signal 105 and the extended microinstruction enable signal 107 are ANDed, and the external terminal 106 is set not to use extended microinstructions, so the selection signal is not generated regardless of whether the match signal 105 is generated. 1
09 selects a micro address on the micro address bus 12 and inputs it to the micro pointer 7. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro ROM 1 and stored in the micro instruction register 3.

When microinstruction 2 indicates a subroutine branch, micronext address 9 of the microinstructions held in microinstruction register 3 is input to micronext address register 10 . At the same time, the arithmetic control microinstruction 13 is transferred from the microinstruction register 3 to the microdecoder 4.
is input. Furthermore, the micro address 6 of the micro pointer 7 is incremented by 1 by the micro incrementer 8 and stored in the micro stack register 11 as the return destination address of the micro subroutine. The microdecoder 4 generates the control signal 5 as described above. In the next step, the microaddress stored in the micronext address register 10 is output to the microaddress bus 12. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. The match signal 105 and the extended microinstruction enable signal 107 are ANDed, and the external terminal 106 is set not to use extended microinstructions, so the selection signal is not generated regardless of whether the match signal 105 is generated. 109 selects a micro address on the micro address bus 12 and inputs it to the micro pointer 7; The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7, and the micro instruction 2 corresponding to the micro address 6 is output from the micro ROM 1 and stored in the micro instruction register 3.

When the microinstruction 2 indicates a return from a microsubroutine, the return destination address of the subroutine is output from the microstack register 11 to the microaddress bus 12 as the next microaddress. This microaddress and the contents of the mask address register 102 are compared by a comparator 104. The match signal 105 is ANDed with the extended microinstruction enable signal 107;
Since the external terminal 106 is set not to use extended microinstructions, the selection signal 109 selects the microaddress on the microaddress bus 12 and sends it to the micropointer 7 regardless of whether the match signal 105 is generated or not.
Enter. The micro ROM 1 is accessed by the micro address 6 stored in the micro pointer 7,
Microinstruction 2 corresponding to microaddress 6 is output from microROM 1 and stored in microinstruction register 3.

The micro RAM mentioned above is freely rewritable, and by storing a desired extended micro program in advance, it can be expanded and changed into micro instructions having a desired function.

[0029]

As described above, according to the present invention, there are provided microinstruction storage means for storing microinstructions, extended microinstruction storage means for storing extended microinstructions obtained by extending the above microinstructions, and microinstruction storage means for storing extended microinstructions. a micropointer that holds a microaddress for accessing the microinstruction, a mask address storage means that stores a mask address for extending the microinstruction to the extended microinstruction, and an expansion microcontroller that stores the extended microaddress corresponding to the masked address. an address storage means, an address comparison means for comparing the mask address and the microaddress, an external terminal for setting whether or not to use the extended microinstruction, and a comparison between a set value to the external terminal and the address. The configuration includes a selection means for selecting the micro address and the extended micro address according to the comparison result of the means and outputting the selected micro address to the micro pointer, so that expansion can be performed by setting external terminals without changing the circuit of the instruction decoder. It is possible to easily select whether or not to use microinstructions, and therefore, new instructions can be added or the functions of the instructions can be extended and changed, and the extended microinstructions can be easily tested. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microprogram control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional microprogram control device.

[Explanation of symbols]

1 Micro ROM (micro instruction storage means) 7
Micro pointer 101 Micro RAM (extended micro instruction storage means) 102 Micro address register (mask address storage means) 103 Extended micro address register (extended micro address storage means) 104 Comparison circuit (comparison means) 106 External terminal 110 Selection circuit (selection means) )

Claims (1)

[Claims] 1. A microprogram control device for a microprocessor in which arithmetic processing is controlled by microinstructions, comprising a microinstruction storage means for storing microinstructions, and an extended microinstruction for storing extended microinstructions obtained by extending the above microinstructions. a storage means, a micropointer for holding a microaddress for accessing the microinstruction storage means, a mask address storage means for storing a mask address for expanding the microinstruction into the extended microinstruction, and a mask address corresponding to the mask address. an extended microaddress storage means for storing an extended microaddress to be used; an address comparison means for comparing the mask address and the microaddress; an external terminal for setting whether or not to use the extended microinstruction; A microprogram control device comprising: selection means for selecting the microaddress and the extended microaddress and outputting the selected microaddress to the micropointer based on a comparison result of the set value to the terminal and the address comparison means.