JPH04373022A - Microprogram control circuit - Google Patents

Abstract

PURPOSE:To reduce the development cost of a product incorporating a new function depending on a microinstruction and to shorten time for the development by extending or changing the functions according to the microinstruction without changing an instruction decoder part. CONSTITUTION:A microaddress 6a of the microinstruction selected by an instruction decoder 12 is compared with a mask address 31 by a microaddress comparator circuit 33. When the both addresses are coincident, a replacing microaddress 29 is selected by a microaddress selecting circuit 35, and a micro-ROM (microinstruction storing means) 1 is accessed by the replacing microaddress 29 in place of the microaddress 6a. Then, the function of the microinstruction designated by the microaddress 6a is switched with the function of the replacing microinstruction designated by the replacing microaddress 29.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram control circuit for a microprocessor that controls arithmetic processing using microinstructions, and more particularly to means for switching the functions of microinstructions.

0002

2. Description of the Related Art FIG. 10 shows an example of the configuration of a conventional microprogram control circuit. In the figure, reference numeral 1 denotes a micro RO as a micro instruction storage means for storing micro instructions.
M, 2a is microdata indicating the contents of the microinstruction read from the microROM 1, 3 is a microdata register as a microdata holding means that holds the microdata 2a, and 2b is a microdata register 3 that stores the microinstruction data from the microinstruction data. Microdata from which the next address information has been extracted, 4 is microdata 2
a microdecoder that decodes b and parameter information;
5 is a control signal decoded by the micro-decoder 4; 6a and 6b are micro-addresses that designate the execution entry of the micro-instruction; 7 is a micro-pointer as a micro-instruction access means for accessing the micro-instruction in the micro-ROM 1 by the micro-address 6b; 8 is a micro counter that counts up the micro address 6b of the micro pointer 7, and 6c is a micro counter 8.
9 is the next micro address that specifies the next micro address 6a based on the contents of the address field of the micro data 2a.
10 is a micro-next address register as micro-next address holding means for storing micro-next address 9;
1 is a micro stack register that stores a return destination micro address 6c when executing a subroutine using a micro instruction; 12 is an instruction decoder that decodes an instruction fetched from the outside; 13 is a decoder code decoded by the instruction decoder 12; 14 is a microaddress register that holds a microaddress code that specifies the start entry address of a microinstruction in the decoder code 13; 15 is a microparameter register that stores parameter information such as addressing mode in the decoder code 13; 16 is a microparameter register that stores parameter information such as addressing mode; Indicates microparameters that are parameter information.

FIG. 11 is a diagram showing an instruction format for explaining a method of selecting a starting entry of a microinstruction for each instruction in a conventional example.
8 is a 2-word instruction, 19 is an opcode that specifies the operation of the instruction, 20 is a dest field that specifies the address and access method of the dest data, 21 is a size field that specifies the size of the source data, and 22 is the address of the source data. A source field 23 designating an access method indicates an extension field designated by the source field 22.

FIG. 12 is a diagram showing the entry structure of a horizontal microinstruction. In the figure, 24 is a microinstruction, 25 is a microaddress field for specifying the microaddress 6a of the next microinstruction, and 26 is a microprogram field. Indicates a microsequence field that specifies a processing sequence.

Next, the operation of the conventional example will be explained using FIGS. 10, 11 and 12. First, a method of generating the decoder code 13 will be explained. Instructions fetched from an external storage device (not shown) are sent to an instruction decoder 12. The instruction decoder 12 specifies the type of instruction using the operation code 19 and generates a microaddress code corresponding to the start entry of the microinstruction 24. Parameter information is generated from the addressing mode and register number for accessing the source data and dest data specified in the dest field 20 and source field 22 and the size information of the source data specified in the size field 21 at the same time as the micro address code is generated. Generate code. The micro address code and the parameter information code are output from the instruction decoder 12 as a decoder code 13, and the micro address code is stored in the micro address register 14 and the parameter information code is stored in the micro parameter register 15. Unlike the 1-word instruction 17, when the 2-word instruction 18 has additional information such as offset information and immediate value data for the addressing mode that accesses the source data, this information is stored as the extension field 23 specified in the source field 22. Given. The size of the extension field 23 (here, 1 word) and the presence or absence of the extension field 23 are also given to the decoder code 13 as a source field parameter information code, along with the addressing mode, register number, etc. Therefore, the start entry of microinstruction 24 specified by opcode 19 is not fixed in the format of the instruction. In other words, the start entry address of the microinstruction 24 is determined only by the opcode 19 and is unrelated to the contents of the source field 22 and the dest field 20, and if the opcode 19 indicates the same processing content, it is one word without the extension field 23. The micro address 6a is the same in the instruction 17 and the 2-word instruction 18 having the extension field 23.

Next, the read operation of the microinstruction 24 will be explained. When the decoder code 13 is input to the micro address register 14 and the micro parameter register 15, a read operation of the micro ROM 1 is started. First, the microaddress 6a is read from the microaddress register 14, the microparameter 16 is read from the microparameter register 15, and the microaddress 6a is read out from the micropointer 7.
6 is held in the micro decoder 4. Micro pointer 7 reads micro ROM1 according to micro address 6b.
is accessed and microinstruction 2 is accessed as microdata 2a.
4 to the micro data register 3.

The operation differs as follows depending on how the micro address 6a to be executed next, designated by the micro sequence field 26 of the micro instruction 24, is determined. First, when instruction processing is completed in one step of a microinstruction, microdata 2b is output from the microdata register 3 to the microdecoder 4. The micro decoder 4 decodes the previously held micro parameters 16 and micro data 2b to generate a control signal 5 for controlling an arithmetic unit and the like. At the same time that microdata 2b is output from microdata register 3 to microdecoder 4, the next decoder code 13 is set in microaddress register 14 and microparameter register 15. Since the microsequence field 26 of the microinstruction 24 indicates the end of the microinstruction 24,
The micro address 6a for processing the next instruction is transferred from the micro address register 14 to the micro pointer 7, and the micro parameter 16 is transferred from the micro parameter register 1.
5 to micro decoder 4 and micro ROM1
A new microinstruction 24 is read from.

Next, when the instruction decoded by the instruction decoder 12 is processed by a plurality of microinstructions 24, the microsequence field 26 indicates the end of the microinstruction 24 in parallel with the reading of the microinstruction 24 from the microROM 1. The micro address 6b of the micro pointer 7 is counted up by 1 by the micro counter 8 until the micro address 6b is indicated. Then, the next microinstruction 24 is read out using the counted up microaddress 6d.

Further, when the micro sequence field 26 of the micro instruction 24 indicates a branch of the micro instruction 24 and the micro instruction 24 branches, the micro data register 3 extracts the micro address field 25 of the micro data 2a as the micro next address 9 and stores the micro instruction 24 as the micro instruction 24. Output to next address register 10. On the other hand, the micro data 2b from which the micro address field 25 has been extracted is output from the micro data register 3 to the micro decoder 4. The microdecoder 4 generates the control signal 5 as described above. At this time, the micro pointer 7 reads the micro address 6a from the micro next address register 10 and reads the next micro instruction 24 until the micro sequence field 26 indicates that the micro instruction 24 is not branched or terminated.

Finally, if the microsequence field 26 of the microinstruction 24 indicates a subroutine branch of the microinstruction 24 and the microinstruction 24 makes a microsubroutine call, that is, if the instruction decoded by the instruction decoder 12 has a common instruction with another instruction, When processed by the micro instruction 24, the micro output register 3 extracts the micro address field 25 of the micro data 2a as the micro next address 9 of the subroutine jump destination and transfers it to the micro next address register 10. On the other hand, the micro data 2b from which the micro address field 25 has been extracted is transferred from the micro data register 3 to the micro decoder 4. The microdecoder 4 generates the control signal 5 as described above. At this time, in parallel, the micro address 6b of the micro pointer 7 is set to 1 by the micro counter 8.
is incremented and stored in the micro stack register 11 as the return destination micro address 6c of the micro subroutine, and the micro address 6a of the micro sub routine branch destination is read from the micro next address register 10 into the micro pointer 7, and the sub routine branches and processing begins. It will be done. When the micro sequence field 26 indicates the end of the micro subroutine branch, the micro pointer 7 sets the micro address 6a of the micro stack register 11 as the return destination address of the sub routine.
is read, and the next microinstruction 24 is read.

The timing of the above operation will be briefly explained using FIGS. 13, 14, 15, and 16. In FIG. 13, 27 indicates the processing flow of instruction I, 28 indicates the processing flow of instruction II, and in FIGS. 13 to 16, A, B, C, and D indicate operation cycles for reading microinstructions, and arrows indicate data Indicates the direction of movement (processing). Here, the same symbols as in FIG. 10 indicate the same functions. Basically A, B, C, D 4
Each cycle is a read cycle for one microinstruction.

First, a case will be described in which processing of an instruction decoded by the instruction decoder 12 is completed with one microinstruction in FIG. 13. In a cycle D (hereinafter abbreviated as cycle) immediately before reading from the micro ROM 1 starts, the decoder code 13 of the instruction I is sent from the instruction decoder 12.
is output and the micro address 6a is input to the micro address register 14. At A, the micro address 6a is read into the micro pointer 7, and at B, the micro address 6b from the micro pointer 7 is read into the micro ROM.
1 is accessed, microdata 2a is read into the microdata register 3 at C, microdata 2b is passed to the microdecoder 4 at D, where it is decoded together with the microparameter 16, and then controlled at A. Signal 5 is output. At this time, in D, the decoder code 13 of the instruction II is output from the instruction decoder 12, and is thereafter processed in the same manner as the instruction I.

Next, a case in which microinstructions do not branch when processing is performed using a plurality of microinstructions will be described with reference to FIG. At C, the micro address 6b of the micro pointer 7 is taken into the micro counter 8 and counted up by 1, and at D, the micro address 6c is input to the micro pointer 7.
passed to. Then, in the next B, the next microinstruction is accessed by the micropointer 7. In the same case, as shown in FIG. 15, the micro address 9 indicated by the address field 25 of the micro instruction extracted by the micro data register 3 at C is stored in the micro next address register 10 at D. Then, at the next A, the instruction is passed to the micropointer 7, and at the next B, the microinstruction at the branch destination is accessed by the micropointer 7. Similarly, when branching to a subroutine, as shown in FIG. 16, the micro address 6b of the micro pointer 7 is taken into the micro counter 8 at C and counted up by 1, and then passed to the micro stack register 11 at D. Then, at the next A after the subroutine branch ends, it is passed to the micropointer 7, and at the next B, the microinstruction at the branch destination is accessed by the micropointer 7.

[0014]

[Problems to be Solved by the Invention] In the conventional microprogram control circuit as described above, changing the execution procedure of a microinstruction can be handled by changing the programming of the microaddress field and microsequence field in the microinstruction. This can be easily handled by changing the data programmed into the micro ROM during the manufacturing process. However, in such a conventional microprogram control circuit, if it is desired to add a new instruction or expand or change the functions of an instruction, it is necessary to perform additional programming on the chip. and,
When developing products by changing the micro-instructions, there is a problem in that the circuit of the instruction decoder must be significantly changed in order to be able to decode the micro-address of the newly added micro-ROM, prolonging the development period.

The present invention has been made to solve the above-mentioned problems, and provides a microprogram control circuit that allows functions to be expanded or changed using microinstructions without modifying the instruction decoder section. The purpose is to

[0016]

[Means for Solving the Problems] A microprogram control circuit according to the first invention as set forth in claim 1 has a microinstruction storage means (micro ROM1) for storing microinstructions.
) and a microinstruction access means (micropointer 7) that accesses microinstructions using microaddresses.
, a mask address storage means (mask address register 32) for storing a mask address for masking a micro-instruction, a micro-address comparison means (micro-address comparison circuit 33) for comparing the mask address and the micro-address, A replacement microaddress storage means (replacement microaddress register 30) stores a replacement microaddress of a replacement microinstruction that is accessed in place of a designated microinstruction, and a microaddress and replacement microaddress are determined based on the comparison results of the microaddress comparing means. The function of the microinstruction specified by the microaddress set in the mask address is replaced by the microaddress selection means (microaddress selection circuit 35) which selects and gives the microinstruction access means a microaddress for accessing the microinstruction storage means. This is used to switch the function of the micro-address replacement micro-instruction.

The microprogram control circuit according to the second aspect of the present invention includes a microinstruction storage means (micro ROM 1) for storing microinstructions, and a microinstruction access means (micropointer) for accessing the microinstructions by microaddresses. 7), a micro data holding means (micro data register 3) that holds the micro data read from the micro instruction storage means, and a micro next address that holds the address of the next micro instruction to be read determined by the micro data. Holding means (micro next address register 10) and mask address storage means (mask address register 32) for storing a mask address for masking a micro instruction.
and microaddress comparing means (microaddress comparison circuit 33) that compares the mask address and the microaddress.
), replacement microaddress storage means (replacement microaddress register 30) that stores the replacement microaddress of the replacement microinstruction accessed in place of the microinstruction specified by the mask address, and microaddress comparison means (microaddress comparison circuit). 33), an instruction change means (NOP instruction generation circuit 36
) and microaddress selection means () which selects the replacement microaddress and the micronext address from the microdata holding means and provides the micronext address holding means with the micronext address for next accessing the microinstruction storage means.
The micro-address selection circuit 35) forcibly replaces the function of the micro-instruction specified by the micro-address set in the mask address with a no-operation instruction, and changes the operation of the next micro-instruction to the function of the replaced micro-instruction of the replaced micro-address. It is something that can be switched.

The microprogram control circuit according to the third aspect of the present invention includes a microinstruction storage means (micro ROM 1) for storing microinstructions, and a microinstruction access means (micropointer) for accessing the microinstructions by microaddresses. 7), micro data holding means (micro data register 3) that holds the micro data read out from the micro instruction storage means, and mask address storage means (mask address register 3) that stores the mask address for masking the micro instruction. 32), a microaddress comparing means (microaddress comparison circuit 33) that compares the mask address and the microaddress, and a replacement device that stores the replacement microaddress of the replacement microinstruction accessed in place of the microinstruction specified by the mask address. microaddress storage means (replacement microaddress register 30); instruction change means (NOP instruction generation circuit 36) for changing the output signal from the microdata holding means to a no-operation instruction based on the comparison result of the microaddress comparison means; A skip signal indicating that the means has forcibly generated a no-operation instruction in response to the comparison result, and microaddress selection means (microaddress selection circuit 35) that receives the skip signal and selects a replacement microaddress in the replacement microaddress storage means.
), the function of the microinstruction specified by the microaddress set in the mask address is forcibly replaced with a no-operation instruction, and the operation of the next microinstruction is switched to the function of the replacement microinstruction specified by the replacement microaddress. It is.

The microprogram control circuit according to the fourth aspect of the invention set forth in claim 4 uses the comparison result of the microaddress comparison means (microaddress comparison circuit 33) among the means of the second invention shown in claim 2. The instruction changing means (NOP instruction generation section 38) for changing the output signal from the micro data holding means (micro data register 3) into a no-operation instruction is programmed into the micro instruction storage means (micro ROM 1).

[0020] The microprogram control circuit according to the fifth invention set forth in claim 5 uses the comparison result of the microaddress comparison means (microaddress comparison circuit 33) among the means of the third invention shown in claim 3. The instruction changing means (NOP instruction generation section 38) for changing the output signal from the micro data holding means (micro data register 3) into a no-operation instruction is programmed into the micro instruction storage means (micro ROM 1).

[0021]

[Operation] According to the first invention, when a microaddress for accessing a microinstruction that performs the function of an instruction to be masked is sent to the microinstruction access means (micropointer 7), the microaddress comparison means (microaddress comparison The micro-address selection means (micro-address selection circuit 35) which receives the detection signal by the circuit 33) replaces the function of the micro-instruction to be masked with the replacement micro-instruction indicated by the replacement micro-address storage means (replacement micro-address register 30). Replace with function.

According to the second invention, the microaddress that accesses the microinstruction that performs the function of the instruction to be masked is the microinstruction access means (micropointer 7).
is detected by the microaddress comparison means (microaddress comparison circuit 33), and the instruction change means (NOP instruction generation circuit 36) that receives the detection signal replaces the microinstruction function with a no-operation instruction, The micro address selection means (micro address selection circuit 35) sets the micro address of the micro instruction to be replaced in the micro next address holding means (micro next address register 10), and the function of the micro instruction to be masked is set in the micro address storage means (replacement micro address register 10). The function of the replacement microinstruction indicated by the address register 30) is replaced.

According to the third invention, the microaddress that accesses the microinstruction that performs the function of the instruction to be masked is the microinstruction access means (micropointer 7).
is detected by the microaddress comparison means (microaddress comparison circuit 33), and the instruction change means (NOP instruction generation circuit 36) that receives the detection signal replaces the microinstruction function with a no-operation instruction, In response to the instruction change means replacing the function with a no-operation instruction, the micro-address selection means (micro-address selection circuit 35) replaces the function of the micro-instruction to be masked with the replacement micro-instruction indicated by the replacement micro-address storage means (replacement micro-address register 30). Replace with the function of

According to the fourth invention, the microaddress that accesses the microinstruction that performs the function of the instruction to be masked is the microinstruction access means (micropointer 7).
is detected by the micro-address comparison means (micro-address comparison circuit 33), and the micro-instruction storage means (micro-ROM 1) receives the detection signal.
replaces the data of the microinstruction read by the microaddress with microdata for executing the no-operation instruction. Then, the replacement micro-address is set in the micro-address holding means (micro-next address register 10) by the micro-address selection means (micro-address selection circuit 35), and the function of the micro-instruction to be masked is replaced with the function of the replacement micro-instruction indicated by the replacement micro-address. do.

According to the fifth invention, the microaddress that accesses the microinstruction that performs the function of the instruction to be masked is the microinstruction access means (micropointer 7).
is detected by the micro-address comparison means (micro-address comparison circuit 33), and the micro-instruction storage means (micro-ROM 1) receives the detection signal.
replaces the data of the microinstruction read by the microaddress with microdata for executing the no-operation instruction. In response to replacing the microinstruction storage means with microdata for executing a no-operation instruction, the microaddress selection means (microaddress selection circuit 35) selects the function of the microinstruction to be masked from the replacement microinstruction indicated by the replacement microaddress. Replace with function.

[0026]

[Example] Example 1. FIG. 1 is a block diagram showing the configuration of a microprogram control circuit according to an embodiment of the invention. In FIG. 1, 29 is a replacement microaddress which is a microaddress of a microinstruction to be executed in place of the microinstruction indicated by the microaddress 6a, and 30 is a replacement microaddress register as a replacement microaddress storage means for storing the replacement microaddress 29. ,
31 is a mask address which is the address of the microinstruction whose function is to be changed; 32 is a mask address register as a mask address storage means for storing the mask address 31; and 33 is the micro address 6a and the mask address 31.
A microaddress comparison circuit 34 serves as microaddress comparison means for comparing the microaddress comparison circuit 3.
3, 35 is a microaddress selection circuit as a microaddress selection means that selects the microaddress 6a and the replacement microaddress 29 based on the microaddress comparison result 34, and 6d is a microaddress selection circuit 6d that selects the microaddress selected by the microaddress selection circuit 35. show. Note that in FIG. 1, the same symbols as in FIG. 10 indicate the same or equivalent parts.

Next, the operation of the microprogram control circuit shown in FIG. 1 will be explained. When the decoder code 13 is input to the micro address register 14 and the micro parameter register 15, the micro RO
A read operation of M1 is started. First, the micro address 6a is sent from the micro address register 14,
Microparameters 16 are read from microparameter register 15. At this time, micro parameter 16
is held in the micro decoder 4, and the micro address 6
a is read into the microaddress selection circuit 35 and taken into the microaddress comparison circuit 33 at the same time. In the micro address comparison circuit 33, the micro address 6a
is compared with the mask address 31 which is the entry address of the microinstruction set in the mask address register 32 for which the function is to be switched. If the comparison results do not match, the comparison result 34 indicates a mismatch, and in response to this, the microaddress selection circuit 35 selects the microaddress 6a and passes it to the micropointer 7 as the microaddress 6d. The micro pointer 7 reads micro instructions from the micro ROM 1 as in the conventional example.

Next, when the comparison results match, the comparison result 34 indicates a match, and in response to this, the microaddress selection circuit 35 selects the replacement microaddress 29 and passes it to the micropointer 7 as the microaddress 6d. The micro pointer 7 reads the replacement microinstruction from the micro ROM 1 as in the conventional example.

Here, the operation differs depending on how to obtain the next micro address 6a specified by the micro sequence field 26 (FIG. 12) of the micro instruction 24, but the micro address 6d passed to the micro pointer 7 is the comparison result. 34, the operation is the same as that of the conventional example, with the only difference being which microaddress 6a or replacement microaddress 29 is selected by the microaddress selection circuit 35, so a description thereof will be omitted.

The input to the microaddress comparison circuit 33 is when the microinstruction 24 branches and the next microaddress 9 of the micronext address register 10 is selected as the next microaddress 6a, and when the microinstruction 24 executes a microsubroutine. When the micro address 6c of the micro stack register 11 is selected as the next micro address 6a, a comparison with the mask address 31 is similarly performed, and the processing shown in the conventional example is performed with the micro address based on the comparison result 34. . At this time, once the replacement microinstruction is selected, microaddress comparison is prohibited until the end of the replacement microinstruction is detected by the sequence field 26 (FIG. 12) (until the replacement microinstruction is completed), and the microinstruction is continuously selected. Control may be performed so that address 6a is selected.

The timing of the above operation will be explained using FIG. The basic timing is the same as that shown in the conventional example, and only the parts that are different from the conventional example will be briefly explained. At A, the micro address 6a and the mask address 31 are input to the micro address comparison circuit 33, the micro address 6a and the mask address 31 are compared, and the comparison result 3 is obtained.
4 is output. At B, the microaddress selection circuit 35 selects the microaddress 6a or the replacement address 29 based on the comparison result 34, and passes the microaddress 6d to the micropointer 7. The micro pointer 7 reads the contents of the micro ROM 1 indicated by the micro address 6b.

Example 2. FIG. 2 shows an embodiment of the invention of claim 2, in which numeral 36 denotes an NOP (No.
2c is the micro data passed from the NOP instruction generation circuit 36 to the micro decoder 4, 9a is the micro next address extracted by the micro data register 3, and 9b is the micro next address selected by the micro address selection circuit 35. Indicates an address. Note that in the drawings, the same symbols as in FIG. 1 indicate the same or equivalent parts.

The operation of the microprogram control circuit shown in FIG. 2 will be explained. When the decoder code 13 is input to the micro address register 14 and the micro parameter register 15, the reading operation of the micro ROM 1 is started as in the conventional example. First, if instruction processing is performed in one microinstruction step, microaddress 6
a is read from the micro address register 14 and the micro parameter 16 is read from the micro parameter register 15. At this time, the microparameter 16 is held in the microdecoder 4, and the microaddress 6a is read into the micropointer 7 and taken into the microaddress comparison circuit 33 at the same time. As in the conventional example, the micro pointer 7 reads micro instructions from the micro ROM 1, and micro data 2a is output. The microaddress comparison circuit 33 compares the microaddress 6a with the mask address 31 which is the entry address of the microinstruction set in the mask address register 32 for which the function is to be switched. If the results compared here do not match,
The comparison result 34 indicates a mismatch, and in response to this, the micro address selection circuit 35 selects the next micro address 9a by the selection signal 34, and selects the next micro address register 10.
Set micro next address 9b to . However, since the sequence field 26 of the microinstruction 24 indicates the end, the micronext address 9b set in the micronext address register 10 becomes invalid. At this time, the input to the next micro address register 10 is normally controlled to be prohibited, but the operation of the micro address selection circuit 35 may be controlled so as to constantly select the next micro address 9a regardless of the comparison result 34. good.

In response to the discrepancy in the comparison result 34, the NOP instruction generating circuit 36 outputs the micro data 2b as it is as micro data 2c to be input to the micro decoder 4. As a result, the control signal 5 is outputted so as to directly execute the command function decoded by the command decoder 12. Next, if the comparison results match, the comparison result 34 indicates a match, and in response to this, the microaddress selection circuit 35 selects the replacement microaddress 29 based on the comparison result 34, and stores it in the micronext address register 10 as the micronext address 9b. set. Further, upon receiving the match of the comparison result 34, the NOP instruction generation circuit 36 generates the micro data 2b.
Instead, micro data 2c indicating a NOP instruction (no operation instruction) is output to the micro decoder 4. As a result, control signal 5 skips the operation of the execution stage (NOP
execute the command). And, originally, the sequence field 26 of the microinstruction 24 (FIG. 26)
indicates the end, so the micro next address 9b set in the micro next address register 10 becomes invalid. The address 6a is read into the micro pointer 7 and the micro data 2a is read from the micro ROM 1. The microaddress 6a is again compared by the microaddress comparing circuit 33, but it does not match, and the comparison result 34 shows that it does not match. As a result, the micro address selection circuit 35
selects the next micro address 9a based on the comparison result 34 and sets the next micro address 9b in the next micro address register 10. In addition, the NOP instruction generation circuit 36
outputs the micro data 2b as it is as micro data 2c which is input to the micro decoder 4. As a result, the control signal 5 is output to execute the function of the replacement microinstruction designated by the replacement microaddress 29 instead of the instruction function decoded by the instruction decoder 12. Further, as described above, since the sequence field 26 (FIG. 12) of the microinstruction 24 indicates the end, the micronext address 9b set in the micronext address register 10 becomes invalid.

Next, when instruction processing is executed using a plurality of microinstructions, the operation differs depending on how the next microaddress 6a specified by the microsequence field 26 of the microinstruction 24 is obtained, as in the conventional example. If it matches, the NOP instruction generation circuit 36 first generates a NOP instruction to replace the function of the microinstruction, and the microaddress selection circuit 35 that receives the comparison result 34 passes the micronext address to the micronext address register 10. The operation is the same as that of the conventional example except for selecting either the next micro address 9a extracted by the data register 3 or the replacement micro address 29 set in the replacement micro address register 30 for the micro address 9b.

Further, the input of the micro address 6a to the micro address comparison circuit 33 is possible if the micro instruction branches and the next micro address 9b of the next micro address register 10 is selected as the next micro address 6a, or if the micro instruction branches to the next micro address 6a. When the subroutine is executed and the micro address 6c of the micro stack register 11 is selected as the next micro address 6a, a comparison is similarly made with the mask address 31, and the processing based on the comparison result 34 and the processing shown in the conventional example are performed. . At this time, once the replacement microinstruction is selected, comparison of microaddresses is prohibited until the end of the replacement microinstruction is detected by the sequence field 26 (until the replacement microinstruction is completed), and the micronext address 9a is continuously checked. It may be controlled so that it is selected.

The timing of the above operation will be briefly explained using FIG. The basic timing is the same as that shown in the conventional example, and only the parts that are different from the conventional example will be briefly explained. At A, the microaddress 6a is input to the microaddress comparison circuit 33 and the micropointer 7. At B, the mask address 31 and the micro address 6a are compared. Upon receiving the comparison result 34 in C, the NOP instruction generation circuit 36 outputs the micro data 2 to the micro decoder 4.
Determine c. On the other hand, the micro data register 3 cuts out the micro next address 9a at C, and the micro next address 9b is selected by the micro address selection circuit 35 at D and is stored in the micro next address register 10.

Example 3. FIG. 3 shows an embodiment of the invention according to claim 3, and in the same figure, numeral 37 indicates a skip signal indicating that the NOP instruction generation circuit 36 has generated a NOP instruction. In the figure, the same reference numerals as in FIGS. 1 and 2 indicate the same parts.

In the microprogram control circuit shown in FIG.
When input to the micro address register 14 and the micro parameter register 15, the micro R
A read operation of OM1 is started. First, when instruction processing is performed in one microinstruction step, the microaddress 6a is sent from the microaddress register 14, and the microparameter 16 is sent to the microparameter register 15.
is read from. At this time, the microparameter 16 is held in the microdecoder 4, and the microaddress 6a is read into the microaddress selection circuit 35. In the micro address selection circuit 35, the skip signal 37 from the NOP instruction generation circuit 36 indicates that it has not been generated (no NOP instruction has been generated), so the micro address 6a from the micro address register 14 is selected and the micro Address 6d is passed, and at the same time, microaddress 6d is taken into microaddress comparison circuit 33. The micro pointer 7 is a micro ROM as in the conventional example.
1, the microinstruction specified by the microaddress 6b is read out, and microdata 2a is output. At the same time as reading from the micro ROM 1, the micro address comparison circuit 33 converts the micro address 6d into the mask address 3, which is the entry address of the micro instruction to switch the function set in the mask address register 32.
Compare with 1. If the comparison result does not match, the comparison result 34 indicates a mismatch, and in response to this, the NOP instruction generation circuit 36 outputs the micro data 2b as it is as the micro data 2c to be input to the micro decoder 4. As a result, the control signal 5 is outputted so as to directly execute the command function decoded by the command decoder 12.

Next, if the comparison result is a match, the micro address comparison circuit 33 detects a match between the mask address 31 and the micro address 6d, and the comparison result 34 indicates a match.The micro address 6b that has already matched the mask address 31 The reading of the microinstruction specified by is being executed. Therefore, upon receiving the match of the comparison result 34, the NOP instruction generation circuit 36 forcibly changes the micro data 2b to micro data 2c indicating a NOP instruction to invalidate the read micro data 2b and sends the micro decoder 4 to the micro data 2c.
Output to. As a result, the control signal 5 is output to skip the operation of the execution stage (to execute the NOP instruction). Next, upon receiving a skip signal 37 from the NOP instruction generation circuit 36 indicating that the operation has been skipped by generating a NOP instruction, the microaddress selection circuit 35 replaces the microaddress 6d to be executed next with the microregister 3.
Assume that the replacement microaddress 29 is stored at 0. Then, the micropointer 7 reads out the replacement microinstruction designated by the replacement microaddress 29. At this time, the comparison result 34 by the microaddress comparator circuit 33 that received the skip signal 37 is a mismatch (although the comparison between the microaddress 6d and the mask address 31 also shows a mismatch, so it is not necessary to apply this signal). In response, the NOP instruction generation circuit 36 generates micro data 2.
Micro data 2c is sent directly from b to micro decoder 4.
Output as . As a result, control signal 5 is output to execute the function of the replacement microinstruction specified by replacement microaddress 29. At this time, the skip signal 37 again indicates that it has not been generated, and the next microaddress 6a is similarly processed.

Next, when instruction processing is executed using a plurality of microinstructions, the operation differs depending on how the next microaddress 6d specified in the microsequence field 26 of the microinstruction 24 is obtained, as in the conventional example. If it matches, a NOP instruction is first generated to replace the function of the microinstruction, and then the replacement microinstruction is executed.The operation is the same as that of the conventional example, so a description thereof will be omitted.

Further, the input of the micro address 6d to the micro address comparator circuit 33 occurs when the micro instruction branches and the micro next address 9 of the micro next address register 10 is selected as the next micro address 6d. When the subroutine is executed and the microaddress 6c of the microstack register 11 is selected as the next microaddress 6d, a comparison is similarly made with the mask address 31, and the processing shown in the conventional example is performed using the microaddress based on the comparison result 34. be exposed.

The timing of the above operation will be explained using FIG. The basic timing is the same as that shown in the conventional example, and only the parts that are different from the conventional example will be briefly explained. At A, the microaddress 6a passes through the microaddress selection circuit 35, and the microaddress 6d is input to the microaddress comparison circuit 33 and the micropointer 7. At B, the mask address 31 and the micro address 6d are compared. Upon receiving the comparison result 34 at C, the NOP instruction generating circuit 36 determines the micro data 2c to be output to the micro decoder 4, and outputs a skip signal 37 when a NOP instruction is generated. If the comparison result 34 matches, the replacement microaddress 29 is selected in the next A.

Example 4. FIG. 7 shows an embodiment of the invention according to claim 4, in which numeral 38 indicates a NOP instruction generation section programmed into the micro ROM 1. Note that the same reference numerals in the figure as in FIG. 2 indicate the same parts.

Next, the operation of this embodiment will be explained. The operation of this embodiment is basically the same as that of the second embodiment, and only the different points will be explained. First, comparison result 3 of the microaddress comparison circuit 33
4 is a match, the NOP instruction generation unit 38 of the micro ROM 1 is enabled and the micro data 2 indicating the function of the NOP instruction is generated instead of the micro data 2 a indicating the function of the micro instruction accessed by the micro address 6b.
a is output. Then, the micro data 2b is directly output from the micro data register 3 to the micro decoder 4. Here, the micro next address 9a cut out by the micro data register 3 is different from that in the second embodiment, but the micro address selection circuit 35 receiving the comparison result 34 selects the replacement micro address 9a as in the second embodiment.
Since I choose 9, there is no problem. Next, if the comparison result 34 does not match, the NOP instruction generating section 38 of the micro ROM 1 is disabled and the micro data 2a indicating the function of the micro instruction accessed by the micro address 6b is output. Then, the micro data 2b is directly output from the micro data register 3 to the micro decoder 4.

Example 5. FIG. 8 shows an embodiment of the invention according to claim 5, in which the same reference numerals as in FIGS. 3 and 7 indicate the same parts.

Next, the operation of this embodiment will be explained. The operation of this embodiment is basically the same as that of the third embodiment, and only the different points will be explained. First, comparison result 3 of the microaddress comparison circuit 33
4 is a match, the NOP instruction generation unit 38 of the micro ROM 1 is enabled and the micro data 2 indicating the function of the NOP instruction is generated instead of the micro data 2 a indicating the function of the micro instruction accessed by the micro address 6b.
a is output. Then, the micro data 2b is directly output from the micro data register 3 to the micro decoder 4. Here, the micro next address 9a extracted by the micro data register 3 is different from the third embodiment, but the next micro instruction to be executed is a skip signal indicating that the NOP instruction generation circuit 36 has generated the NOP instruction. 37, the microaddress selection circuit 35 selects the replacement microaddress 29 as the microaddress 6d as in the third embodiment, so there is no problem. Comparison result 3
4 do not match, the NOP instruction generating section 38 of the micro ROM 1 is disabled and the micro data 2a indicating the function of the micro instruction accessed by the micro address 6b is output. Then, the micro data 2b is directly output from the micro data register 3 to the micro decoder 4.

FIG. 9 is an example of a circuit for explaining the NOP instruction generation section shown in the fourth and fifth embodiments.
The type and micro data are for a micro ROM of 4 bits. In the figure, 39 is the first power supply (hereinafter referred to as Vc
c), 40 is the second power supply (hereinafter abbreviated as GND)
, 41 is in a cutoff state (hereinafter referred to as OF
42 is a programming gate for programming micro data, 43 is a clock signal, 44a and 44b are word lines selected corresponding to micro address 6b, and 45a to 45d are micro data 2a gates. A bit line 46 serving as an output indicates a precharge transistor that becomes conductive (hereinafter abbreviated as ON) in response to a clock signal. In this figure, the same reference numerals as in FIGS. 7 and 8 indicate the same or corresponding parts.

First, a case where the comparison result 34 indicates a match (in this example, if there is a match, the Vcc level is reached) will be explained. In cycle A, the precharge transistor 46 is turned on by the clock signal 43, and the bit line 45a is turned on.
~45d becomes the Vcc level. In the cycle B, the word line 44a or the word line 44b corresponding to the micro address 6b set in the micro pointer 7 becomes the Vcc level, and the precharge transistor 46 is turned off.
It becomes F. When the word line 44a is selected with the Vcc level set to 1 and the GND level set to 0, the word line 44a becomes Vcc level 1 and the GND level set to 0.
The bit line 45a and bit line 45c connected to the programming gate 42, which is turned ON by reaching the cc level, become the GND level. As a result, bit line 4
Bit lines 5a to 45d indicate 0, 1, 0, 1 in this order. Similarly, when word line 44b is selected, 0, 0, 1,
1 is shown. Here, since the comparison result 34 indicates a match, the gate 41 is turned off in the cycle C, and the bit line 4
Bit lines 5a to 45d indicate 1, 1, 1, 0 programmed in the NOP instruction generation unit 38, and the micro data 2a
1, 1, 1, 0 are output. If the comparison result 34 indicates a mismatch, the gate 41 is turned on and the programming gate programmed in the NOP instruction generation section 38 is turned off, so that the microdata 2a selected by the word line is output.

In the above explanation of the operation of each embodiment, detailed explanation of the operation control of the functional blocks shown in the embodiment has been omitted.

[0051]

According to the first aspect of the invention, when a microaddress for accessing a microinstruction that performs the function of an instruction to be masked is sent to the microinstruction access means, it is detected by the microaddress comparison means and the detection signal is The received micro-address selection means can replace the function of the micro-instruction to be masked with the function of the replacement micro-instruction indicated by the replacement micro-address storage means.

According to the second invention, when a microaddress for accessing a microinstruction that performs the function of an instruction to be masked is sent to the microinstruction access means,
The micro-address comparison means detects the micro-instruction, and the instruction changing means receives the detection signal and replaces the micro-instruction function with a no-operation instruction, and the micro-address selection means sets the micro-address of the micro-instruction to be replaced in the micro-next address holding means. It becomes possible to replace the function of the microinstruction to be masked with the function of the replacement microinstruction indicated by the replacement microaddress.

According to the third invention, when a microaddress for accessing a microinstruction that performs the function of an instruction to be masked is sent to the microinstruction access means,
Detected by the microaddress comparing means, the instruction changing means that receives the detection signal replaces the microinstruction function with a no-operation instruction, and after the instruction changing means replaces it with a no-operation instruction, the microaddress selection means wants to mask it. It becomes possible to replace the function of the microinstruction with the function of the replacement microinstruction indicated by the replacement microaddress.

According to the fourth invention, the layout of the instruction changing means is easier than in the second invention. And the second
Similar to the invention of 2.0, it is possible to replace the function of the microinstruction to be masked with the function of the replacement microinstruction indicated by the replacement microaddress.

According to the fifth invention, the layout of the instruction changing means is easier than in the third invention. And the third
Similar to the invention of 2.0, it is possible to replace the function of the microinstruction to be masked with the function of the replacement microinstruction indicated by the replacement microaddress.

As a result of the above, according to the present invention, it is possible to implement a configuration that allows functional expansion and modification using microinstructions without revising the instruction decoding section, making it easy to expand and add instruction functionality. . The timing is especially tough (
When high-speed operation is required (there is no time margin for microaddress comparison processing), the configurations according to the second and third inventions are more effective, and the configurations according to the fourth and fifth inventions are more effective in terms of layout. Therefore, according to the present invention, it is possible to reduce the development cost and shorten the development period of a product incorporating new functions using microinstructions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment (Example 1) of claim 1 of the present invention.

FIG. 2 is a block diagram showing an embodiment (Embodiment 2) of claim 2 of the present invention.

FIG. 3 is a block diagram showing an embodiment (Embodiment 3) of claim 3 of the present invention.

FIG. 4 is a diagram showing the operation timing of the first embodiment in FIG. 1;

FIG. 5 is a diagram showing the operation timing of the second embodiment of FIG. 2;

FIG. 6 is a diagram showing the operation timing of the third embodiment of FIG. 3;

FIG. 7 is a diagram showing an embodiment (Example 4) of claim 4 of the present invention.

FIG. 8 is a diagram showing an embodiment (Example 5) of claim 5 of the present invention.

FIG. 9 is a diagram illustrating a circuit example of a NOP instruction generating section as an instruction changing means according to claims 4 and 5 of the present invention.

FIG. 10 is a block diagram showing a configuration example of a conventional microprogram control circuit.

FIG. 11 is a diagram showing an example of an instruction format.

FIG. 12 is a diagram illustrating an example of an entry structure of a horizontal microinstruction.

13 is a diagram showing the operation timing of the conventional example shown in FIG. 7. FIG.

14 is a diagram showing the operation timing for determining a micro address in the conventional example of FIG. 7; FIG.

15 is a diagram showing the operation timing for determining a branch destination microaddress in the conventional example of FIG. 7; FIG.

16 is a diagram showing operation timing for determining a microaddress to which a subroutine returns in the conventional example of FIG. 7; FIG.

[Explanation of symbols]

1 Micro ROM (micro instruction storage means) 2a,
2b Micro data 3 Micro data register (micro data holding means) 4 Micro decoder 5 Control signals 6a to 6b Micro address 7 Micro pointer (micro instruction access means)
8 Micro counters 9a, 9b Micro next address 10 Micro next address register (micro next address holding means) 11 Micro stack register 12 Instruction decoder 13 Decoder code 14 Micro address register 15 Micro parameter register 16 Micro parameter 31 Mask address 32 Mask address register ( (mask address storage means) 29 Replacement microaddress 30 Replacement microaddress register (replacement microaddress storage means) 33 Microaddress comparison circuit (microaddress comparison means) 34 Comparison result 35 Microaddress selection circuit (microaddress selection means) 36 NOP instruction generation Circuit (instruction changing means) 37
skip signal

Claims (5)

[Claims] 1. A microprogram control circuit for a microprocessor that controls arithmetic processing using microinstructions, comprising: microinstruction storage means for storing microinstructions; microinstruction access means for accessing the microinstructions by microaddresses; A mask address storage means for storing a mask address for masking an instruction, a micro address comparison means for comparing the mask address and the micro address, and a replacement micro instruction to be accessed in place of the micro instruction specified by the mask address. Replacement microaddress storage means for storing a replacement microaddress, and a microcontroller for selecting the microaddress and the replacement microaddress based on the comparison result of the microaddress comparing means and causing the microinstruction access means to access the microinstruction storage means. A microprogram control circuit comprising microaddress selection means for giving an address, and switching the function of the microinstruction specified by the microaddress set in the mask address to the function of the replacement microinstruction specified by the replacement microaddress. . 2. A microprogram control circuit for a microprocessor that controls arithmetic processing using microinstructions, comprising: microinstruction storage means for storing microinstructions; microinstruction access means for accessing the microinstructions by microaddresses; microdata holding means for holding microdata read from the instruction storage means; micronext address holding means for holding a micronext address of a microinstruction to be read next determined by the microdata; and masking the microinstruction. a mask address storage means for storing a mask address for the micro-instruction; a micro-address comparison means for comparing the mask address and the micro-address; a replacement microaddress storing means for storing a replacement microaddress, an instruction changing means for changing an output signal from the microdata holding means to a no-operation instruction according to a comparison result of the microaddress comparing means, and a replacement microaddress storage means for changing the output signal from the microdata holding means to a no-operation instruction; The micro-address selection means selects the micro-next address and supplies the micro-next address to the micro-next-address holding means, and forcibly replaces the function of the micro-instruction designated by the micro-address set in the mask address with a no-operation instruction. ,
A microprogram control circuit characterized in that the operation of the next microinstruction is switched to the function of the replacement microinstruction designated by the replacement microinstruction. 3. A microprogram control circuit for a microprocessor that controls arithmetic processing using microinstructions, comprising: microinstruction storage means for storing microinstructions; microinstruction access means for accessing the microinstructions by microaddresses; microdata holding means for holding microdata read from the instruction storage means, mask address storage means for storing a mask address for masking the microinstruction, and microaddress comparison means for comparing the mask address and the microaddress. , a replacement microaddress storage means for storing a replacement microaddress of a replacement microinstruction accessed in place of the microinstruction specified by the mask address, and an output signal from the microdata holding means based on the comparison result of the microaddress comparison means. an instruction changing means for changing the instruction to a no-operation instruction; a skip signal indicating that the instruction changing means has forcibly generated a no-operation instruction in response to the comparison result; and the replacement microaddress storage means in response to the skip signal. The function of the microinstruction designated by the microaddress set in the mask address is forcibly replaced with a no-operation instruction, and the operation of the next microinstruction is changed to the replacement microinstruction by the replacement microaddress. A microprogram control circuit characterized by switching the function of a replacement microinstruction specified by an address. 4. In a microprogram control circuit of a microprocessor in which arithmetic processing is controlled by microinstructions, an instruction changing means changes an output signal from a microdata holding means to a no-operation instruction based on a comparison result of a microaddress comparing means. 3. A microprogram control circuit according to claim 2, wherein the microprogram control circuit programs the microinstruction storage means. 5. In a microprogram control circuit of a microprocessor in which arithmetic processing is controlled by microinstructions, an instruction changing means changes an output signal from a microdata holding means to a no-operation instruction based on a comparison result of a microaddress comparing means. 4. A microprogram control circuit according to claim 3, wherein the microprogram control circuit programs the microinstruction storage means.