JPH0520052A - Microgram controller - Google Patents

Abstract

PURPOSE:To add or alter a microinstruction processed as one code without altering the circuit of an instruction decoder by storing the microinstruction to be added or altered in a register and storing it in a microinstruction register at need. CONSTITUTION:The register 101 is the register where microinstructions of one record to be added or altered can be written. The microinstruction register 107 is a writable registere and outputs a microinstruction selection signal 104 to a selector 105 according to the indication of a CPU which is not shown in a figure. The selector 105 selects a microinstruction 2 read out of a microinstruction ROM 1 with a microaddress or a microinstrsuction 103 read out of the register 101 according to the microinstruction selection signal 104 and outputs it as an arithmetic control microinstruction 13 to a microinstruction register 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprogram control device for a microprocessor which controls arithmetic processing by microinstructions, and stores in advance microinstructions to be added or changed and, if necessary, stores the microinstructions. The present invention relates to a micro program controller having a function of selecting a micro instruction.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional micro program controller. In FIG. 3, 1 is a micro ROM (hereinafter, micro is abbreviated as μ), 2 is a 111-bit μ instruction read from the μROM 1, 3 is a μ instruction register that holds μ instruction 2, and 13 is a μ instruction 2. Among them, an operation control μ instruction for controlling an arithmetic unit (not shown), 4 is a μ decoder for decoding the operation control μ instruction 13, 5 is a control signal decoded by the μ decoder, and 6 is an entry storing the μ instruction 2. Μ address, 7 is μ address 6
, An incrementer for incrementing the μ address stored in the μ pointer 7 by one, and a μ next address for designating the next μ address in the μ instruction 2, 10
Is a μ-order address register that stores μ-order address 9, 1
1 is the return destination μ when executing a subroutine with the μ instruction
Μ stack register for storing addresses, 12 is μRO
A μ address bus for storing a μ address for accessing M1 in the μ pointer 7.

Next, the operation of the conventional μ program controller will be described. First, the μ instruction will be briefly described. One μ instruction is divided into a part for controlling the arithmetic unit and a part for controlling the reading of the next μ instruction. The part that controls the reading of the next μ instruction includes operations such as reading the μ instruction at the next μ address, jumping to the specified μ address, jumping to the subroutine, and returning from the subroutine. In addition, the part that controls the μ instruction calculator has operations such as transfer, addition, and subtraction.

The instruction code is fetched from an external memory (not shown) and decoded by an instruction decoder (not shown). The μ address for realizing the operation of the instruction code is generated by the decoding result of the instruction decoder. This μ address is output to the μ address bus 12 and stored in the μ pointer 7. Then, the μROM 1 is accessed by the μ address 6 stored in the μ pointer 7,
The μ instruction 2 corresponding to the μ address 6 is output from the μ ROM 1 and stored in the μ instruction register 3.

When executing the μ instruction of the next μ address,
That is, if the μ instruction does not branch, or if one instruction is processed by one μ instruction, the arithmetic unit of the μ instruction 2, that is, the operation control μ instruction 13 is transferred from the μ instruction register 3 to μ instruction.
It is input to the decoder 4 and decoded by the μ decoder 4,
A control signal 5 for controlling a computing unit or the like is generated. Then, the μ address 6 for processing the next instruction is input to the μ pointer 7 from the μ address bus 12, and a new μ instruction 2 is read from the μROM 1.

Next, when one instruction is processed by a plurality of μ instructions, the μ instruction 2 is read from the μROM 1 and held in the μ instruction register 3. At the same time, the μ incrementer 8 increments the μ address of the μ pointer 7 by +1. The μ address 6 incremented by +1 is stored again in the μ pointer 7. Then, the next μ instruction 2 is read by the incremented μ address 6.

Next, when the μ instruction 2 indicates a branch, the μ next address 9 of the μ instruction 2 held in the μ instruction register 3
Is input to the μ-order address register 10. At the same time, the arithmetic control μ instruction 13 is input from the μ instruction register 3 to the μ decoder 4. Then, the μ decoder 4 generates the control signal 5 in the same manner as above. The micro-order address is transferred from the μ-order address register 10 to the μ-pointer 7 through the μ-address bus 12. The next μ instruction is read by the μ address 6 stored in the μ pointer 7.

Next, if the μ instruction 2 indicates a subroutine branch, μ of the μ instructions held in the μ instruction register 3
The next address 9 is input to the μ-order address register 10. At the same time, the arithmetic control μ instruction 13 is input from the μ instruction register 3 to the μ decoder 4. Further, the μ address 6 of the μ pointer 7 is incremented by 1 in the μ incrementer 8 and stored in the μ stack register 11 as a return address of the μ subroutine. Then, the μ decoder 4 generates the control signal 5 as described above. The μ pointer 7 is connected to the μ next address register 1 through the μ address bus 12.
The micro next address is transferred from 0. The next μ instruction is read at the μ address 6 stored in the μ pointer 7.

When the μ instruction 2 indicates a return from the μ subroutine, the return address of the subroutine as the next μ address is stored in the μ pointer 7 from the μ stack register 11 through the μ address bus 12. And μ
At the μ address 6 stored in the pointer 7, the next μ instruction 2 is read.

[0010]

In the conventional μ program control device, the μ instruction is added, the function of the μ instruction is expanded,
When changing, it is necessary to add a new μ address which is the head of the routine of the μ instruction to be added. For this reason,
In order to be able to generate the μ address corresponding to the added μ instruction, it is necessary to drastically change the circuit of the instruction decoder, and there is a problem that the development period is extended.

The μ program control device of the present invention has been made in order to solve the above problems, and adds an instruction that can be processed by μ instruction for one code without requiring a circuit change of the instruction decoder. The purpose is to provide a micro program controller capable of expanding and changing the function of instructions.

[0012]

The μ program control device of the present invention comprises a microinstruction storing means (register 101) in which a second microinstruction for one record to be added and changed can be written, and a microinstruction by a microaddress. Selecting means (selector 105) for selecting the first microinstruction read from the read-only memory or the second microinstruction read from the microinstruction storing means and outputting the selected microinstruction to the microinstruction register; An output means M (microinstruction control register 107) for outputting a microinstruction selection signal 104 for instructing selection is provided.

[0013]

According to the present invention, the output means M controls the selection circuit so as to select the second microinstruction when the microinstruction is added or changed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing an embodiment of the μ program control device of the present invention. In FIG. 1, 1 is a μ (micro) ROM as a micro read only memory, 2 is a μ (micro) instruction, 3 is a μ (micro) instruction register, 4 is a μ (micro) decoder, 5 is a control signal, and 6 is μ (micro) address, 7 is μ (micro) pointer, 8 is incrementer, 9 is micro next address, 10 is μ (micro) next address register,
11 is a μ (micro) stack register, 13 is a calculation control μ (micro) instruction, 101 is a register as a second micro instruction storage unit, and 102 is a source bus (hereinafter,
S bus), 103 is a μ (micro) instruction, 104
Is a μ (micro) instruction selection signal, 105 is a selector as selection means, 106 is a general-purpose register, and 107 is a μ (micro) instruction selection control register as output means M.

Since 1 to 13 have the same functions as those of the conventional device, they are designated by the same reference numerals and the description of the configuration is omitted for simplicity. The register 101 is a register in which a μ instruction (111 bits) for one record to be added or changed can be written. The source bus 102 is a 32-bit source bus for writing to the register 101, and the μ instruction 103 is a μ instruction for one record read from the register 101. The μ instruction selection control signal 104 is a selection signal for selecting either the μ instruction 2 read from the μROM 1 or the μ instruction 103 read from the register 101. The selector 105 follows the μ instruction selection control signal 104
Μ instruction 2 read from μROM1 by micro address
Alternatively, the μ instruction 103 read from the register 101 is selected, and the operation control μ instruction 1 is stored in the micro instruction register 3.
Output as 3. The general-purpose register 106 is a general-purpose register (R0 to R15), the micro-instruction control register 107 is a writable register, and the μ instruction 2 or the μ instruction 103 is selected by the selector 105 according to an instruction from a CPU (not shown). Give instructions to do.

FIG. 2 is a diagram showing the μ instruction selection control register of FIG. 1 in detail. In FIG. 2, F is a μ instruction switching enable bit that sets whether or not the μ instruction is switched. The output of the μ instruction switching enable bit F is connected to the μ instruction selection signal 104. Only the μ instruction selection bit is shown in the μ instruction control register 107,
Bits B1 and B2 used for other functions may exist. Also, this bit may be embedded in another flag register or the like.

Next, the operation of this embodiment will be described. First, the registration operation to the register 101 will be described.
The register 101 has a 111-bit configuration (0 to 11 bits).
0 bit), and writable. Register 101
Writing to is performed by transferring 32-bit data four times through the S bus 102. That is, the first time is 0 bits to 31 bits, the second time is 32 bits to 63 bits, and 3 bits.
64th bit to 95th bit, 4th time 0th bit to 14th bit of S bus is 96th bit of register 101
Written to 110 bits.

The setting of the μ instruction selection control register 107 will be described.
The control register setting instruction sets the μ instruction switching enable bit of the μ instruction selection control register. Also,
The μ instruction is selected by selecting the μ instruction 103 when “1” is written in the μ instruction selection control register 107 and selecting “0” in the μ instruction selection control register 107. , Μ instruction 2 is selected.

Next, the transfer operation will be described. Here, it is assumed that the transfer operation from the register R0 to the register R1 (transfer between registers) can be processed by the μ instruction of one code. First, in the μ instruction selection control register 107,
If "0" is set and "0" is output from the μ instruction selection control signal, the transfer instruction from the register R0 to the register R1 is fetched from an external memory (not shown) and Decoded by the decoder. Then, the μ address for realizing the operation of the μ instruction is generated by the decoding result. This μ
The address is output to the μ address bus 12 and stored in the μ pointer 7. The μROM 1 is accessed by the μ address 6 stored in the μ pointer 7, and the μ instruction 2 (register R 0 to register R) corresponding to the μ address 6 is accessed.
1) is output from the μROM 1 and is selectively output from the selection circuit 105 according to the selection control signal 104.
It is stored in the instruction register 3. Then, the μ instruction 2 stored in the μ instruction register 3, that is, the operation microinstruction 13 is decoded by the μ decoder 4, and the decoded instruction causes 32 from the designated transfer source register R0.
The bit data is output to the 32-bit S bus 102 and transferred to the designated transfer destination register R1.

Next, the μ instruction selection control signal 104 is "1".
And the operation when the μ instruction 103 is selected will be described. It is assumed that the transfer instruction from the register R3 to the register R4 of the general-purpose register 106 is written in the register 101 in advance. A transfer instruction from the register R1 to the register R2, which is a μ instruction of one code, is fetched from an external memory (not shown) and is decoded by an instruction decoder (not shown) to obtain a μ instruction for realizing the operation of the μ instruction. An address is generated. This μ address is output to the μ address bus 12 and stored in the μ pointer 7. The μROM 1 is accessed by the μaddress 6 stored in the μ pointer 7, and the μ instruction 2 (register R1 to register R2) corresponding to the μaddress 6 is accessed.
To the selection circuit 1 is output from the μROM1.
It is input to 05. On the other hand, the changed 1-code μ instruction 103 (transfer instruction from the register R3 to the register R4) written in the register 101 is also input to the selection circuit 105. The μ instruction selection signal 104 indicates “1”, and accordingly the μ instruction 103 is selected by the selection circuit 105 and stored in the μ instruction register 3. Then, the μ decoder 4 decodes and executes the μ instruction 103 (transfer instruction from the register R3 to the register R4).

Next, the operation when the μ instruction selection signal 104 indicates “0” and the μ instruction 2 is selected will be described. The transfer instruction from the register R1 to the register R2, which is a μ instruction of one code, is shown in the figure. Not fetched from external memory,
It is decoded by an instruction decoder (not shown). A μ address for realizing the operation of the μ instruction is generated by the decoding result. This μ address is μ address bus 1
2 and is stored in the μ pointer 7. The μROM 1 is accessed by the μaddress 6 stored in the μ pointer 7, and the μ instruction 2 (transfer instruction from the register R1 to the register R2) corresponding to the μaddress 6 is output from the μROM 1 and input to the selection circuit 105. In addition, the changed μ instruction 10 of one code written in the register 101
3 (transfer instruction from register R3 to register R4)
It is input to the selection circuit 105. The μ instruction selection signal 104 indicates “0”, and accordingly, the μ instruction 2 is selected by the selection circuit 105 and stored in the μ instruction register 3. Then, the μ-decoder 4 decodes and executes μ-instruction 2 (transfer instruction from register R1 to register R2).

[0022]

According to the μ program control device of the present invention, the microinstruction storing means in which the second microinstruction for one record to be added and changed can be written, and the microinstruction read from the micro read only memory at the microaddress. 1
Selecting means for selecting the second microinstruction read from the microinstruction or the microinstruction storing means and outputting it to the microinstruction register; and means M for outputting a microinstruction selection signal for instructing the selecting means to make a selection. Since it is equipped with, 1 without changing the circuit of the instruction decoder
This has the effect of adding instructions that can be processed by μ instructions for the code and expanding or changing the functionality of the instructions.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a micro program control device of the present invention.

2 is a detailed diagram of a μ instruction selection control register of the apparatus of FIG. 1;

FIG. 3 is a circuit block diagram showing an example of a conventional technique.

[Explanation of symbols]

 1 micro (μ) ROM 2 micro (μ) instruction 3 micro (μ) instruction register 4 micro (μ) decoder 6 micro (μ) address 7 micro (μ) pointer 13 arithmetic control micro (μ) instruction 101 register 102 source bus 103 micro (μ) instruction 104 micro (μ) instruction selection signal 105 selector (selection circuit) 106 general-purpose register 107 micro (μ) instruction selection control register

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[Procedure amendment]

[Submission date] June 4, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

[0015] Incidentally, 1-13 to have the same functions as the conventional apparatus, and with the same reference numerals, and description of the configuration will be omitted. The register 101 has μ for one record to be added or changed.
This is a register in which instructions (111 bits) can be written.
The source bus 102 is a 32-bit source bus for writing to the register 101, and the μ instruction 103 is the register 10
It is a μ instruction for one record read from 1. The μ instruction selection control signal 104 is the μ instruction 2 read from the μROM 1 or the μ instruction 103 read from the register 101.
Is a selection signal for selecting either of the above. Selector 105
Selects the μ instruction 2 read from the μ ROM 1 or the μ instruction 103 read from the register 101 at the micro address according to the μ instruction selection control signal 104, and outputs it to the micro instruction register 3 as the operation control μ instruction 13. .. The general-purpose register 106 is a general-purpose register (R0 to R0).
R15), and the microinstruction control register 107 is
This is a writable register, and the μ instruction 2 or μ instruction 1 is sent to the selector 105 in accordance with an instruction from a CPU (not shown).
Give instructions to select 03.

Claims (1)

Claim: What is claimed is: 1. A micro program control device comprising: a micro read-only memory for storing a first micro instruction corresponding to a micro address; and a micro instruction register for holding the first micro instruction. , A micro-instruction storage means capable of writing a second micro-instruction for one record to be added and changed, and a first micro-instruction read from the micro-read only memory at a micro address or read from the micro instruction storage means It has a selection means for selecting the second microinstruction and outputting it to the microinstruction register, and a microinstruction selection signal output means M for instructing the selection means to make a selection. The output means M is a microinstruction. To add or change the above, select the second microinstruction above Microprogram control unit and controls the means.