JPS6158854B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device in an information processing device.

FIG. 1 is a circuit block diagram showing an example of a conventional microprogram-controlled information processing device.

In FIG. 1, reference numeral 1 is a microinstruction address register, 2 is a control memory that stores a series of microprograms, 3 is a decoder that decodes microinstructions, and 4 is an arithmetic control unit that performs various arithmetic processing and control. , 5 is an adder that adds the value "1" to the input value, and 6 is a switching circuit.

The microinstruction stored at the address specified by the output a of the microinstruction address register 1 is read out from the control memory 2 and sent to the decoder 3.
Various arithmetic operations within the arithmetic control section 4 are controlled by the control signals decoded by the arithmetic control section 4. In this arithmetic operation, data and the like are exchanged between the information processing device and the external device via the interface h.

Now, in this conventional device, in a microinstruction cycle, if the microinstruction to be executed does not specify a branch operation, the microinstruction to be executed in the immediately next cycle is usually placed at the address of the microinstruction in the current cycle. It is stored at the address added by 1". Therefore, it is necessary to use the value obtained by adding "1" to the output a of the microinstruction address register 1 by the adder 5 as the address for reading the microinstruction to be executed in the next cycle. That is, since it is not a branch specification, the branch establishment signal d given from the arithmetic control unit 4 becomes logic "0", and the output f of the adder 5 is selected as the output g of the switching circuit 6, and the "value of the current microinstruction address" is output. +1” will be stored in microinstruction address register 1 at the start of the next cycle.

In addition, if the microinstruction executed in a certain microinstruction cycle specifies a conditional branch operation, the address of the microinstruction to be executed in the immediately next cycle depends on whether a certain branch condition is met or not. will be different. If the branch condition is not satisfied, the branch established signal d is logic “0”
As a result, the operation is the same as that of the microinstruction without branch specification. If the branch condition is satisfied, the branch completion signal d becomes logic "1" and the branch destination address e given separately from the arithmetic control unit 4 is selected by the switching circuit 6 and is the address of the microinstruction to be executed in the next cycle. It is stored in the microinstruction address register 1 as a microinstruction address register.

As described above, in the conventional device, when a microinstruction specifying a conditional branch stored at address N in control memory 2 is executed, the microinstruction at an arbitrary branch address M is executed when the branch condition is met. , if not established, the microinstruction at address M+1 is executed in the next microinstruction cycle. Therefore, the microinstructions for conditional branching and the microinstructions to be executed in the next cycle when the condition is not satisfied must be stored in consecutive address locations of address N and address N+1 on the control memory 2.

For example, now microinstructions A, B, C and D
, microinstruction A performs a conditional branch operation, and if the branching condition is met, microinstruction B is executed, and if the branching condition is not met, microinstruction C is executed in the next cycle. If microinstruction A is at address N, microinstruction C is stored at address N+1. Microinstruction B
is stored at an arbitrary M address. At this time, there is a microinstruction D at address X, which also performs a conditional branch operation, and, like microinstruction A, is required to execute microinstruction B if the branching condition is met, and microinstruction C if the branching condition is not met. , microinstruction C must be stored at address X+1. This contradicts the address condition of microinstruction C with respect to microinstruction A. In order to resolve this contradiction, it is necessary to separately prepare a microinstruction C' having the same content as microinstruction C at address X+1. If microinstruction C itself is also a conditional branch instruction, then N+
Microinstruction with the same content as microinstruction E at address 2
Prepare E' at address X+2. As such, the number of physical steps of microinstructions increases due to limitations on conditional branch operations. In order to avoid such an increase in the number of steps, in order to commonly use the microinstruction at address N+1, it is necessary to unconditionally branch to microinstruction C at address N+1 instead of microinstruction C' at address X+1. In this case, microinstruction C'' exists only for the branch operation, and in reality it wastes one wasted microinstruction cycle. This results in waste and degrades the performance of the device.

Also, for example, when there is one isolated free address in control memory, it is impossible to insert a new conditional branch microinstruction there; I had to find a vacant address. This also becomes a cause of hindering the effective use of control memory.

In order to deal with the above-mentioned problems, for example, when the branch condition is not met, in some cases, the value stored in a separate register (hereinafter referred to as a constant register) is set to the output f of the adder 5.
Devices that select instead of this have also been considered. This allows branching in two directions regardless of the address where the conditional branch microinstruction is stored. However, in such a device, as long as the contents of the constant register are the same, the destination of the conditional branch microinstruction at any address when the storage condition is not satisfied must be the same step as indicated by the constant register. .

Separately, as a method to enable branching from the address of the conditional branch microinstruction itself to an arbitrary relative address when the storage condition is not met, the result of adding the contents of the microinstruction address register 1 and the constant register is In the end, a device for selection may also be considered.

For example, by setting the value "t" in the constant register,
N+t when the branch condition is not met in a conditional branch microinstruction with different addresses, N address and M address.
This makes it possible to branch to different steps such as addresses and addresses M+t.

However, according to this method, if you want to branch from multiple different addresses to one fixed address, you need to set a unique value in the constant register that corresponds to the address of each conditional branch microinstruction. It comes out.

Even in the above two methods that allow a conditional branch operation to branch to an address other than the address incremented by "+1" when the branch condition is not met, when the address is generated when the branch condition is not met, only a given constant or a constant is used. Since a simple addition value to the current microinstruction address is uniformly used, branching operations are restricted, causing waste in terms of the number of physical steps and execution time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram control device that can fully utilize the function of conditional branching operations while suppressing performance deterioration and increase in the number of physical steps due to microprogramming limitations.

In order to achieve the above object, a microprogram control device according to the present invention includes a microinstruction address register that stores address information of a microinstruction, a microinstruction storage means that stores a plurality of microinstructions, and a microinstruction controller specified by the address information. an arithmetic control unit that controls processing operations of various arithmetic operations using microinstructions of the microinstruction storage means read from addresses; a mode register that can store an arithmetic mode for address generation; and an auxiliary address for address generation. Using the auxiliary address register that can be stored, the contents of the microinstruction address register, and the auxiliary address register, select either the arithmetic circuit output or the branch destination address depending on whether the branch is established or not of the branch microinstruction and the arithmetic circuit that can perform various operations. and a switching circuit to switch the branch microinstruction to the arithmetic circuit when a predetermined condition is not instructed from the arithmetic control unit to the arithmetic circuit by the microinstruction on the condition that the branch condition is not satisfied when the branch microinstruction is executed. The content of the address register and a predetermined constant are added, and when a certain condition is instructed from the arithmetic control unit to the arithmetic circuit by the microinstruction, the content of the mode register stored in advance by the microinstruction. According to the calculation mode indicated by , the contents of the microinstruction address register and the contents of the auxiliary address register stored in advance by the microinstruction are subjected to calculation processing, and the calculation result is stored in the microinstruction address register as address information. , when the branch condition of the branch microinstruction is satisfied, the branch destination address is stored as address information in the microinstruction address register.

According to the above configuration, it is possible to significantly improve the waste of physical steps and the loss in execution time.
The objectives of the invention can be fully achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 shows an embodiment of the device according to the invention. This embodiment includes a microinstruction address register 1, a control memory 2 that stores a microprogram, and
(microinstruction storage means), microinstruction decoder 3, arithmetic control unit 1 that performs various arithmetic processing and control
2. “A+1” “A+” for two inputs A and B
Arithmetic circuit 11 capable of calculating "B" (addition), "A-B" (subtraction), "A∧B" (logical product), "A∨B" (logical sum), branch/non-branch address switching circuit 6 , a flip-flop 7 that can be set or reset by a microinstruction, an AND circuit 8, an auxiliary address register 9 that stores any value specified by the microinstruction, and a mode register 10 that specifies the operation mode of the arithmetic circuit 11. In this circuit configuration, the configurations of circuit sections using the same symbols as in FIG. 1 are the same as those of the conventional circuit.

The output a of the microinstruction address register 1 is supplied to the control memory 2 and the "A" input of the arithmetic circuit 11. Control memory 2 is specified by the address a.
The output b read from the decoder 3 is decoded and the output c is sent to the arithmetic control section 12. Reference numeral d is a branch established signal indicating whether the branch condition is met (logic "1") or not (logic "0"). ) selects the branch destination address e given from the arithmetic control unit 12, and when the condition is not satisfied, selects the output f of the arithmetic circuit 11 as the output g, and stores the value in the microinstruction address register 1. be done. Reference numeral h is an interface that connects the arithmetic control unit 12 and an external device. Reference symbols i and j are the set and reset signals of the flip-flop 7 produced by the microinstructions. Reference numeral k is a conditional branch designation signal, which is logic "1" if a conditional branch is designated, and logic "0" if a non-branch or unconditional branch is designated.

The AND result output m of the output l of the flip-flop 7 and the conditional branch designation signal k is output by the arithmetic circuit 11.
It is used as a mode switching signal to decide whether to change the calculation operation according to the output q of the mode register 10. Reference numeral n is an auxiliary address given via the arithmetic control unit 12 to be set in the auxiliary address register 9, and the output o of the auxiliary address register 9 is used as the "B" input of the arithmetic circuit 11. Reference symbol p is an input given from the arithmetic control unit 12 for setting in the mode register 10. When the mode switching signal m is logic “0”, the arithmetic circuit 11 outputs “A+1” and logic “1”.
If so, the value set in mode register 10 is 0,
According to 1, 2 and 3 “A+B”, “A-
The arithmetic operations of "B", "A∧B" and "A∨B" are performed, respectively.

By adopting such a configuration, in this embodiment, when the flip-flop 7 is in the reset state, the operation is exactly the same as that of a device having a conventional configuration. That is, since the flip-flop 7 is "off", the mode switching signal m becomes "0", the arithmetic circuit 11 always executes the operation "A+1", and the output f is "contents of the microinstruction address register 1 +1". is output. Therefore, when executing a conditional branch microinstruction, if the branch completion signal d is logic "1", the branch destination address e
However, if the branch establishment signal d is logic "0", the output f of the arithmetic circuit 11 (current microinstruction address +
1) are respectively stored in the microinstruction address register 1 and used as the microinstruction read address from the control memory 2 in the next microinstruction cycle.

However, when the flip-flop 7 is in the set state ("on"), a special operation is performed when a conditional branch microinstruction is executed. That is, if the branch taken signal d is logic "1", the branch destination address e is stored in the microinstruction address register 1 in the same way as when the flip-flop 7 is off.

However, if the conditional branch designation signal k is logic "1" and the branch established signal d is logic "0", the mode switching signal m becomes logic "1", and therefore the output f of the arithmetic circuit 11 contains the microinstruction address. The contents of register 1 and the contents of auxiliary address register 9 are operated (for example, added) according to mode register 10 to obtain a result, which is stored in microinstruction address register 1.

For example, if the value of the microinstruction address register 1 is N, the value of the auxiliary address register 9 is t, and the value of the mode register 10 is 0 (designated "A+B"), a branch to address "N+t" is eventually realized. Depending on the value t previously set in the auxiliary address register 9, along with the branch destination address e, branching can be made in any two directions.

By enabling special operations using flip-flop 7, auxiliary address register 9, and mode register 10 as described above, advantages not available with conventional configuration devices can be obtained.

Next, a detailed flow of a microprogram using the apparatus of the present invention will be explained with reference to FIGS. 3 to 6. In Figures 3 to 5, each square frame represents one microinstruction, and the symbols S ₁ , S ₂ , etc. on the right side of each frame indicate convenient step names of each microinstruction, and the necessary In this case, the storage address of each microinstruction on the control memory 2 is shown on the left side of each frame, for example, if it is address N, it is indicated as <N>. Among the operations of each microinstruction, those specific to the device of the present invention are shown within the box.
"1→F/F" and "0→F/F" mean setting and resetting flip-flop 7 in FIG. 2, respectively.

"t→AREG" means to store the value t in the auxiliary address register 9 in FIG. 2, and "u-MREG" means to store the value u in the mode register 10.

In the example of FIG. 3, the flip-flop 7 is set in steps S ₁ and S ₂ and reset in step S ₃ . Further, the mode register 10 is set to a value of 0 ("addition" mode) at step _S1 and a value of 1 ("subtraction" mode) at step _S2 . At step _S4 , the value t is stored in the auxiliary address register 9. The subsequent step _S5 is a conditional branch microinstruction that specifies the branch destination address W at address N.

If the branch condition is met at step _S5 , a branch to step _S9 at address W is made regardless of the contents of flip-flop 7, auxiliary address register 9, and mode register 10. However, if the branch condition is not satisfied, the flip-flop 7, auxiliary address register 9 and mode register 10
Accordingly, the step S ₆ at address N+t, N−t
Address step S ₇ or address N+1 step S ₈
It will diverge into.

That is, there are three types of sequences: S ₁ →S ₄ →S ₅ →S ₆ , S ₂ →S ₄ →S ₅ →S ₇ , and S ₃ →S ₄ →S ₅ →S ₈ . While setting the common value t in the auxiliary address register, the value 0 set in the mode register 10
By making the arithmetic operation of the arithmetic circuit 11 variable depending on the difference between (“addition” mode) or 1 (“subtraction” mode), the degree of freedom in branching increases compared to conventional devices, and micro It becomes easier to standardize instructions.

FIG. 4 shows “A∧” by the arithmetic circuit 11.
This is an example of a case where the operation of "B" (logical product) is used. In step _S1 , the flip-flop 7 is set, the binary value "111110" is stored in the auxiliary address register 9, and the value 2 is stored in the mode register 10.
(“logical AND” mode) is set.

Step _S2 is a conditional branch microinstruction at address N, and when the branch condition is met, the branch destination is step _S5 at address W. Now set N to an even value, for example N=011010
(binary), the microinstruction address of the next cycle when the branch condition is not satisfied in step _S2 is the AND result of the contents of microinstruction address register 1 and auxiliary address register 9, and is the same address as the original N. become. In other words, it means looping with its own steps. If N is an odd value, for example N=011011, the AND result will mean "011010", that is, address "N-1". If you use this, for example, you can continue waiting for another interrupt signal until a certain counter overflows, enter the processing step _S4 when the interrupt occurs, and execute another routine _S5 when there is no interrupt. It is useful in such cases. step
Preferably, the branch condition at _S2 is a counter overflow signal, and the flip-flop 7 is reset by an interrupt signal. If N is an even number, the process loops at step _S2 until an interrupt is accepted, and then the process exits to step _S4 . If the counter overflows before accepting the interrupt, the branch condition is met and the process exits to step _S5 . If N is an odd number, waiting can be performed by a two-step loop of addresses N-1 and N. This means that even if step _S1 has exactly the same settings, the unit of loop can be considered depending on the address of the step to be executed thereafter. Such a function makes it easy to reduce the number of times various conditions are judged and avoid unnecessary delays.

In the example shown in FIG.
The functions of "B" (logical product) and "A∨B" (logical sum) are used.For ease of understanding, we will assume a control memory as shown in FIG.

The control memory in Figure 6 has an area from address 000000 to address 111111 in binary representation, and this area is further expanded.
000000-001111, 010000-011111,
Let's consider four subareas: 100000 to 101111 addresses, 110000 to 111111 addresses, and .

In step _S1 , flip-flop 7 is set and auxiliary address register 9 has the value 110000 (binary),
The mode register 10 is set to the value 2 ("AND" mode). In step _S2 , the flip-flop 7 is set, the auxiliary address register 9 is set to the value 001111 (binary), and the mode register 10 is set to the value 3 ("OR" mode). In step _S3 , the flip-flop 7 is reset.

Step S ₄ is address N (N = 011001 in this example)
This is a conditional branch microinstruction whose branch destination is step _S8 at address W. If the branch condition is not satisfied at step S ₄ , the sequence is S ₁ → S ₄ →
There are three types: S ₅ , S ₂ →S ₄ →S ₆ and S ₃ →S ₄ →S ₇ .

Step _S4 is now included in address 011001, ie, within the subarea in FIG. Therefore, in the case of S ₁ -> S ₄ -> S ₅ , the address of step S ₅ becomes address "010000" as a result of the AND operation of "011001" and "110000". This is nothing but the starting address of the subarea. Similarly, the address of step _S6 is the address "011111" as a result of the OR operation of "011001" and "001111". This is the final address of the subarea. From this, if the flip-flop 7, auxiliary address register 9, and mode register 10 are set in the same way as steps _S1 and _S2 , the conditional branch microinstruction at any address in the subarea, not just step _S4, can be executed. It can be seen that during execution, it is possible to jump to address ``010000'' or ``011111'' if necessary. By using this, you can use specific addresses within a certain subarea (in this example, "010000" and "011111")
can be assigned as the entrance to the special case processing routine, and the operation of branching to this can be executed without affecting the performance of the general case, and the number of physical steps can also be saved.

In this embodiment, four types of operation modes, addition, subtraction, logical product, and logical sum, using the mode register 10 have been explained above, but if these modes are made more abundant, flexibility in microprogramming can be increased accordingly. can.

Also, the value set in the auxiliary address register 9 is
If the data of the results of various operations are reflected in the execution of a certain microinstruction, branching to a special processing routine only in the case of a certain data pattern can be efficiently performed.

In the above example, branching to an address completely unrelated to microinstruction address register 1 is not mentioned, but for example, if the value "000000" is set in auxiliary address register ₉ in step S1 of FIG.
It is also possible to cause the instruction to skip to the "0" address in all cases, regardless of the value N of the microinstruction address register 1. Furthermore, in general, if the arithmetic circuit 11 is provided with a mode called "0+B", it is even possible to specify the branch destination when the branch condition is not met completely only by the auxiliary address register 9.

As explained in detail above, according to the present invention, the degree of freedom in branching operations is increased, so it is possible to suppress an increase in microprogram capacity and waste in execution time.
It becomes possible to improve the performance of the information processing device.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an example of a conventional device.
FIG. 2 is a circuit block diagram showing one embodiment of the present invention, FIGS. 3, 4, and 5 are flowcharts for explaining the operation of the present invention, and FIG. 6 is an auxiliary flowchart of FIG. 5. It is a figure showing control memory for explanation. 1... Microinstruction address register, 2...
Control memory (microinstruction storage means), 3... decoder, 4, 12... arithmetic control section, 5... adder,
6...Switching circuit, 7...Flip-flop, 8...
...AND circuit, 9...Auxiliary address register, 1
0...Mode register, 11...Arithmetic circuit.

Claims (1)

[Claims] 1. A micro-instruction address register that stores address information of micro-instructions, a micro-instruction storage means that stores a plurality of micro-instructions, and various micro-instructions stored in the micro-instruction storage means that are read from addresses specified by the address information. an arithmetic control unit that controls arithmetic processing operations; a mode register that can store an arithmetic mode for address generation; and an auxiliary address register that can store an auxiliary address for address generation;
It includes an arithmetic circuit that can perform various calculations using the contents of the microinstruction address register and the auxiliary address register, and a switching circuit that selects either the arithmetic circuit output or the branch destination address depending on whether the branch of the branch microinstruction is established or not. When executing the branch micro-instruction, if a certain condition is not specified by the micro-instruction to the arithmetic circuit from the arithmetic control unit under the condition that the branch condition is not satisfied, the predetermined contents of the micro-instruction address register are determined. When a certain condition is instructed from the arithmetic control unit to the arithmetic circuit by the microinstruction, the calculation mode is added according to the arithmetic mode indicated by the contents of the mode register stored in advance by the microinstruction. Arithmetic processing is performed on the contents of the microinstruction address register and the contents of the auxiliary address register previously stored by the microinstruction, and the result of the calculation is stored as address information in the microinstruction address register, and the branching of the branch microinstruction is performed. A microprogram control device characterized in that, when a condition is met, the branch destination address is stored as address information in the microinstruction address register.