JPH04251331A - Information processor - Google Patents

Abstract

PURPOSE:To make the overall information processing time of the title processor shorter than before by using a clock having such a long period that can execute a microinstruction which can only be executed by a clock signal having a long period to such microinstruction and another clock having a short period to the other microinstructions. CONSTITUTION:Addresses in a control storing means 3 in which plural specific microinstructions are stored are stored in advance in a microinstruction address comparison circuit 8. When it is discriminated that one of the addresses stored in the circuit 8 coincides with an address designating signal 104 outputted from a microinstruction address holding means as a result of comparison, a clock period switching designating means 9 designates the clock signal corresponding to the coincident microinstruction. A clock period switching means 12 selects the clock having the corresponding period from clock generating means 10 and 11 and uses the clock for each means constituting a logic circuit 1 as a clock signal 109.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that operates under the control of microinstructions.

0002

2. Description of the Related Art Conventional information processing devices of this type operate using a clock signal of a single cycle, and do not have a function of switching to a clock signal of a different cycle depending on the execution address of an arbitrary microinstruction. Ta.

0003

[Problems to be Solved by the Invention] Since the above-mentioned conventional information processing device operates with a single-cycle clock signal, the processing operations executed by the hardware section and the processing operations executed by the microprogram section are different. In devices that include Since it is not possible to use a short-cycle clock signal that can be used to operate the system, there is a drawback that the information processing speed cannot be increased.

Furthermore, in a device that performs preset processing using only a group of microinstructions, the execution time for executing most of the microinstructions is short, but if the execution time for some of the microinstructions is long, must use a clock signal with a cycle that allows the microinstruction with the longest execution time to be executed. Therefore, when executing the microinstruction group mentioned above, the overall cycle of the clock signal can be shortened. There was a drawback that the processing time for information could not be shortened.

An object of the present invention is to use a clock signal with a short period when executing an instruction that can be executed at a high speed, and to use a clock signal having a short period when executing an instruction that must be executed at a slow speed. An object of the present invention is to provide an information processing device that can select and use a clock signal with a long cycle that can execute such instructions.

[0006]

Means for Solving the Problems The information processing apparatus of the present invention is characterized in that the control storage means follows an address signal from the microinstruction holding means which holds the addresses of the microinstructions stored in the control storage means in the order of their execution. an information processing device that processes preset information by extracting a microinstruction stored at an address specified by the address signal from the memory and using a microinstruction execution means to execute a process corresponding to the extracted microinstruction; A plurality of predetermined micro-instruction addresses are stored, and the stored micro-instruction address signal is compared with the address signal output from the micro-instruction address holding means, and when they match, the matched micro-instruction address signal is microinstruction address comparison means for outputting a match signal according to the instruction address; clock cycle switching instructing means for outputting a selection signal specifying a clock signal having a cycle corresponding to the match signal from the microinstruction address comparison means; Clock generation means for generating clock signals having different periods corresponding to the selection signal; and selecting and outputting a clock signal having a period specified by the selection signal specifying the clock signal from the clock generation means. and clock cycle switching instruction means.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

The logic circuit unit 1 includes a control storage means 3 which stores a plurality of microinstructions, and a microinstruction address holding means which holds the addresses of the microinstructions stored in the control storage means 3 in the order of execution. 7, a microinstruction holding means 4 for temporarily holding the microinstruction 100 outputted from the control storage means 3 in response to the address signal 103 outputted from the microinstruction address holding means 7;
A micro-instruction decoding means 5 decodes the micro-instruction 101 held by the micro-instruction holding means 4 and converts it into an instruction 102 that can be operated by a micro-instruction execution means (to be described later), and information corresponding to the decoded instruction 102. micro-instruction execution means 6 for processing, and an address in the aforementioned control storage means 3 where a plurality of predetermined micro-instructions among the micro-instructions stored in the aforementioned control storage means 3 are stored. The address signal 104 output from the microinstruction address holding means 7 described above is compared with the address of the previously stored microinstruction described above, and when the two match, a match signal ( In Figure 1, 110 and 1
The microinstruction address comparison means 8 outputs two signals 11 (2 signals 11), and the clock switching instruction means 9 designates a clock signal having a period corresponding to these coincidence signals 110 and 111. Each of these components receives a clock signal 109 output from the clock circuit section 2, which will be described later.
Synchronous control is performed by

The clock circuit section 2 includes a first clock signal 122 and a clock signal 123 having different periods.
The clock generating means 10 and the second clock generating means 11 select one of the above-mentioned clock signals 122 and 123 according to the designation of the above-mentioned clock cycle switching instructing means 9 and output it as the clock signal 109. The clock cycle switching means 12 is comprised of a clock cycle switching means 12.

Now, it is assumed that the period of the clock signal 122 is shorter than the period of the clock signal 123, and the control storage means 3
Executing a specific microinstruction stored in the microinstruction requires a longer execution time than executing other microinstructions, and can be executed when synchronously controlled by the clock signal 123 described above. When executed, it is assumed that it can be executed even if it is synchronously controlled by the clock signal 122 described above.

In such a case, the address at which the above-mentioned specific microinstruction is stored in the above-mentioned control storage means 3 is stored in the microinstruction address comparison means 8, and the above-mentioned specific When a micro-instruction is executed and a micro-instruction different from this specific micro-instruction is executed, the above-mentioned control storage means 3 stores information about the micro-instruction to be executed immediately after the specific micro-instruction is executed. The addresses stored in the microinstruction address comparison means 8 are also stored in advance.

In this way, the microinstruction address comparing means 8 selects the clock signal 122 that enables the execution of the specific microinstruction described above just before the specific microinstruction is executed, and performs synchronous control using this clock signal. The above-mentioned clock signal 123 is used to execute a specific microinstruction in the previous stage, and when executing other microinstructions, the clock signal 123 is
can be used to execute microinstructions.

FIG. 2 is a block diagram showing an embodiment of the microinstruction address comparison means 8, clock cycle switching instruction means 9, and clock circuit section 2 shown in FIG. 3 is a timing chart illustrating the operation of each shown portion.

As the clock signal 109 shown in FIGS. 1 and 2, it is assumed that the output signal 122 supplied from the first clock generating means 10 is selectively output.

Among the microinstructions stored in the control storage means 3 described in FIG. An address value A in the control storage means 3 is stored in advance, and this address value A is used as an output signal 10.
7 and a first address register 13 which outputs as 7, and the aforementioned control storage means 3 which stores this microinstruction for other microinstructions following the aforementioned specific microinstruction.
The address value B within is stored in advance, and this address value B
The second address register 14 outputs the output signal 108 as the output signal 108, and the output signal 107 is compared with the address signal 104 output from the microinstruction address holding means 7, and when they match, a first match signal 111 is output. A first comparator 15 that outputs the value "1" and a second comparator that compares the output signal 108 and the address signal 104 described above and outputs "1" as a second match signal 110 when the two match. Address signal 10 input to microinstruction address comparison means 8 consisting of
When the value of 4 matches the address value A, the first match signal 111 having the value "1" is output from the first comparator 15, and the OR gate 17 in the clock cycle switching instruction means 9 and the second flip-flop 22 is applied to the set input terminal S of .

The output of the OR gate 17 becomes "1", and this output is applied to the set input terminal of the first flip-flop 21 in the clock cycle switching instruction means 9.

These first and second flip-flops 21
and 22 are RS flip-flops that are synchronously controlled by a first clock signal 124. Selector 2 of
5 is selectively connected and output.

A Q signal output 112 having a value of "1" is output from the Q output terminal of the first flip-flop 21, and the second
It is added to the input side of the third flip-flop 23 in the clock circuit section 2 of. In addition, the first flip-flop 2
From the output of the negative value of Q of 1, a signal 11 with the value “0” is generated.
3 is output and added to the input of the third AND gate 20 in the clock circuit section 2. Due to the input of this signal 113, the output of the clock signal 109 that has been output from the AND gate 20 is interrupted.

The third flip-flop 23 is synchronously controlled by a second clock signal 125 connected to the output signal 123 of the second clock generating means 11 by a second selector 26 in the clock circuit section 2. It is a D flip-flop.

When the third flip-flop 23 receives the Q signal 112 having the value "1" as described above, it outputs a reset signal 118 which is a Q signal having the value "1", and also outputs an output signal which is the negative value of Q. 119 and the value “0” as the third
In addition to the input of the AND gate 20, the output of the clock signal 109 is also interrupted.

Since this reset signal 118 is applied to the reset terminal R of the first flip-flop 21, the first
The value of the Q signal output 112 of the flip-flop 21 is “0”.
”, and the value of the output signal 113 of the negative value of Q is “1”.
becomes. Therefore, since the value of the output signal 119 of the negative value of Q of the third flip-flop 23 becomes "1", when the first clock signal 124 is added, the third AND gate 2
From 0, the clock signal 109 can be output.

As already explained, the first coincidence signal 1
11 is input to the set terminal S of the second flip-flop 22, a signal 114 having a value of "1" is output from the Q output of the second flip-flop 22. The Q output signal 114 of the second flip-flop 22 is input to the first AND gate 18 in the clock cycle switching instruction means 9 together with the output signal 113 of the negative value of Q of the first flip-flop 21. Ru.

As described above, the output signal 1 of the negative value of Q of the first flip-flop 21 is output by the reset signal 118.
When the value of 13 becomes "1", the value of the Q output signal 114 is already "1", so the first selection signal 116 having the value "1" is output from the first AND gate and the clock circuit section It is applied to the set terminal S of the fourth flip-flop 24 in the second flip-flop 2. The fourth flip-flop 24 is an RS flip-flop controlled by the second clock signal 125.

When the first selection signal 116 is input, the fourth flip-flop 24 outputs the value "1" as the Q output signal.
It outputs a signal 120 having .

The first selector 25 is controlled by this signal 120, and when this signal 120 has the value "1", it selects the output signal 123 of the second clock generating means 11 and outputs it as the first clock signal 124. , also signal 1
When the value of 20 is “0”, the first clock generating means 1
The output signal 122 of 0 is output as the first clock signal 124.

The value of the signal 121, which is the output of the negative value of Q of the fourth flip-flop 24, is "0" in the above case. The second selector 26 is controlled by the signal 121,
When the value of the signal 121 is "0", the output signal 122 of the first clock generating means 10 is selectively connected and output as the second clock signal 125, and when the value of the signal 121 is "1"
Sometimes, the output signal 12 of the second clock generating means 11
3 is selectively output as the second clock signal 125, so in the above case, the second selector 26 selectively outputs the signal 122 as the second clock signal 125.

The above-mentioned first flip-flop 21 is connected to the input side of the third AND gate 20 in the clock circuit section 2.
Output 113 of the negative value of Q of and the third flip-flop 2
Output 119 of the negative value of Q of 3 and the first clock signal 12
4 is connected, in the above state, the output signal 123 from the second clock generating means 11 is selected as the clock signal and output as the output signal 109 of the third AND gate.

Next, in the above-mentioned state, the address designation signal 104 from the microinstruction address holding means 7 becomes the clock signal 1 generated by the second clock generation means 11.
09 and outputs a signal that matches the address value B of the microinstruction held in the second register 14, the second
A coincidence signal 110 is output and applied to the OR gate 17 and the reset terminal R of the second flip-flop 22.

The value "1" is output from the OR gate 17, and the Q output signal 112 of the first flip-flop 21 becomes "1".
”, and the output 113 of the negative value of Q becomes “0”, so the output of the clock signal 109 from the third AND gate 20 is interrupted. During this time, the value “1” is output from the Q output terminal of the third flip-flop 23. ” is output and applied to the reset terminal R of the first flip-flop 21 to put the first flip-flop 21 in the reset state, so that the Q output signal 112 of the first flip-flop
When the value of becomes "0", the output signal 113 of the negative value of Q
The value of becomes "1". However, these operations are synchronously controlled by the first clock signal 124, which is the signal 123 selectively connected by the first selector 25.

As a result, the value of the Q negative value output 119 of the third flip-flop 23 also becomes "1", and if the first clock signal 124 is input to the third AND gate again, it can be output as the clock signal 109. state. Here, the second selector 26 selects and uses the signal 122 as the second clock signal 125 that performs synchronous control of the third flip-flop 23.

On the other hand, the second
The coincidence signal 110 of the second flip-flop 22
is reset, so it is in the clock cycle switching instruction means 9, and receives the output signal 113 of the negative value of Q of the first flip-flop 21 and the signal 115 of the negative value of Q of the second flip-flop 22. A second selection signal 117 having a value of “1” is output from the second AND gate 19,
It is applied to the reset terminal R of the fourth flip-flop 24.

The fourth flip-flop 24 receives the signal 117
Since it is reset by
becomes. Therefore, the signal 12 is selected by the first selector 25.
2 is selected and output as the first clock signal 124, and the signal 123 is selected by the second selector 26 and output as the second clock signal 125. The signal 122 outputted by the first clock generating means 10 is the clock signal 109
It will be output as

[0034]

As described above, in the information processing apparatus of the present invention, when a microinstruction with a long processing time is to be executed in advance, the microinstruction is executed using a clock signal with a long cycle that allows the microinstruction to be executed. Also, when transitioning from a specific microinstruction with a long execution time to a subsequent microinstruction with a short execution time, a clock signal with a short cycle that allows this microinstruction to execute is selected and information processing is performed using this selected clock signal. Therefore, compared to conventional information processing devices of this type, the present invention has the effect of being able to efficiently process information in a shorter time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing device of the present invention.

FIG. 2 is a block diagram showing an example of a microinstruction address comparison means, a clock cycle switching support means, and a clock circuit section in FIG. 1;

FIG. 3 is a flowchart for explaining the operation of FIG. 2;

[Explanation of symbols]

1 Logic circuit section 2 Clock circuit section 3 Control storage means 4 Microinstruction holding means 5 Microinstruction decoding means 6 Microinstruction execution means 7 Microinstruction address holding means 8 Microinstruction address comparison means 9 Clock cycle switching instruction means 10 First clock Generation means 11 Second clock generation means 12 Clock cycle switching means 13 First address register 14 Second address register 15 First comparator 16 Second comparator 17 OR gate 18 First AND gate 19 Second AND Gate 20 Third AND gate 21 First flip-flop 22 Second flip-flop 23 Third flip-flop 24 Fourth flip-flop 25 First selector 26 Second selector

Claims (2)

[Claims] 1. Addresses of microinstructions stored in the control storage means are stored in the address designated by the address signal from the control storage means in accordance with an address signal from the microinstruction holding means that holds the addresses in the order of execution. In an information processing apparatus that processes preset information by extracting a microinstruction from a microinstruction and executing a process corresponding to the extracted microinstruction using a microinstruction execution means, a plurality of predetermined microinstruction addresses are used. a microinstruction that stores a stored microinstruction address signal and compares the stored microinstruction address signal with an address signal output from the microinstruction address holding means, and when they match, outputs a matching signal corresponding to the matched microinstruction address. an address comparing means; a clock cycle switching instructing means for outputting a selection signal specifying a clock signal having a period corresponding to the matching signal from the microinstruction address comparing means; A clock generation means for generating a clock signal; and a clock cycle switching instruction means for selecting and outputting a clock signal having a cycle specified by a selection signal specifying the clock signal from the clock generation means. Information processing equipment. 2. First and second micro-instructions for storing and outputting, respectively, the address of a first micro-instruction and the address of a second micro-instruction that are predetermined among the micro-instructions stored in the control storage means. a register, a first comparator that compares the output of the microinstruction holding means and the output of the first register, and outputs a first match signal when these two outputs match; and an output of the microinstruction holding means; a second comparator that compares the output of the second register and outputs a second match signal when the two outputs match; and the first and second match signals. an OR gate that generates and outputs the logical sum of the OR gate, and a first Q output that is synchronously controlled by a first clock signal with the output of the OR gate as a set input and a reset signal as a reset input, and a negative value of the first Q output. A first RS flip-flop that outputs a Q output and a second Q output that is synchronously controlled by the first clock signal with the first coincidence signal as a set input and the second coincidence signal as a reset input. a second RS flip-flop that outputs a negative value of the Q output; and a first AND gate that generates a logical product of the negative value of the first Q output and the second Q output and outputs the logical product as a first selection signal. and a second AND gate that generates a logical product of the negative value of the first Q output and the negative value of the second Q output and outputs it as a second selection signal; first and second clock generating means that generate clock signals having different periods; and a second clock generating means that receives the first Q signal as input;
a third flip-flop that is synchronously controlled by a clock signal and outputs the set signal and the negative value of the set signal, the negative value of the set signal, the negative value of the first Q output, and the first clock signal; A third AND gate that generates a logical product of and outputs it as a clock signal, and a fourth AND gate that is synchronously controlled by the second clock signal, with the first selection signal as a set input and the second selection signal as a reset input. and a fourth RS flip-flop that outputs the negative value of the Q output and the fourth Q output, and is controlled by the fourth Q output, and when the fourth Q output is "1", the second clock is generated selecting the output from the means and the fourth Q
When the output is "0", the first selector selects the output from the first clock generating means and outputs the first clock signal, and the fourth Q output is controlled by the negative value of the fourth Q output. When the negative value of the Q output is "1", the output from the second clock generating means is selected, and when the negative value of the fourth Q output is "0", the output from the first clock generating means is selected. and a second selector for selecting and outputting the second clock signal, the output of the third AND gate being used as a clock signal for information processing operation. The information processing device according to claim 1.