JPH02224123A - Information processor - Google Patents

Abstract

PURPOSE:To make information processing efficient by executing adaptive type clock selection corresponding to execution time in each microinstruction, and excluding redundancy included in logical processing or physical processing. CONSTITUTION:A logical circuit part 2 including a part of a CPU and a clock circuit part 3 for selectively generating two kinds of operation clocks constitute a main part. At the time of executing logical processing or physical processing in accordance with a microinstruction whose processing contents can be variably defined, clock frequency selection commanding means 6, 7 decoding the microinstruction command the selection of specified clock frequency to a clock generating circuit 3 for selectively outputting plural operation clocks having respectively different frequency values while considering the execution time in each microinstruction, so that adaptive clock selection considering the execution time in each microinstruction can be executed and redundancy included in the logical processing or physical processing can be excluded. Consequently, highly efficient information processing can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that enables adaptive clock changes using microinstructions.

[Prior Art] A computer smaller than a minicomputer is sometimes called a microcomputer after the word micro, which means ultra-compact. Some Noranos have functions that exceed those of conventional minicomputers, so it may be difficult to define the category of microcomputer based on the size of the circuit.

In these small information processing devices, including minicomputers, the function equivalent to an instruction decoder is released to the user so that the user can assemble detailed operating instructions within the central processing unit to suit the application system. Some systems allow users to freely define microinstructions, and by devising microprograms created using microinstructions, users can expand the scope of their individual application systems.

[Problems to be Solved by the Invention] The conventional information processing device described above uses microinstructions issued by the central processing unit as F-type instructions related to data processing such as arithmetic operations, logical operations, or shift instructions.

Functionally, they can be roughly classified into three types, such as P-type instructions that control execution sequences such as branches and interrupt processing, and E-type instructions related to input/output control and external control, but from the perspective of instruction format. can be roughly divided into microinstructions related to logical processing on software and microinstructions related to physical processing on hardware. In general, in a program handled by an information processing device, logical processing and physical processing are sequentially executed alternately or singly, and the execution time differs for each process. However, in conventional information processing devices whose operating clocks were fixed to a single frequency, the clock frequency was set according to instructions that take longer to execute, either logical processing or physical processing. Even for the instructions that can be processed, there are many cases where it is unavoidable to execute them according to a long-cycle operating clock, and as a result of the latent redundancy throughout the processing process where multiple instructions are executed sequentially, efficient information processing is difficult. I was faced with such issues.

[Means for Solving the Problems] The present invention has solved the above problems, and is an information processing device that executes logical processing or physical processing according to microinstructions whose processing contents are variable in definition, and which has different frequencies. Clock generation means for selectively outputting a plurality of operating clocks; and a clock frequency selection means for decoding the microinstruction and instructing the clock generation means to select a clock frequency specified by taking into consideration the execution time for each instruction in advance. The present invention is characterized by comprising an instruction means.

[Operation] This invention provides microinstructions to clock generation means that selectively outputs a plurality of operating clocks with different frequencies when executing logical processing or physical processing in accordance with microinstructions whose processing contents are variable in definition. The decoded clock frequency selection instructing means selects and instructs the specified clock frequency taking into account the execution time for each instruction, thereby performing adaptive clock selection that takes into account the execution time for each microinstruction, and performs logic processing and Eliminate potential redundancy in physical processing as much as possible.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic configuration diagram showing an embodiment of an information processing device of the present invention, and FIGS. 2 and 3 are a circuit diagram specifically showing the main parts of FIG. 1 and signal waveform diagrams of each part of the circuit, respectively. be.

The main parts of the information processing device l shown in FIG. 1 include a logic circuit section 2 that includes a part of a central processing unit, and a clock circuit section 3 that serves as clock generation means that selectively generates two types of operating clocks. Configure. The logic circuit unit 2 includes a control storage circuit 4 that stores the correspondence between microinstructions and processing contents defined for each instruction, and sequentially stores microinstructions read from the control storage circuit 4 in the process of digesting the program. A clock cycle switching instruction circuit 7 is added to the components within the central processing unit, such as a microinstruction holding register 5 and a microinstruction decoding circuit 6 that decodes the microinstructions held in the microinstruction holding register 5.

The micro-instruction decoding circuit 6 and the clock cycle switching instructing circuit 7 constitute a clock frequency selection instructing means, which decodes the micro-instructions and generates a clock at a specified clock frequency by considering the execution time for each instruction in advance. A selection instruction is given to the clock circuit section 3 which is the means. The clock circuit section 3 receives instructions from an oscillator 8 that generates a reference oscillation pulse, a clock period conversion circuit 9 that divides the oscillation output of the oscillator 8 and generates two types of operating clocks, and a clock period switching instruction circuit 7. Accordingly, the clock cycle switching circuit IO selects one of the two types of operating clocks output by the clock cycle conversion circuit 9.

Hereinafter, the specific circuit configuration and operation of the clock cycle switching instruction circuit 7 and the clock cycle switching circuit IO will be explained with reference to FIG. 2.3.

First, it is assumed that in the initial state, the flip-flop circuits II and 12 in the clock cycle switching instruction circuit 7 are in a reset state. Further, the oscillation pulse supplied from the oscillator 8 in the clock circuit section 3 is frequency-divided in the clock period conversion circuit 9, and is divided into a short period (high frequency) and a long period (low frequency).
Two types of operating clocks are supplied to each of the pair of selector circuits 13 and 14 in the clock cycle switching circuit IO.

Since the outputs of the Nant gate circuits 15 and 16 that receive the Q outputs of the flip-flop circuits 11 and 12 are both high level, the outputs of the Nant gate circuit 17 and the AND gate circuit 18 in the clock cycle switching circuit 10 are both low level. The flip-flop circuit 19, which uses the output of the AND gate circuit 18 as a data input, is in a reset state.

Therefore, the low level Q of the flip-flop circuit 19
The selector circuit 13, which receives the output as a selection command, selects a long-period operating clock. Furthermore, since the AND gate circuit 20 which receives the outputs of the Nant gate circuits 15 and 16 as its gate input has its gate open, the selector circuit 1
The long-period operation clock outputted from the circuit 3 is supplied directly to the logic circuit section 2 through the AND gate circuit 20. In addition, another selector circuit 14 selects a short-cycle operation clock and selects a flip-flop circuit! 9 and the clock input terminals of the next stage 7 lip-flop circuit 21.

Here, the control storage circuit 4 in the logic circuit unit 2 gives a microinstruction to the microinstruction holding register 5 to change the clock period from a long period to a short period at time tl shown in FIG. do.

This instruction is decoded by the microinstruction decoding circuit 6 and stored in the first stage of the clock cycle switching instruction circuit 7.
Of the NAND gate circuits 22 and 23, one of the NAND gate circuits 22 is supplied as a low level decode output. AND gate circuit 2 after Nant gate circuit 22
4 has its gate open when it receives the Q output from the flip-flop circuit 21, so the output switches to high level when the decode output is supplied. Therefore, the flip-flop circuit 11 is set and its Q output is fed back to the set input terminal via the Nant gate circuit 22 and the AND gate circuit 24, thereby maintaining the set state.

Incidentally, the Q output of the flip-flop circuit 11 is inverted by the Nant's gate circuit 15 and sent to the N'and's gate circuit 17 and the AND gate circuit 20 in the clock cycle switching circuit 10 as a low level switching instruction signal. At this time, since the output of the Nant gate circuit 16 is at a high level, the flip-flop circuit 19 receives a high level output from the AND gate circuit 18 and is set, and gives a high level selection command to the selector circuit 13. As a result, the selector circuit 13 selects a short-cycle operating clock. However, since the AND gate circuit 20 has already closed its gate, the clock supply to the logic circuit section 2 is interrupted. Further, when the flip-flop circuit 21 set by the flip-flop circuit 19 gives a high-level selection command to the other selector circuit 14, the long-period operating clock is selected here, and this is applied to the seven flip-flop circuits 19. 21 clock input terminal.

On the other hand, due to the Q output of the flip-flop circuit 21 set together with the long-cycle clock input, the AND gate circuit 24 in the clock cycle switching instruction circuit 7 closes the gate, so the flip-flop circuit 11 is reset, and until then the low level The output of the Nant gate circuit 15, which had been outputting the switching instruction signal, becomes high level. As a result, the AND gate circuit 20 opens the gate, and only then the short-cycle operating clock selected by the selector circuit 13 is sent to the logic circuit unit 2 via the AND gate circuit 20, and the logic circuit The operating clock of section 2 is switched from long cycle (low frequency) to short cycle (high frequency).

Next, assume that the control storage circuit 4 in the logic circuit unit 2 gives an instruction to the microinstruction holding register 5 to change the operating clock from a short period to a long period at time t shown in FIG. This instruction is decoded by the microinstruction decoding circuit 6, and one input of the Nant gate circuit 23 is set to a low level. The AND gate circuit 24 receiving the output of the Nant gate circuit 23 is the flip 70 tube circuit 2 which is inverted by the inverter circuit 25 and set to a high level.
Since it receives the Q output of 1, it ends up being AND gate circuit 2.
The output of 4 is switched to high level, and the flip-flop circuit 12 is set. Flip-flop circuit! The Q output of No. 2 is inverted by the Nant gate circuit 16 and sent as a low-level switching instruction signal to the AND gate circuit 18.20 in the clock cycle switching circuit IO. The result is an AND gate circuit! The output of 8 is switched to low level, and the flip-flop circuit 19, which is reset in response to this, maintains the reset state by the Q output fed back via the Nant gate circuit 17 and the AND gate circuit 18. However, since the AND gate circuit 20 has already closed its gate, the clock supply to the logic circuit section 2 is interrupted.

By the way, the selector circuit 13 receives a low level selection command from the flip-flop circuit 19, and this time selects a long-period operating clock. Also, flip-flop circuits! The selector circuit 14 receives the selection command from the flip-flop circuit 21 reset by 9, selects a short-cycle operating clock, and sends it to the flip-flop circuit 19.
．． 21 clock input terminals.

On the other hand, the AND gate circuit 24 is inverted and supplied with the high-level Q output of the flip-flop circuit 21 via the inverter circuit 25 to close its gate, so that the flip-flop circuit 12 is reset.

As a result, the Q output of the flip-flop circuit 12, which is inverted and set to high level by the Nant gate circuit 16, opens the gate of the AND gate circuit 20, so that the long-period operating clock selected by the selector circuit 13 is activated. , and is sent to the logic circuit unit 2 via the AND gate circuit 20, and the operating clock is switched from short cycle (high frequency) to long cycle (low frequency).

In this way, the information processing device I has a clock circuit unit 3 that selectively outputs a plurality of operating clocks having different frequencies when executing logical processing or physical processing in accordance with microinstructions whose processing contents are variable in definition. On the other hand, since the microinstruction decoding circuit 6 and the clock period switching instruction circuit 7 are configured to select and instruct the specified clock period by taking into consideration the execution time for each instruction, an adaptive type that corresponds to the execution time for each microinstruction is provided. By selecting these clocks, redundancy latent in logical processing and physical processing can be eliminated as much as possible. As a result, for example, when logical processing and physical processing occur in succession, the clock period for microinstructions with a long execution time is lengthened using a low-frequency operation clock, while conversely, the execution time is By shortening the clock cycle using a high-frequency operation clock for short microinstructions, it is possible to eliminate redundancy in the execution of a given process. Furthermore, even when only logical processing or only physical processing is continuous, efficient logical processing and physical processing can be performed by selecting the clock period according to the execution time of each processing.

[Effects of the Invention] As explained above, the present invention selectively outputs multiple operating clocks with different frequencies when executing logical processing or physical processing according to microinstructions whose processing contents are variable in definition. The clock frequency selection instructing means that decodes the microinstruction selects and instructs the clock generation means to select the specified clock frequency, taking into consideration the execution time for each instruction, so that the clock frequency selection instructing means for the clock generation means that decodes the microinstruction selects and instructs the specified clock frequency, taking into account the execution time of each instruction. By performing adaptive clock selection, potential redundancy in logical and physical processing can be eliminated as much as possible. By increasing the clock cycle for microinstructions that take a long time, and conversely by shortening the clock cycle for microinstructions that take a short execution time, redundancy is created in the execution of a given process. In addition, even when only logical processing or only physical processing is continuous, by selecting the clock period according to the execution time of each processing,
It has excellent effects such as efficient logical processing and physical processing.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of an information processing device of the present invention, and FIGS. 2 and 3 are a circuit diagram and a signal waveform diagram of each part of the circuit, respectively, specifically showing the main parts of FIG. 1. be. 109. Information processing device, 2. ,,Logic circuit section. 380. Clock circuit section, 6. , , Microinstruction decoding circuit, 7. ,,Clock period switching instruction circuit.

Claims (1)

[Claims] An information processing device that executes logical processing or physical processing in accordance with microinstructions whose processing contents are variable in definition, the information processing device comprising: clock generation means for selectively outputting a plurality of operating clocks having different frequencies; An information processing device comprising clock frequency selection instructing means for instructing the clock generating means to select a clock frequency specified in advance by taking into account execution time for each instruction.