JPS61282946A - Programmable controller - Google Patents

Abstract

PURPOSE:To change easily a sequence program by providing plural user program memories allocated to the same address area and a chip selecting circuit which selects one of them in accordance with a program switching request. CONSTITUTION:When sequence change data 1 is inputted to a change data input circuit 2, the input circuit 2 latches change data 1, and the circuit 2 holes change data 1 until different change data is inputted. A CPU 3 reads in change data 1 to send it to a chip selecting circuit 4 and initializes an internal data memory 5. When receiving a memory selecting signal of a user program area from a memory selecting signal generating decoder 6, the chip selecting circuit 4 activates a chip selecting signal 11 of sequence program memories 8, 9, and 10 in accordance with change data 1. Thus, one of sequence program memories 8, 9, and 10 is selected, and the sequence program stored in the selected memory is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a programmable controller having a function of selecting a plurality of different sequence programs.

[Technical background of the invention and its problems]

When performing sequence control using a programmable controller (hereinafter referred to as PC), it may be desirable to change the sequence depending on the object to be controlled.

A block diagram of a conventional PC is shown in FIG.

In FIG. 4, the user program is stored in a sequence program memory 8 and executed by a CPU (arithmetic processing unit) 3 according to a procedure stored in a system memo 2.

The internal data memory 5 temporarily stores the execution results of the user program, and exchanges data with the input section 14 and the output section 15 via the I10 path interface 13.

The decoder 6 generates a memory selection signal 7 for each memory according to the address signal output from the CPU 3.

FIG. 5 shows an example of a memory map when a plurality of sequences are selectively switched and executed in a conventional PC having the configuration shown in FIG. 4.

That is, in the past, the user program area was, for example, three sequence program areas (A) and (B).

(C), and select and execute one sequence program while interlocking each other on the program.

However, in the above method, since the user program area is divided into a plurality of parts, there is a problem in that the capacity of each sequence program becomes small, and the user program itself becomes complicated due to switching between sequence programs.

Another method is to download the sequence program to be executed from the host computer and rewrite the user program area in the PC. In this case, there is no limit to the number of sequences that can be selected, and the memory capacity of the PC is also limited. Although it can be used effectively, the means of data transmission becomes complicated, and transmission errors due to the influence of noise cause PCs to
This poses a problem in terms of reliability as it may lead to runaway behavior.

[Purpose of the invention]

An object of the present invention is to provide a rational programmable controller that can easily change sequence programs while effectively utilizing memory capacity.

[Summary of the Invention] The present invention provides a plurality of user program memories allocated to the same address area on a memory, and a chip select that selects one of the plurality of user program memories in response to an external program switching request. This is a programmable controller equipped with a circuit that allows sequence programs to be easily switched without reducing the memory capacity of user programs.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG.

In FIG. 1, when sequence change data 1 is input to the change data input circuit 2, the input circuit 2 inputs the change data 1.
is latched and the changed data 1 is held until different changed data is input.

Subsequently, the CPU 3 reads the change data 1 at the timing shown in the transition diagram shown in FIG. 2, sends it to the chip select circuit 4, and initializes the internal data memory 5.

When the chip select circuit 4 receives the memory selection signal for the user program area from the memory selection signal generation decoder 6, it activates the chip select signal 11 of the sequence program memories 8, 9, and 10 in accordance with the change data 1.

This allows the sequence program memory 8°9.10
Only one of them is selected and the sequence program stored in that memory is executed.

Sequence program memories 8, 9 and 10 are separate ROs
Since it is mounted on the board as an M chip, the capacity of the user program area can be tripled as shown in FIG. 3 compared to the conventional case shown in FIG.

Furthermore, it is sufficient to simply switch the ROM chip according to the sequence change data, making sequence switching easier than in the past.

〔Effect of the invention〕

As described above, according to the present invention, a rational programmable controller that can easily switch between a plurality of sequence programs while effectively utilizing memory capacity can be obtained.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
3 is a system software transition diagram in the figure, FIG. 3 is a memory map diagram in FIG. 1, FIG. 4 is a configuration diagram of a conventional programmable controller, and FIG. 5 is a conventional memory map diagram. 1 Sequence change data 2 Input circuit 3 CPU 4 Chip select circuit 5 Internal data memory 6 Decoders 8 to 10 Sequence program memory 12
System memory 13 I10 bus interface 14
Human resources department 15 Output section 16 Address bus 17 Data bus 18 I10 bus (8733) Agent Patent attorney Yoshiaki Inomata (and 1 others)
Name) Figure 1 Figure 3 f? Figure 4

Claims (1)

[Claims] Multiple user program memories allocated to the same address area on memory, and one of the multiple user program memories in response to an external program switching request.
A programmable controller characterized by being equipped with a chip select circuit that selects one.