JPH06187148A - Order control circuit for information processor - Google Patents

Abstract

PURPOSE:To provide an order control circuit of an information processor made possible easily performing the branching and feed-back processings of sequences and realizing acceleration. CONSTITUTION:Order control information CD read from a memory circuit 1 is periodically held by a register circuit 2, direct address data D1 in held information are inputted and held by plural program counter circuits 5 and 6 for respective load signals in the held information, one of them is selectively supplied to the memory circuit 1 as memory address data AD and the order control information CD of a next step is read. At this time, whether or not external input signals Sin satisfy conditions set by reference data D2 for judgement is judged, an address selection state is held as it is in the case of satisfying the conditions, one of the plural program counter circuits 5 and 6 is counting operated based on next address selecting signals S1 in the held information and output data are selected in the case of not satisfying the conditions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence control circuit used in an information processing apparatus, and more particularly to a sequence control circuit which detects a change in an external input signal and immediately performs control according to the change.

[0002]

2. Description of the Related Art A sequence control circuit used in a conventional information processing apparatus has been composed of individual circuit elements such as logic gates and flip-flops. In recent years, this type of sequence control circuit has a microprogram system. It has been adopted.

In this microprogram system, a plurality of pieces of information for order control (hereinafter referred to as order control information) are stored in advance in a memory circuit, and arbitrary order control information is taken out by addressing and synchronized with a clock. Then, they are sequentially taken into the register circuit and held. Then, the held sequence control information is compared with the external input signal, and the sequence control information of the next step is read from the memory circuit by address switching from the comparison result.

Specifically, first, it is determined whether or not the external input signal matches the condition set by the sequence control information,
If they match, the branch address in the sequence control information is loaded into the program counter for address generation to generate the same address, and the same sequence control information is taken out from the memory circuit. When the state of the external input signal changes and the setting conditions of the sequence control information do not match, the program counter is started, the address is switched sequentially, and the sequence control information that matches the setting conditions is selected from the memory circuit. I am trying to change.

However, in the order control circuit using the conventional microprogram system as described above, when the address is branched from the order control information and then the address is returned to the position before the branch again, the address immediately before the branch is set before the branch. It must be stored temporarily and then returned to the original position by referring to that address, or the branch address must be stored in advance in the memory circuit as control information. It was complicated and difficult to speed up.

[0006]

As described above, in the conventional sequence control circuit of the information processing apparatus, the sequence branching and restoring processing is complicated and it is difficult to increase the speed.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a sequence control circuit of an information processing apparatus which can easily perform sequence branching and restoring processing and can realize high speed.

[0008]

A sequence control circuit of an information processing apparatus according to the present invention includes a plurality of sequence control information each including direct address data, reference data for determination, a next address control signal, and a plurality of load signals. Each of which is stored in advance at a plurality of addresses, a register circuit which periodically holds the order control information read from the memory circuit, and outputs by data and by signal, and a load output by each of the register circuits. A plurality of program counter circuits that take in and output the direct address data output from the register circuit according to one of the signals, and select one of the output data of the plurality of program counter circuits to select the memory address data. From the register circuit and the address switching circuit supplied to the memory circuit as The external input determination circuit that compares the input determination reference data with the external input signal and determines whether the external input signal satisfies the conditions set by the determination reference data, and this external input determination circuit When it is determined that the conditions are satisfied, the operating states of the plurality of program counter circuits and address switching circuits are retained as they are,
When the external input determination circuit determines that the condition is not satisfied, one of the plurality of program counter circuits is caused to perform a count operation based on the next address control signal output from the register circuit, and the output data is output to the address. And a program counter control circuit for selecting the switching circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the arrangement of a sequence control circuit according to the present invention. In FIG. 1, a memory circuit 1 stores in advance a plurality of control data (sequence control information of a predetermined format) corresponding to various states of an external input signal, and selectively reads and outputs control data corresponding to the memory address data AD. .

The sequence control information is the next address selection signal S.
1, determination permission signal S2, first load signal S3, second load signal S4, direct address data D1, and determination reference data D2.

The register circuit 2 fetches and holds the control data (sequence control information) CD read from the memory circuit 1 in synchronization with the clock signal CK and outputs it by signal and by data.

The external input judgment circuit 3 compares the judgment reference data D2 output from the register circuit 2 with the external input signal Sin, and whether the external input signal Sin satisfies the condition set by the reference data D2. Determine whether or not.

The program counter control circuit 4 is activated by the clock signal CK, and outputs the next address selection signal S1 from the register circuit 2, the judgment permission signal S2, and the judgment result signal S5 from the external input judgment circuit 3 based on the judgment result signal S5. The 1-count permission signal S6, the second count permission signal S7, and the address switching signal S8 are generated.

The first program counter circuit 5 and the second program counter circuit 6 both have the same structure, are set to an initial state by a reset signal RS, and are activated by corresponding count enable signals S6 and S7, respectively, and the above register is set. Load signal S output from circuit 2
The direct address data D1 output from the register circuit 2 is fetched and output according to S3 and S4.

The address switching circuit 7 selects one of the address data AD1 and AD2 output from the first and second program counter circuits 5 and 6 according to the address switching signal S8 output from the program counter control circuit 4. And supplies it to the memory circuit 1.

The operation of the above arrangement will be described below.

First, in the initial state, the reset signal R
The data in the first and second program counter circuits 5, 6 is cleared (initial value) by S, and the initial address AD1,
It is assumed that either one of AD2 is supplied to the memory circuit 1 via the address switching circuit 7 and the certain control data CD is read. The register circuit 2 holds the control data CD in synchronization with the clock signal CK and distributes the control data CD by signal or data.

Of these, the judgment reference data D2 is supplied to the external input judgment circuit 3 together with the external input signal Sin. The external input determination circuit 3 determines whether or not the external input signal Sin satisfies the condition set by the reference data D2,
When the condition is satisfied, the determination result signal S5 of logic "1" is output, and when the condition is not satisfied, the determination result signal S5 of logic "0" is output.

The determination result signal S5 is supplied to the program counter control circuit 4 together with the next address selection signal S1 and the determination permission signal S2 output from the register circuit 3. The program counter control circuit 4 is provided with the input / output table shown in FIG. 2 in advance. When the clock signal CK is supplied, the program counter control circuit 4 refers to this table to check the states of the input signals S1, S2, S5. The respective logic levels of the first and second count enable signals S6 and S7 and the address switching signal S8 are determined.

In FIG. 2, when the determination permission signal S2 is logic "0" (FIGS. 2A and 2B), the count permission signals S6 and S7 and the address switching signal S8 are all the determination result signal S5. Becomes irrelevant and is determined by the logic level of the next address selection signal S1.

Here, the next address selection signal S1 is logic 0.
(FIG. 2 (a)), the address switching signal S8 is logic "0", the first count enable signal S6 is logic "1",
The second count enable signal S7 is set to logic "0".

When the next address selection signal S1 is logic "1" (FIG. 2B), the address switching signal S8 is logic "1".
In addition, the first count enable signal S6 is set to logic "0" and the second count enable signal S7 is set to logic "1".

On the other hand, when the determination permission signal S2 is logic "1" (FIGS. 2C, 2D and 2E), the following is performed.

When the determination result signal S5 is logic "1" and the next address selection signal S1 is logic "0" (FIG. 2 (c)),
The address switching signal S8 is logic "0", the first count enable signal S6 is logic "1", and the second count enable signal S7 is
Is set to a logical "0".

When the determination result signal S5 is logic "1" and the next address selection signal S1 is logic "1" (FIG. 2 (d)),
The address switching signal S8 has a logic "1", the first count enable signal S6 has a logic "0", and the second count enable signal S7.
Is set to a logical "1".

When the judgment result signal S5 is logic "0" (FIG. 2 (e)), none of the address switching signal S8, the first count permission signal S6, and the second count permission signal S7 are changed, and the preceding signal. State is retained.

The first logical level is set as described above
The count enable signal S6 is the first program counter circuit 5
In addition, the second count enable signal S7 is supplied to the second program counter circuit 6.

The first program counter circuit 5 outputs the first address data AD1 under the following conditions.

When the first load signal S3 supplied from the register circuit 2 is a logic "1", the direct address data D1 supplied from the register circuit 2 is input and held internally, and then as the first address data AD1. Output. However, its output state is determined by the logic level of the first count enable signal S6.

That is, irrespective of the logic level of the first load signal S3, when the first count enable signal S6 is logic "0", the first program counter circuit 5 does nothing and retains the data already held. It is held and output as the first address data AD1. In addition, the first load signal S3 is logic "1" and the first count enable signal S6
Also has a logic "1", it adds 1 to the data held so far and holds it internally and outputs it as the first address data AD1.

Similarly, the second program counter circuit 6
Outputs the second address data AD2 under the following conditions.

When the second load signal S4 supplied from the register circuit 2 is logic "1", the direct address data D1 supplied from the register circuit 2 is input and held internally, and then as the second address data AD2. Output. However, its output state is determined by the logic level of the second count enable signal S7.

That is, irrespective of the logic level of the second load signal S4, when the second count enable signal S7 is logic "0", the second program counter circuit 6 does nothing and retains the data already held. It is held and output as the second address data AD2. Further, the second load signal S4 is logic "1" and the second count enable signal S7
Also, when it is a logic 1, it adds 1 to the data that has been held so far, holds it internally, and outputs it as the second address data AD2.

First and second program counter circuits 5, 6
From the first and second address data AD1, AD
2 is supplied to the address switching circuit 7. The address switching circuit 7 derives the first address data AD1 as the memory address data AD to the memory circuit 1 when the address switching signal S8 supplied from the program counter control circuit 4 is logical "0", and the address switching signal S8 is output. Is logic "1", the second address data AD2 is supplied to the memory circuit 1 as the memory address data AD.

The memory circuit 1 reads the control data CD in the area designated by the input memory address data AD and sends it to the register circuit 2. The register circuit 2 holds the control data CD in synchronization with the clock signal CK.

After that, the above operation is repeated to compare the judgment reference data D2 in the control data CD with the external input signal Sin. If the condition is satisfied, the same control data is used in the next step and the condition is satisfied. If is not satisfied, in the next step, the control data corresponding to the address data added by 1 is processed.

Therefore, in the sequence control circuit having the above-mentioned configuration, the jump destination address at the time of branching the control is set in each of the program counter circuits 5 and 6 by the plurality of program counter circuits 5 and 6, and the external input is performed. When the control sequence is changed according to the state of the signal Sin, the addresses AD1 and AD2 output from the plurality of program counter circuits 5 and 6 are selected and used as the memory address AD, which is extremely easy. It is possible to perform the branching and returning processing of the sequence, and thereby to speed up the processing.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications without departing from the gist of the present invention.

[0040]

As described above, according to the present invention, it is possible to provide a sequence control circuit of an information processing device which facilitates branching and restoring of a sequence and can realize high speed.

[Brief description of drawings]

FIG. 1 is a block circuit configuration diagram showing an embodiment of a sequence control circuit of an information processing apparatus according to the present invention.

FIG. 2 is a table configuration diagram showing input / output conditions of a program counter control circuit of the same embodiment.

[Explanation of symbols]

 1 memory circuit 2 register circuit 3 external input determination circuit 4 program counter control circuit 5 first program counter circuit 6 second program counter circuit 7 address switching circuit AD memory address data CD sequence control data D1 direct address data D2 determination reference data Sin External input signal CK Clock signal RS Reset signal S1 Primary address selection signal S2 Judgment permission signal S3 First load signal S4 Second load signal S5 Judgment result signal S6 First count permission signal S7 Second count permission signal S8 Address switching signal AD1 1 address data AD2 2nd address data

Claims (1)

[Claims] 1. A memory circuit in which a plurality of order control information each including direct address data, judgment reference data, a next address control signal, and a plurality of load signals are stored in advance in a plurality of addresses, respectively, and the memory circuit. From the register circuit that periodically holds the sequence control information read from the register circuit and outputs the data according to the data and the signal according to one of the plurality of load signals output from the register circuit. A plurality of program counter circuits for fetching and outputting the direct address data; an address switching circuit for selecting one of the output data of the plurality of program counter circuits and supplying it as memory address data to the memory circuit; The judgment reference data output from the register circuit and the external input signal Comparing the door, and the external input judging circuit judges whether to satisfy the condition that external input signal is set by the determination reference data, when the external input determination circuit determines that the condition is satisfied,
Based on the next address control signal output from the register circuit when the operation states of the plurality of program counter circuits and the address switching circuit are held as they are and the external input determination circuit determines that the conditions are not satisfied. And a program counter control circuit for causing one of the plurality of program counter circuits to perform a count operation and select output data thereof from the address switching circuit.