JP2004062401A - Arithmetic processor and camera device using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic processor capable of executing conditional branching and maximum or minimum value computation at a high speed. <P>SOLUTION: Instruction executing parts 10 of processor elements 13<SB>1</SB>-13<SB>n</SB>compare magnitudes of data inputted from data input ports 200, 201, and either of the output value of the comparison result and a value of a flag register 8<SB>1</SB>is selected according to the input value of an instruction code 203. Based on this result, one of the data input from the data input ports 200, 201 is selected and outputted from a data output port 204. Thus, for example, the procedure of executing a process "r2 = max (r0, r1)" for determining the greater of two figures r0, r1 and storing the result in r2 is described as "MAX r2, ro, r1," and can be executed in one instruction step. A MAX instruction is a maximum value instruction (an instruction to store the greater of the two figures r0, r1 in r2). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an arithmetic processor for efficiently executing a conditional branch (conditional branch instruction), a maximum value operation, or a minimum value operation, and a camera device using the arithmetic processor.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a SIMD (Single Instruction Multiple Data) type parallel operation processor, the same operation is performed simultaneously on a plurality of data to thereby speed up the operation process. That is, since the arithmetic processor has a configuration in which processing for one instruction stream is performed in parallel in each of the plurality of processor elements, an instruction step (for example, an instruction step (eg, , A conditional branch instruction step) cannot be executed in parallel in each processor element along this one instruction stream.
[0003]
In order to solve this problem, the literature: “Y. Fujita et al (NEC)“ IMAP: Integrated Memory Array Processor ”, Journal of Circuits, Systems and Computers, Vol. 2, No. 2, p. For each processor element, a mask register indicating whether or not to perform processing in accordance with the instruction stream on the instruction bus is installed, and the instruction stream corresponding to each branch destination of the conditional branch is flowed in the instruction bus in a time-division manner. The branch is being executed. That is, the hardware is provided with a circuit dedicated to performing conditional branching, thereby executing conditional branching. As a result, processor elements having the same branch destination can be executed in parallel. In addition, high-speed conditional branch processing is realized.
[0004]
As a conventional SIMD (Single Instruction Multiple Data) type parallel operation processor, for example, there is one shown in FIG. Fig. 4 shows the literature: "Y. Fujita et al (NEC)" IMAP: Integrated Memory Array Processor ", Journal of Circuits, Systems and Computers, Vol. FIG. 2 is a block diagram illustrating a main configuration of an arithmetic processor. However, FIG. 1 shows only the instruction issuing unit 900 and the arithmetic processing unit 901 as main components of the processor.
[0005]
As shown in FIG. 4, the processing unit 901 is configured to include a plurality of processor elements ₉₀₃ 1 _{~903 n.} The instruction issuance unit 900 via the instruction bus 902 is connected to a plurality of processor elements ₉₀₃ 1 _{~903 n.} Each of the processor elements 903 _{1 to} 903 _n has a corresponding general-purpose register 906 _{1 to} 906 _n , a mask register 907 _{1 to} 907 _n, and an operation execution unit 908 _{1 to} 908 _n .
[0006]
Hereinafter, the operation of the conventional arithmetic processor shown in FIG. 4 when processing a conditional branch will be described. In the arithmetic processor shown in FIG. 4, when processing a conditional branch (abbreviated as a conditional branch instruction), the mask registers 907 _{1 to} 907 _n are referred to in each of the processor elements 903 _{1 to} 903 _n , and the mask registers 907 _{1 to} 907 _n are respectively referred to. Only the processor element corresponding to the mask register having a value of 1 among 907 _{1 to} 907 _n executes the conditional branch on the instruction bus 902.
[0007]
FIG. 5 is a flowchart illustrating a procedure for executing a conditional branch in a general arithmetic processor. When the processing of the conditional branch shown in the flowchart of FIG. 5 is executed by the conventional arithmetic processor shown in FIG. 4, for example, a sequence of instruction steps as shown below is performed. Is required.
[0008]
CMP r0, r1
SETMR
MUL r2, r0, r3
INVMR
ADD r2, r1, r3
CLRMR
[0009]
Here, r0 to r3 represent registers, the CMP instruction represents a comparison instruction, the MUL instruction represents a multiplication instruction, the ADD instruction represents an addition instruction, and the SETMR, INVMR, and CLRMR instructions respectively represent the result of the comparison instruction and the value of the flag. In the mask registers 407 _{1 to} 407 _n , an instruction to invert the values of the mask registers 407 _{1 to} 407 _n , and an instruction to clear (set 1) the values of the mask registers 407 _{1 to} 407 _n .
[0010]
First, in the instruction step of “CMP r0, r1”, each processor element compares the magnitude relation between r0 and r1, and compares the comparison result (“1” or “0” corresponding to true or false, respectively) with SETMR. It is set in a mask register 407 _{1 to} 407 _n by an instruction. As a result, only the processor element for which the comparison result in the instruction step of “CMP r0, r1” is true is set to 1 in the corresponding mask register, and the instruction step of the next “MUL r2, r0, r3” is set. Will be executed.
[0011]
Next, the value of the mask register 407 _{1 to} 407 _n is inverted by the instruction step of INVMR located therebelow. As a result, the value of the mask register of the processor element for which the comparison result is true is On the contrary, since the value of the mask register of the processor element whose comparison result is false is inverted to 1, only the processor element inverted to 1 at this time is changed to the next " The instruction step ADD r2, r1, r3 "will be executed. Finally, all the values of the mask registers 407 _{1 to} 407 _n are cleared (reset) to ₁ by the CLRMR instruction step, and the process returns to the normal processing.
[0012]
[Problems to be solved by the invention]
However, in the above-described conventional arithmetic processor, it is necessary to execute a branch control instruction such as SETMR, INVMR, or CLRMR in order to set the value of the mask register 407. The ratio of the number of executed instructions for branch control instructions such as SETMR is larger than the number of instructions, and there is a problem in that speeding up of conditional branch processing is hindered. This problem has been particularly remarkable in the case of a conditional branch having a small number of executed instructions after the branch, that is, a conditional branch having a small scale.
[0013]
The present invention has been made in view of the above-described conventional problems, and has as its object to provide an arithmetic processor capable of executing conditional branching at high speed and a camera device using the arithmetic processor. It is another object of the present invention to provide an arithmetic processor capable of executing a maximum value operation or a minimum value operation at high speed and a camera device using the arithmetic processor.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, an arithmetic processor according to the present invention is an arithmetic processor that performs conditional branch processing, and includes an arithmetic execution unit that executes an operation, and an operation result obtained by the operation execution unit. Register means for storing a flag generated from the calculation result obtained by the calculation execution means, and a flag register selected from the flags stored in the flag register means. And selecting command execution means for selecting one from a plurality of input data input from the register means and outputting the selected data to the register means. Therefore, it is possible to speed up the conditional branch processing in which the operation content changes depending on the data.
[0015]
Further, an arithmetic processor according to the present invention is an arithmetic processor that selects appropriate data from a plurality of data based on an instruction code, and is obtained by an arithmetic execution unit that executes an arithmetic operation and the arithmetic execution unit. Register means for registering the calculated operation result, flag register means for storing a flag generated from the operation result obtained by the operation execution means, and an instruction for performing a predetermined process based on the specified instruction code. Executing means, wherein the instruction executing means compares values of a plurality of input data, and outputs information indicating a maximum or minimum value of the plurality of input data, In accordance with the designated instruction code, either the information output from the comparing means or the flag selected from the flags stored in the flag register means Selecting one of a plurality of input data input from the register means based on first selection means for selecting and outputting and information or a flag output from the first selection means; Second selecting means for outputting the data to the register means. Therefore, it is possible to speed up the conditional branch processing or the maximum value operation or the minimum value operation in which the operation content changes depending on the data by adding a small amount of hardware.
[0016]
In the arithmetic processor according to the present invention, the specified instruction code may be one of the plurality of input data in accordance with a value of a flag selected from the flags stored in the flag register means. If the instruction code is an instruction code to output, the first selecting means outputs a flag selected from the flags stored in the flag register means, and the second selecting means outputs the selected flag. One of a plurality of input data input from the register means is selected according to the value of the flag thus set. Therefore, it is possible to speed up the conditional branch processing in which the operation content changes depending on the data.
[0017]
Further, the arithmetic processor according to the present invention, when the specified instruction code is an instruction code instructing to output data having a maximum value among a plurality of input data input from the register means, The comparing means outputs information indicating the data having the largest value among the plurality of input data, the first selecting means outputs the information output from the comparing means, and the second selecting means Selects the data indicated by the information output from the first selecting means, and outputs the data having the minimum value among the plurality of input data input from the register means, by the specified instruction code. If the instruction code is such that the instruction code indicates, the comparing means outputs information indicating the data having the smallest value among the plurality of input data, and the first selecting means outputs the information output from the comparing means. Output, the second selecting means selects the data indicated by the information output from said first selecting means. Therefore, it is possible to speed up the maximum value operation or the minimum value operation in which the operation content changes depending on the data.
[0018]
Further, a camera device according to the present invention uses the arithmetic processor according to claims 1, 2, 3 or 4 as an image processing means for processing an image signal. Therefore, it is possible to provide a camera device that enables high-speed shooting and easily changes specifications.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of an arithmetic processor according to the present invention will be described in detail in the order of [first embodiment] and [second embodiment] with reference to the drawings. Further, a camera device according to the present invention will be described in detail as a third embodiment with reference to the drawings. Note that the arithmetic processors of the first and second embodiments are SIMD (Single Instruction Multiple Data) type parallel arithmetic processors.
[0020]
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of the arithmetic processor according to the first embodiment of the present invention. As shown in the figure, the arithmetic processor in the first embodiment, the instruction issue unit 1, an instruction bus 2 is constructed by a plurality of processor elements 3 ₁ to 3 _n.
[0021]
The processor elements 3 _{1 to} 3 _n include general-purpose registers 6 _{1 to} 6 _n corresponding to register means used in the arithmetic execution units 7 _{1 to} 7 _n described later, which are used for registering arithmetic results, and the like. and operation executing section 7 ₁ to _7-n corresponding to the operation execution unit, the flag register 8 _1-8 corresponding to the flag register means for storing a variety of flags generated by the operation result of the arithmetic execution unit 7 ₁ to _7-n and _n, and a selection instruction execution unit 9 ₁ to 9 _n corresponding to the selected instruction execution unit. The selection instruction execution unit _{9 1} includes a data input port 100 and 101 connected to the general-purpose register _61, a data output port 102, and a condition input port 103, and a selector 104. Incidentally, although not shown, a selection command is configured in the execution unit 9 ₂ to 9 _n be the same as selected instruction execution unit 9 ₁ configuration, configuration of processors elements 3 ₁ processor element 3 ₂ to 3 _n The configuration is the same.
[0022]
In the arithmetic processor of this structure, the instruction read from the instruction issue unit 1 is supplied to each processor element 3 ₁ to 3 _n through the instruction bus 2. Then, the processor element 3 _1, selector 104 selects the instruction execution unit 9 _1, depending on the value of the flag input from the condition input port 103, either of the two data input from the data input port 100 and 101 One of them is selected and output from the data output port 102. Data input port 100 and 101 and the data output port 102 is connected to the general-purpose register _61, the current to the operation result by the operation execution unit ₇₁ in the general register ₆₁ is numeric. The condition input port 103 is connected to the flag register _81, and to be able to enter values for any of the flags among the plurality of calculation result flag.
[0023]
Hereinafter, the number of instruction steps required for the conditional branch in the arithmetic processor of the present embodiment will be compared with the conventional arithmetic processor. An instruction step sequence by the arithmetic processor of the present embodiment when performing the processing of the conditional branch shown in the flowchart of FIG. 5 is shown below.
[0024]
MUL r2, r0, r3
ADD r4, r1, r3
CMP r0, r1
SEL r2, r2, r4
[0025]
Here, the SEL command is intended to refer to a selection instruction proposed by the present invention, more specifically, "SEL r2, r2, r4", the execution of the CMP instruction immediately before each processor element ₃ 1 to 3 _n By inputting the flag value based on the result to the condition input port 103, inputting the values of the registers r2 and r4 to the data input ports 100 and 101, and storing the output value from the data output port 102 in the register r2, the CMP instruction is executed. It is assumed that the instruction step is to execute a process of selecting one of the value of the register r2 and the value of r4 in accordance with the execution result of the step and substituting the value into the register r2.
[0026]
The instructions “MUL r2, r0, r3” and “ADD r4, r1, r3” corresponding to the processing steps 501, 502 at both branch destinations shown in FIG. 5 are compared with the instructions “CMP r0, r1” corresponding to the comparison processing step 500. ", And both operation results are temporarily saved in the registers r2 and r4. After that, “CMP r0, r1” is executed, and a selection instruction “SEL r2, r2, r4” for selecting a value from the register r2 or r4 according to the comparison result is executed. Is substituted.
[0027]
With such an arrangement of instruction steps, it becomes possible for all processor elements 3 _{1 to} 3 _n to execute simultaneously in each processor element without disturbing the sequence of the instruction sequence, and furthermore, for each processor element, an appropriate The result can be obtained.
[0028]
Also, when the processing of the flow shown in FIG. 5 is executed by the arithmetic processor having the configuration shown in FIG. 1, six instruction steps were conventionally required. In the present embodiment, the selection instruction SEL is selected by the selection instruction execution unit 9. By performing the above operation, the program can be executed in four instruction steps. Therefore, it is possible to speed up the conditional branch processing in which the operation content changes depending on the data.
[0029]
In the description of the present embodiment, two data input ports and one condition input port are used. However, three or more data input ports and two or more condition input ports are provided, and one out of three or more data is provided. May be selected. In this case, the conditional branch processing for branching into three or more branches can be executed at high speed.
[0030]
[Second embodiment]
FIG. 2 is a block diagram illustrating a configuration of the arithmetic processor according to the second embodiment of the present invention. As shown in the figure, the processor elements 13 _{1 to} 13 _n of the second embodiment are different from the processor elements 3 _{1 to} 3 _n shown in FIG. and a command execution unit 10 ₁ to 10 _n corresponding to the instruction execution unit in the claims to perform branch processing or maximum value calculation or minimum value operation. The instruction execution units 10 ₁ to 10 _n correspond to two data input ports 200 and 201, a 1-bit condition input port 202, an instruction code input port 203, a data output port 204, and a second selection unit. The selector 205 includes a selector 205, a selector 206 corresponding to a first selector, and a comparator 207 corresponding to a comparator. Incidentally, although not shown, the configuration of the processor element ₁₃ 2 to 13 _n are the same as the configuration of the processor element 13 _1.
[0031]
The selector 205 selects one of the two data input from the data input ports 200 and 201 according to the output value from the selector 206 and outputs the selected data from the data output port 204. The comparator 207 compares the values of the two data input from the data input ports 200 and 201 and outputs the information indicating the maximum or minimum data to the selector 206 in one bit. The selector 206 selects one of the data input from the condition input port 202 and the information output from the comparator 207 according to the instruction code input to the instruction code input port 203. Output. Data input port 200, 201 and the data output port 204 is connected to the general-purpose register _61, the condition input port 202 is connected to the flag register _81, the instruction code input port 203 is connected to the instruction bus 2 I have.
[0032]
Hereinafter, the operation in the case where the conditional branch processing, the maximum value operation, or the minimum value operation is executed in the arithmetic processor of the present embodiment will be described.
[0033]
<Conditional branch processing>
When the conditional branch processing is executed using the selection instruction, the processing is performed in the same procedure as the procedure described in the first embodiment. However, in order to select data input from the condition input port 202 as data to be input from the selector 206 to the selector 205, an instruction code indicating a selection instruction is input to the instruction code input port 203.
[0034]
<Maximum value calculation, Minimum value calculation>
To execute the maximum value operation or the minimum value operation, an instruction code indicating that the instruction is the maximum instruction or the minimum instruction is input to the instruction code input port 203, and the comparator 206 is used as data to be input from the selector 206 to the selector 205. The data output from 207 is selected. The comparator 207 compares the values of the data input to the data input ports 200 and 201, and the result of the comparison is input to the selector 205. , Is output from the data output port 204. Therefore, the maximum value or the minimum value can be obtained for each processor element.
[0035]
For example, when the processing “r2 = max (r0, r1)” of obtaining the larger value of the two numbers r0 and r1 and storing the result in r2 is performed using the arithmetic processor of the present embodiment, The execution procedure can be executed in one instruction step as shown below. The MAX instruction below indicates a maximum value instruction, and indicates that a larger one of two numbers r0 and r1 is stored in r2.
[0036]
MAX r2, r0, r1
[0037]
On the other hand, when the selection instruction is executed, the execution procedure is as follows and requires two instruction steps.
[0038]
CMP r0, r1
SEL r2, r0, r1
[0039]
As described above, the provision of the instruction execution units 10 ₁ to 10 _n can speed up the maximum value operation or the minimum value operation in which the operation content changes depending on the data. The instruction execution unit ₁₀ 1 to 10 _n of the present embodiment, the first embodiment of the selection instruction execution unit ₉ 1 to 9 _n to comparator ₂₀₇ 1 to 207 _n and 1-bit selector ₂₀₆ 1 -206 _n It can be realized simply by adding. Furthermore, since a comparison instruction is usually present in the instruction set of a general processor, it is common that a comparator is originally present, and if this comparator is used, a new one must be added. There is almost no hardware required, and the maximum value operation and the minimum value operation can be executed at high speed by adding only a small amount of hardware.
[0040]
In the present embodiment, the comparator 207 is described as an example, but a subtractor may be used instead of the comparator 207. In that case, a bit representing the sign of the result of the subtractor is input to the selector 206, and the same effect can be obtained.
[0041]
Further, in the present embodiment, two data input ports and one condition input port are used, and the comparing means is the comparator 207 which compares the two numbers. However, three or more data input ports and three or more condition input ports are used. And a comparator for comparing three or more numbers as comparison means. When executing as a selection instruction, one of three or more numbers is selected, and a maximum value instruction or a minimum value instruction is selected. When executing as a value instruction, the maximum value or the minimum value of three or more numbers may be obtained.
[0042]
[Third embodiment]
FIG. 3 is a block diagram illustrating a configuration of a camera device according to a third embodiment of the present invention. As shown in the figure, the camera device according to the present embodiment includes an imaging unit 300, an A / D converter 301, an image processing processor 302 corresponding to an image processing unit in the claims, an image storage unit or an image storage unit. The transmission unit 303 is configured. Note that the arithmetic processor of the first or second embodiment is used as the image processor 302.
[0043]
The image captured by the imaging unit 300 is converted into a digital signal by the A / D converter 301, processed by the image processor 302, and sent to the image storage unit or the image transmission unit 303. According to the present embodiment, the image processing specification can be changed only by changing the software that controls the image processing processor 302, as compared with a camera device using a dedicated image processing circuit. Further, since a high-speed arithmetic processor is used as the image processing processor 302, a camera device that can perform high-speed imaging, that is, high-speed image processing can be realized.
[0044]
【The invention's effect】
As described above, according to the arithmetic processor according to the present invention, it is possible to speed up conditional branch processing or maximum value operation or minimum value operation in which the operation content changes depending on data. Further, it is possible to provide a camera device that enables high-speed shooting and easily changes specifications.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an arithmetic processor according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of an arithmetic processor according to a second embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of a camera device according to a third embodiment of the present invention; FIG. , No. 3, pp. 227-245, 1992 "is a block diagram showing a main configuration of an arithmetic processor. [FIG. 5] A flowchart for explaining an execution procedure of a conditional branch in a general arithmetic processor.
1 instruction issue unit 2 instruction bus ₃ 1 to 3 _n processor elements ₆ 1 to 6 _n general purpose registers ₇ 1 to _7-n execution unit ₈ 1 to 8 _n flag register ₉ 1 to 9 _n selection instruction execution unit 10 selects instruction-up Value command / minimum value command execution unit 100, 101 data input port 102 data output port 103 condition input port 104 selector 200, 201 data input port 202 condition input port 203 instruction code input port 204 data output port 205 selector 206 selector 207 Comparator 300 Imaging unit 301 A / D converter 302 Image processor 303 Image storage unit or image transmission unit 900 Command issuing unit 901 Operation processing unit 902 Command buses 903 _{1 to} 403 _n Processor elements 906 _{1 to} 906 _n General purpose register 907 _{1 ~907 n} mask register 9 8 ₁ ~908 _n execution unit

Claims (5)

An arithmetic processor that performs conditional branch processing,
Operation execution means for executing an operation;
Register means for setting the operation result obtained by the operation execution means,
Flag register means for storing a flag generated from the calculation result obtained by the calculation execution means,
According to the value of the flag selected from the flags stored in the flag register means, one of a plurality of input data input from the register means is selected, and the selected data is stored in the register means. And a selection instruction executing means for outputting the selected instruction to the processor. An arithmetic processor that selects appropriate data from a plurality of data based on an instruction code,
Operation execution means for executing an operation;
Register means for setting the operation result obtained by the operation execution means,
Flag register means for storing a flag generated from the calculation result obtained by the calculation execution means,
Instruction execution means for performing predetermined processing based on the instructed instruction code,
The instruction execution means includes:
A comparing unit that compares values of a plurality of input data and outputs information indicating a maximum or a minimum value of the plurality of input data,
First selecting means for selecting and outputting either the information output from the comparing means or the flag selected from the flags stored in the flag register means according to the designated instruction code; ,
A second step of selecting one of a plurality of input data input from the register means based on information or a flag output from the first selection means, and outputting the selected data to the register means; And a selecting means. When the specified instruction code is an instruction code instructing to output one from the plurality of input data in accordance with a value of a flag selected from the flags stored in the flag register means. ,
The first selecting means outputs a flag selected from the flags stored in the flag register means,
3. The processor according to claim 2, wherein said second selecting means selects one from a plurality of input data input from said register means according to a value of said selected flag. When the specified instruction code is an instruction code instructing to output data having a maximum value among a plurality of input data input from the register means,
The comparing means outputs information indicating data having a maximum value among the plurality of input data,
The first selecting means outputs information output from the comparing means,
The second selecting means selects data indicated by the information output from the first selecting means,
When the specified instruction code is an instruction code instructing to output data having a minimum value among a plurality of input data input from the register means,
The comparing means outputs information indicating data having a minimum value among the plurality of input data,
The first selecting means outputs information output from the comparing means,
4. The processor according to claim 2, wherein said second selecting means selects data indicated by the information outputted from said first selecting means. A camera device using the arithmetic processor according to claim 1, 2, 3, or 4 as image processing means for processing an image signal.

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