US8954483B2 - Arithmetic circuit and arithmetic apparatus - Google Patents
Arithmetic circuit and arithmetic apparatus Download PDFInfo
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- US8954483B2 US8954483B2 US13/546,683 US201213546683A US8954483B2 US 8954483 B2 US8954483 B2 US 8954483B2 US 201213546683 A US201213546683 A US 201213546683A US 8954483 B2 US8954483 B2 US 8954483B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
Definitions
- the present invention relates to an arithmetic circuit and an arithmetic apparatus and, particularly, to an arithmetic circuit and an arithmetic apparatus that perform parallel processing.
- the color space is used as a means of representing color information of pixels that form an image.
- the RGB System that represents Red-Green-Blue additive color mixing is widely used.
- the HSV System is often used for the reason that it offers familiarity with the sense of humans, being users.
- the HSV System represents color information using three elements of Hue, Saturation and Value.
- RGB color space which is referred to hereinafter as RGB color space
- HSV color space color information represented in the HSV System
- conversion between two systems is required.
- the conversion is performed by an image processor or the like.
- a general instruction-set processor such as an image processor
- 2-input 1-output instructions are often used.
- VLIW Very Long Instruction Word
- Hue (H), Saturation (S) and Value (V) are represented as follows. Note that the minimum of Red (R), Green (G) and Blue (B) is 0, and the maximum is 1.
- Hue (H) differs depending on which of R, G and B is the maximum.
- Hue (H) is represented by the following equation (1).
- MAX indicates the value of R, which is the maximum value.
- MIN indicates the minimum value among R, G and B, which is the smaller value of G and B.
- Equation ⁇ ⁇ ( 1 ) ⁇ : H 60 ⁇ G - B MAX - MIN + 0 ( 1 )
- Hue (H) is represented by the following equation (2).
- MAX indicates the value of G, which is the maximum value.
- MIN indicates the minimum value among R, G and B, which is the smaller value of R and B.
- Equation ⁇ ⁇ ( 2 ) ⁇ : H 60 ⁇ B - R MAX - MIN + 120 ( 2 )
- Hue (H) is represented by the following equation (3).
- MAX indicates the value of B, which is the maximum value.
- MIN indicates the minimum value among R, G and B, which is the smaller value of R and G.
- Equation ⁇ ⁇ ( 3 ) ⁇ : H 60 ⁇ R - G MAX - MIN + 240 ( 3 )
- Saturation (S) is represented by the following equation (4).
- Value (V) is represented by the following equation (5).
- conditional branch to compare three values of R, G and B and operation to obtain the maximum value MAX and the minimum value MIN of R, G and B are required when calculating Hue (H). Further, it is also required to obtain a difference between two values other than the maximum value MAX (the numerator of the fraction in the first term of the right hand side of the equations (1) to (3)).
- VLIW processor As an arithmetic processor to perform the conditional branch and calculate the maximum value and the minimum value, a VLIW processor is known, for example. Various other processors are also proposed.
- the maximum value of the two values r1 and r2 is stored in the value r4.
- the maximum value of the two values r3 and r4 is stored in the value r4.
- the value r4 is temporarily stored in the register file after executing the first cycle, and then the stored value r4 is referred to in the second cycle. This is the same in the case of calculating the minimum value.
- the maximum value of R, G and B needs to be known before performing calculation by the above equations (1) to (3), it is necessary to calculate the maximum value in advance.
- One aspect of the present invention is an arithmetic circuit that includes a plurality of computing units that perform arithmetic computations on input data and output flag information generated based on a result of the computations, a plurality of selection circuits that select any one of the data input to the plurality of computing units, and a decision unit that receives the flag information from the plurality of computing units and controls select operation of each of the plurality of selection circuits.
- the select operation of the selection circuits may be controlled based on a magnitude relation of the data input to the computing units, so that the selection circuits select a maximum value, a minimum value and a difference of values other than the maximum value. It is thereby possible to calculate the maximum value, the minimum value and the difference of values other than the maximum value in a single cycle without storing data into a register in the process of the computations.
- FIG. 1 is a block diagram schematically showing a configuration of an arithmetic apparatus 100 according to a first embodiment
- FIG. 2 is a diagram showing a decision table 41 stored in a decision unit 40 ;
- FIG. 3 is a block diagram schematically showing a configuration of the arithmetic apparatus 100 when setting the decision table 41 externally;
- FIG. 4 is a diagram showing set values of the decision table 41 ;
- FIG. 5 is a diagram showing a structure example of a value val of decision information setting instruction SET according to the first embodiment
- FIG. 6 is a diagram showing a relation between the value val of the decision information setting instruction SET and the set values of the decision table 41 ;
- FIG. 7 is a block diagram schematically showing a configuration of an arithmetic apparatus 200 according to a second embodiment
- FIG. 8 is a diagram showing a decision table 42 for sorting stored in the decision unit 40 ;
- FIG. 9 is a block diagram schematically showing a configuration of the arithmetic apparatus 200 when setting the decision table 42 externally;
- FIG. 10 is a diagram showing a structure example of the value val of the decision information setting instruction SET according to the second embodiment
- FIG. 11 is a block diagram schematically showing a configuration of an arithmetic apparatus 300 according to a third embodiment.
- FIG. 12 is a diagram showing a decision table 44 stored in a decision unit 43 .
- FIG. 1 is a block diagram schematically showing a configuration of the arithmetic apparatus 100 according to the first embodiment.
- the arithmetic apparatus 100 includes a register file 101 and an arithmetic circuit 10 .
- the register file 101 stores data to be used for computations of the arithmetic circuit 10 or data calculated by computations of the arithmetic circuit 10 .
- the register file 101 is provided with ports IN 1 to IN 3 through which data are input. Further, the register file 101 outputs data D 0 to D 2 to the arithmetic circuit 10 . Note that the data D 0 to D 2 correspond to first to third data, respectively.
- the register file 101 may have other ports or output other data, and which port to be used or which data to be output can be designated by an instruction from an external control circuit (not shown), for example.
- the arithmetic circuit 10 includes a plurality of slots 11 to 13 and a decision unit 40 .
- the slots 11 to 13 include adders/subtracters CAL 11 to CAL 13 and selectors SEL 11 to SEL 13 , respectively.
- the adder/subtracter is one example of a computing unit, and the adders/subtracters CAL 11 to CAL 13 correspond to first to third computing units, respectively.
- the selectors SEL 11 to SEL 13 are 3-input 1-output selectors.
- the selector is one example of a selection circuit, and the selectors SEL 11 to SEL 13 correspond to first to third selection circuits, respectively.
- the data D 0 and D 1 are input to the adder/subtracter CAL 11 from the register file 101 .
- the adder/subtracter CAL 11 then outputs a computation result C 1 to the selector SEL 13 . Further, the adder/subtracter CAL 11 outputs a sign flag F 1 to the decision unit 40 .
- the data D 0 to D 2 are respectively input from the register file 101 to input ports ps 0 to ps 2 of the selector SEL 11 .
- the selector SEL 11 then outputs any one of the data D 0 to D 2 as a maximum value MAX to the port IN 1 of the register file 101 based on a control signal CON 1 from the decision unit 40 .
- the data D 1 and D 2 are input to the adder/subtracter CAL 12 from the register file 101 .
- the adder/subtracter CAL 12 then outputs a computation result C 2 to the selector SEL 13 . Further, the adder/subtracter CAL 12 outputs a sign flag F 2 to the decision unit 40 .
- the data D 0 to D 2 are respectively input from the register file 101 to input ports ps 0 to ps 2 of the selector SEL 12 .
- the selector SEL 12 then outputs any one of the data D 0 to D 2 as a minimum value MIN to the port IN 2 of the register file 101 based on a control signal CON 2 from the decision unit 40 .
- the data D 2 and D 0 are input to the adder/subtracter CAL 13 from the register file 101 .
- the adder/subtracter CAL 13 then outputs a computation result C 3 to the selector SEL 13 . Further, the adder/subtracter CAL 13 outputs a sign flag F 3 to the decision unit 40 .
- the computation results C 1 to C 3 of the adders/subtracters CAL 11 to CAL 13 are respectively input to input ports ps 0 to ps 2 of the selector SEL 13 .
- the selector SEL 13 then outputs any one of the computation results C 1 to C 3 as a difference DIFF to the port IN 3 of the register file 101 based on a control signal CON 3 from the decision unit 40 .
- sign flag is flag information that is output according to the computation result of the adder/subtracter, and the sign flags F 1 to F 3 correspond to first to third sign flags, respectively.
- the decision unit 40 outputs the control signals CON 1 to CON 3 to the selectors SEL 11 to SEL 13 , respectively, by reference to a stored decision table 41 on the basis of the sign flags F 1 to F 3 .
- the decision table 41 correspond to a first decision table.
- the arithmetic circuit 10 reads the data D 0 to D 2 from the register file 101 .
- the arithmetic circuit 10 detects the maximum value MAX and the minimum value MIN of the data D 0 to D 2 and the difference DIFF between two values other than the maximum value MAX. Then, the arithmetic circuit 10 outputs the maximum value MAX, the minimum value MIN, and the difference DIFF between two values other than the maximum value MAX to the register file 101 .
- the adder/subtracter CAL 11 subtracts the value of the data D 1 from the value of the data D 0 and outputs the subtraction result as the computation result C 1 . Further, the adder/subtracter CAL 11 outputs the sign flag F 1 according to the subtraction result. Specifically, when the sign of the computation result C 1 is negative, i.e. D 0 ⁇ D 1 , the adder/subtracter CAL 11 outputs “1” as the sign flag F 1 . On the other hand, when the sign of the computation result C 1 is not negative, i.e. D 0 ⁇ D 1 , the adder/subtracter CAL 11 outputs “0” as the sign flag F 1 .
- the adder/subtracter CAL 12 subtracts the value of the data D 2 from the value of the data D 1 and outputs the subtraction result as the computation result C 2 . Further, the adder/subtracter CAL 12 outputs the sign flag F 2 according to the subtraction result. Specifically, when the sign of the computation result C 2 is negative, i.e. D 1 ⁇ D 2 , the adder/subtracter CAL 12 outputs “1” as the sign flag F 2 . On the other hand, when the sign of the computation result C 2 is not negative, i.e. D 1 ⁇ D 2 , the adder/subtracter CAL 12 outputs “0” as the sign flag F 2 .
- the adder/subtracter CAL 13 subtracts the value of the data D 0 from the value of the data D 2 and outputs the subtraction result as the computation result C 3 . Further, the adder/subtracter CAL 13 outputs the sign flag F 3 according to the subtraction result. Specifically, when the sign of the computation result C 3 is negative, i.e. D 2 ⁇ D 0 , the adder/subtracter CAL 13 outputs “1” as the sign flag F 3 . On the other hand, when the sign of the computation result C 3 is not negative, i.e. D 2 ⁇ D 0 , the adder/subtracter CAL 13 outputs “0” as the sign flag F 3 .
- the decision unit 40 determines a magnitude relation among the data D 0 to D 2 according to the sign flags F 1 to F 3 .
- the decision unit 40 then outputs the control signals CON 1 to CONS on the basis of the magnitude relation of the data D 0 to D 2 .
- FIG. 2 is a diagram showing a decision table 41 that is stored in the decision unit 40 .
- the decision unit 40 outputs “0”, “2” and “1” as the control signals CON 1 to CON 3 , respectively.
- Each of the selectors SEL 11 to SEL 13 selects any one of the input ports ps 0 to ps 2 according to the control signals CON 1 to CON 3 . Specifically, when the value of the control signals CON 1 to CON 3 is k (k is an integer of 0 to 2), each of the selectors SEL 11 to SEL 13 selects an input port psk.
- the selector SEL 11 selects the data D 0 that is input to the input port ps 0 according to the value “0” of the control signal CON 1 .
- the data D 0 is thereby specified as the maximum value MAX.
- the selector SEL 11 functions as a maximum value selector.
- the selector SEL 11 outputs the data D 0 , which is the maximum value MAX, to the port IN 1 of the register file 101 . Accordingly, the port IN 1 of the register file 101 always receives the maximum value MAX.
- the selector SEL 12 selects the data D 2 that is input to the input port ps 2 according to the value “2” of the control signal CON 2 .
- the data D 2 is thereby specified as the minimum value MIN.
- the selector SEL 12 functions as a minimum value selector.
- the selector SEL 12 outputs the data D 2 , which is the minimum value MIN, to the port IN 2 of the register file 101 . Accordingly, the port IN 2 of the register file 101 always receives the minimum value MIN.
- the selector SEL 13 selects the computation result C 2 that is input to the input port ps 1 according to the value “1” of the control signal CON 3 .
- the computation result C 2 i.e. (D 1 ⁇ D 2 )
- the selector SEL 13 selects the computation result C 2 of the adder/subtracter CAL 12 to which the maximum value MAX (D 0 ) is not input as the difference DIFF according to the control signal CON 3 .
- the selector SEL 13 functions as a difference selector.
- the selector SEL 13 outputs the computation result C 2 , which is the difference DIFF, to the port IN 3 of the register file 101 . Accordingly, the port IN 3 of the register file 101 always receives the difference DIFF.
- the selectors SEL 11 to SEL 13 output the maximum value MAX, the minimum value MIN and the difference DIFF, respectively, when the sign flags F 1 to F 3 are other values as a matter of course.
- vmax (d 0 >d 1 )?((d 0 >d 2 )?d 0 :d 2 ):((d 1 >d 2 )?d 1 :d 2 );
- Vdiff d 2 ⁇ d 0 ;
- Vdiff d 0 ⁇ d 1 ;
- vmax corresponds to the maximum value MAX
- vmin corresponds to the minimum value MIN
- vdiff corresponds to the difference DIFF
- d 0 to d 2 correspond to the data D 0 to D 2 , respectively.
- the arithmetic circuit 10 detects the maximum value MAX, the minimum value MIN and the difference DIFF between two values other than the maximum value MAX on the basis of the decision result of the decision unit 40 . Then, the arithmetic circuit 10 can output the maximum value MAX, the minimum value MIN and the difference DIFF between two values other than the maximum value MAX to the corresponding ports IN 1 to IN 3 of the register file 101 . Thus, the arithmetic circuit 10 can calculate the maximum value MAX and the minimum value MIN in one cycle without temporarily storing the intermediate computation result into the register file 101 after reading data from the register file 101 .
- the arithmetic circuit 10 can perform computations that involve conditional branch to compare three or more values and specify the maximum value, the minimum value and the like of the values in one cycle. Therefore, faster calculation is possible compared with the case of calculating the maximum value MAX and the minimum value MIN of three or more values in a plurality of cycles. Consequently, in this configuration, it is possible to achieve the arithmetic circuit and the arithmetic apparatus that can perform comparison involving conditional branch of three or more values at high speed.
- conditional branch is required, which hinders the speed-up of the conversion from the RGB color space to the HSV color space.
- the decision unit 40 can determine which of the data D 0 to D 2 is the maximum value by referring to the sign flags F 1 to F 3 and thereby find which of the equations (1) to (3) is to be used. Consequently, in this configuration, it is possible to achieve the arithmetic circuit and the arithmetic apparatus that can perform conditional branch at high speed in the conversion from the RGB color space to the HSV color space.
- the arithmetic apparatus 100 and the arithmetic circuit 10 can perform the conversion from the RGB color space to the HSV color space at high speed and efficiently.
- FIG. 3 is a block diagram schematically showing a configuration of the arithmetic apparatus 100 when setting the decision table 41 externally.
- a decision information setting instruction SET is given to the decision unit 40 from a control circuit 102 outside the arithmetic apparatus 100 .
- the decision information setting instruction SET is an instruction having the information content of 32 bits, and it is an instruction to set the values of the control signals CON 1 to CON 3 contained in the decision table 41 .
- FIG. 4 is a diagram showing set values of the decision table 41 . As shown in FIG. 4 , set values d 01 to d 03 , d 11 to d 13 , d 21 to d 23 , d 31 to d 33 , d 41 to d 43 , d 51 to d 53 , d 61 to d 63 and d 71 to d 73 are assigned to the control signals CON 1 to CON 3 .
- the information content of 3 bits is allocated to each of the set values. Accordingly, ten set values can be set at a time by the 32-bit decision information setting instruction SET.
- specific values can be set to the set values d 01 to d 03 , d 11 to d 13 , d 21 to d 23 , d 31 to d 33 , d 41 to d 43 , d 51 to d 53 and d 61 to d 63 of the decision table 41 .
- the decision information setting instruction SET can be represented by the following statement. Statement representing the decision information setting instruction SET:
- idx indicates the order of the decision information setting instruction SET, and when the decision information setting instruction SET is given three times, any of 0 to 2 is assigned.
- the value val indicates values assigned to the set values d 01 to d 03 , d 11 to d 13 , d 21 to d 23 , d 31 to d 33 , d 41 to d 43 , d 51 to d 53 and d 61 to d 63 .
- the value val is represented by 32-bit immediate value.
- FIG. 5 is a diagram showing a structure example of the value val of the decision information setting instruction SET according to the first embodiment.
- the value val of the decision information setting instruction SET is composed of two free bits 50 and values e 0 to e 9 of 3 bits each, for example.
- FIG. 6 is a diagram showing a relation between the value val of the decision information setting instruction SET and the set values of the decision table 41 . The case of setting the values shown in FIG. 2 as the control signals CON 1 to CON 3 is discussed, for example.
- the value val of the decision information setting instruction SET is the value shown in FIG. 5 in binary form. Conversion of this value into 32-bit immediate value expressed in hexadecimal form results in “0x00000002”.
- the decision information setting instruction SET can be represented by the following statement. Statement representing the decision information setting instruction SET:
- the values in the decision table 41 can be set specifically.
- the arithmetic apparatus 200 is an apparatus capable of performing sorting of three data D 0 to D 2 in addition to the HSV conversion performed in the arithmetic apparatus 100 according to the first embodiment.
- FIG. 7 is a block diagram schematically showing a configuration of the arithmetic apparatus 200 according to the second embodiment.
- the arithmetic apparatus 200 is an example of the transformation of the configuration of the arithmetic apparatus 100 according to the first embodiment, and the configuration of the arithmetic circuit differs specifically.
- the arithmetic apparatus 200 includes a register file 101 and an arithmetic circuit 20 .
- the register file 101 is the same as that of the first embodiment and thus not redundantly described.
- the arithmetic circuit 20 includes slots 11 , 12 and 23 , and a decision unit 40 .
- an adder/subtracter CAL 11 outputs a computation result C 1 to a selector SEL 23 .
- the other configuration of the slot 11 is the same as that of the first embodiment and thus not redundantly described.
- an adder/subtracter CAL 12 outputs a computation result C 2 to the selector SEL 23 .
- the other configuration of the slot 12 is the same as that of the first embodiment and thus not redundantly described.
- the decision unit 40 is the same as that of the arithmetic circuit 10 and thus not redundantly described.
- the slot 23 includes an adder/subtracter CAL 13 and the selector SEL 23 .
- the selector SEL 23 is a 6-input 1-output selector, which corresponds to a third selection circuit.
- the adder/subtracter CAL 13 outputs a computation result C 3 to the selector SEL 23 .
- the computation results C 1 to C 3 of the adders/subtracters CAL 11 to CAL 13 are respectively input to input ports ps 0 to ps 2 of the selector SEL 23 , and the data D 0 to D 2 are respectively input to input ports ps 3 to ps 5 of the selector SEL 23 .
- the selector SEL 23 then outputs any of the data D 0 to D 2 as an intermediate value MID to the port IN 3 of the register file 101 based on a control signal CON 3 from the decision unit 40 .
- the other configuration of the slot 23 is the same as that of the slot 13 and thus not redundantly described.
- the HSV conversion in the arithmetic apparatus 200 is the same as that of the arithmetic apparatus 100 according to the first embodiment and not redundantly described, and sorting is described hereinbelow.
- the arithmetic apparatus 200 is capable of switching between the HSV conversion and the sorting by changing the set values of the decision table by the decision information setting instruction SET that is input to the decision unit 40 from the external control circuit 102 .
- the sorting is specifically described hereinafter.
- the adder/subtracter CAL 11 subtracts the value of the data D 1 from the value of the data D 0 and outputs the subtraction result as the computation result C 1 , as in the case of the HSV conversion. Further, the adder/subtracter CAL 11 outputs the sign flag F 1 according to the subtraction result. Specifically, when the sign of the computation result C 1 is negative, i.e. D 0 ⁇ D 1 , the adder/subtracter CAL 11 outputs “1” as the sign flag F 1 . On the other hand, when the sign of the computation result C 1 is not negative, i.e. D 0 ⁇ D 1 , the adder/subtracter CAL 11 outputs “0” as the sign flag F 1 .
- the adder/subtracter CAL 12 subtracts the value of the data D 2 from the value of the data D 1 and outputs the subtraction result as the computation result C 2 , as in the case of the HSV conversion. Further, the adder/subtracter CAL 12 outputs the sign flag F 2 according to the subtraction result. Specifically, when the sign of the computation result C 2 is negative, i.e. D 1 ⁇ D 2 , the adder/subtracter CAL 12 outputs “1” as the sign flag F 2 . On the other hand, when the sign of the computation result C 2 is not negative, i.e. D 1 ⁇ D 2 , the adder/subtracter CAL 12 outputs “0” as the sign flag F 2 .
- the adder/subtracter CAL 13 subtracts the value of the data D 0 from the value of the data D 2 and outputs the subtraction result as the computation result C 3 , as in the case of the HSV conversion. Further, the adder/subtracter CAL 13 outputs the sign flag F 3 according to the subtraction result. Specifically, when the sign of the computation result C 3 is negative, i.e. D 2 ⁇ D 0 , the adder/subtracter CAL 13 outputs “1” as the sign flag F 3 . On the other hand, when the sign of the computation result C 3 is not negative, i.e. the adder/subtracter CAL 13 outputs “0” as the sign flag F 3 .
- the decision unit 40 determines a magnitude relation among the data D 0 to D 2 according to the sign flags F 1 to F 3 .
- the decision unit 40 then outputs the control signals CON 1 to CON 3 on the basis of the magnitude relation of the data D 0 to D 2 .
- FIG. 8 is a diagram showing a decision table 42 for the sorting that is stored in the decision unit 40 . Note that the decision table 42 corresponds to a second decision table.
- the decision unit 40 outputs “0”, “2” and “4” as the control signals CON 1 to CON 3 , respectively.
- Each of the selectors SEL 11 and SEL 12 selects any one of the input ports ps 0 to ps 2 according to the control signals CON 1 and CON 2 .
- the selector SEL 23 selects any of the input ports ps 0 to ps 5 according to the control signal CON 3 . Specifically, when the value of the control signals CON 1 and CON 2 is k (k is an integer of 0 to 2), each of the selectors SEL 11 and SEL 12 selects an input port psk. When the value of the control signal CON 3 is j (j is an integer of 0 to 5), the selector SEL 23 selects an input port psj.
- the selector SEL 11 selects the data D 0 that is input to the input port ps 0 according to the value “0” of the control signal CON 1 , as in the case of the HSV conversion.
- the data D 0 is thereby specified as the maximum value MAX.
- the selector SEL 11 functions as a maximum value selector.
- the selector SEL 11 outputs the data D 0 , which is the maximum value MAX, to the port IN 1 of the register file 101 . Accordingly, the port IN 1 of the register file 101 always receives the maximum value MAX.
- the selector SEL 12 selects the data D 2 that is input to the input port ps 2 according to the value “2” of the control signal CON 2 , as in the case of the HSV conversion.
- the data D 2 is thereby specified as the minimum value MIN.
- the selector SEL 12 functions as a minimum value selector.
- the selector SEL 12 outputs the data D 2 , which is the minimum value MIN, to the port IN 2 of the register file 101 . Accordingly, the port IN 2 of the register file 101 always receives the minimum value MIN.
- the selector SEL 23 selects the data D 1 that is input to the input port ps 4 according to the value “4” of the control signal CONS.
- the data D 1 is thereby specified as the intermediate value MID.
- the selector SEL 23 functions as an intermediate value selector.
- the selector SEL 23 outputs the data D 1 , which is the intermediate value MID, to the port IN 3 of the register file 101 . Accordingly, the port IN 3 of the register file 101 always receives the intermediate value MID.
- the selectors SEL 11 , SEL 12 and SEL 23 output the maximum value MAX, the minimum value MIN and the intermediate value MID, respectively, when the sign flags F 1 to F 3 are other values as a matter of course.
- FIG. 9 is a block diagram schematically showing a configuration of the arithmetic apparatus 200 when setting the decision table 42 externally.
- the decision table 41 can be replaced with the decision table 42 by the decision information setting instruction SET in the following procedure.
- the decision table 42 can be replaced with the decision table 41 in the same procedure as a matter of course.
- the decision information setting instruction SET is given to the decision unit 40 from a control circuit 102 outside the arithmetic apparatus 200 .
- the set values of the decision table 42 are the same as those of the decision table 41 described earlier with reference to FIG. 4 and thus not redundantly described.
- the structure of the value val of the decision information setting instruction SET is described earlier with reference to FIG. 5 and thus not redundantly described.
- the relation between the value val of the decision information setting instruction SET and the set values of the decision table 42 is also described earlier with reference to FIG. 6 and thus not redundantly described.
- FIG. 10 is a diagram showing a structure example of the value val of the decision information setting instruction SET according to the second embodiment.
- the decision information setting instruction SET is the value shown in FIG. 10 in binary form. Conversion of this value into 32-bit immediate value expressed in hexadecimal form results in “0x00000102”.
- the decision information setting instruction SET can be represented by the following statement. Statement representing the decision information setting instruction SET:
- the arithmetic circuit 20 detects the maximum value MAX, the minimum value MIN and the intermediate value MID on the basis of the decision result of the decision unit 40 . Then, the arithmetic circuit 20 can output the maximum value MAX, the minimum value MIN and the intermediate value MID to the corresponding ports IN 1 to IN 3 of the register file 101 . Thus, the arithmetic circuit 20 can determine the magnitude relation of the data D 0 to D 2 read from the register file 101 and sort the values, in addition to performing the HSV conversion. In other words, the arithmetic circuit 20 can perform computations that requires conditional branch to compare three or more values and specify the maximum value, the minimum value and the like of the values, which is the sorting specifically, in one cycle.
- the arithmetic circuit 20 can calculate the maximum value MAX, the minimum value MIN and the intermediate value MID in one cycle without temporarily storing the intermediate computation result into the register file 101 after reading data from the register file 101 .
- the arithmetic circuit 20 can thereby perform the sorting at high speed.
- the arithmetic apparatus 300 is an apparatus capable of specifying constants that are used for the conversion from the RGB color space to the HSV color space at the same time in addition to the HSV conversion performed in the arithmetic apparatus 100 according to the first embodiment.
- FIG. 11 is a block diagram schematically showing a configuration of the arithmetic apparatus 300 according to the third embodiment.
- the arithmetic apparatus 300 is an example of the transformation of the configuration of the arithmetic apparatus 100 according to the first embodiment, and the configuration of the arithmetic circuit differs specifically.
- the arithmetic apparatus 300 includes a register file 101 and an arithmetic circuit 30 .
- the register file 101 is the same as that of the first embodiment except that a port IN 4 is added, and thus not redundantly described.
- the arithmetic circuit 30 includes slots 11 to 13 and 34 , and a decision unit 43 .
- the slots 11 to 13 are the same as those of the arithmetic circuit 10 and thus not redundantly described.
- the slot 34 includes constant registers 341 to 343 and a selector SEL 34 .
- the selector SEL 34 is a 3-input 1-output selector, which corresponds to a fourth selection circuit.
- Constant data CD 0 to CD 2 are respectively input to input ports ps 0 to ps 2 of the selector SEL 34 from the constant registers 341 to 343 .
- the selector SEL 34 then outputs any of the constant data CD 0 to CD 2 as a constant CONST to the port IN 4 of the register file 101 based on a control signal CON 4 from the decision unit 43 .
- the decision unit 43 outputs the control signals CON 1 to CON 3 to the selectors SEL 11 to SEL 13 , respectively, and outputs the control signal CON 4 to the selector SEL 34 of the slot 34 by reference to a stored decision table 44 on the basis of the sign flags F 1 to F 3 .
- the decision table 44 corresponds to a third decision table.
- the decision unit 43 determines a magnitude relation among the data D 0 to D 2 according to the sign flags F 1 to F 3 .
- the decision unit 43 then outputs the control signals CON 1 to CON 4 on the basis of the magnitude relation of the data D 0 to D 2 .
- FIG. 12 is a diagram showing a decision table 44 that is stored in the decision unit 43 .
- the sign flags F 1 to F 3 are “0”, “0” and “1”, respectively, the propositions “D 0 ⁇ D 1 ” and “D 1 ⁇ D 2 ” are false, and the proposition “D 2 ⁇ D 0 ” is true.
- the magnitude relation “D 1 ⁇ D 1 ⁇ D 2 ” is established for the data D 0 to D 2 .
- the decision unit 43 outputs “0”, “2”, “1” and “0” as the control signals CON 1 to CON 4 , respectively.
- the selector SEL 34 selects any of the input ports ps 0 to ps 2 according to the control signal CON 4 . Specifically, when the value of the control signal CON 4 is k (k is an integer of 0 to 2), the selector SEL 34 selects an input port psk. Because the control signal CON 4 is “0” as described above, the selector SEL 34 selects the input port ps 0 . The selector SEL 34 outputs the constant data CD 0 as the constant CONST.
- the values of the constant data CD 0 to CD 2 are “0”, “120” and “240”, respectively.
- the selector SEL 34 selects the constant data CD 0 indicating the constant part of the equation (1) as the constant CONST.
- G or B which is the data D 1 or D 2
- the appropriate constant can be calculated as a result that the decision unit 43 makes decision using the decision table 44 .
- an instruction given to the arithmetic apparatus 300 is represented by the following statement using C language, for example.
- vmax (d 0 >d 1 )?((d 0 >d 2 )?d 0 :d 2 ):((d 1 >d 2 )?d 1 :d 2 );
- Vdiff d 2 ⁇ d 0 ;
- Vdiff d 0 ⁇ d 1 ;
- vmax corresponds to the maximum value MAX
- vmin corresponds to the minimum value MIN
- vdiff corresponds to the difference DIFF
- const corresponds to the constant CONST
- d 0 to d 2 correspond to data D 0 to D 2 , respectively.
- control circuit 102 is disposed inside the arithmetic apparatus 100 or 200 in FIGS. 3 and 9 , it may be disposed outside the arithmetic apparatus 100 or 200 .
- decision table 41 is rewritten by the decision information setting instruction SET in the second embodiment, this is by way of illustration.
- a decision table for the HSV conversion and a decision table for the sorting may be prestored in the decision unit 40 , and the decision table to be used may be designated by a selection signal from the control circuit.
- the structure of the decision information setting instruction SET in the above-described embodiments is merely by way of illustration.
- the values e 0 to e 9 in the value val of the decision information setting instruction SET may be arranged in a different order.
- the positions of free bits may be at other positions.
- the correspondence between the set values of the decision table and the values e 0 to e 9 may be another one. Note that, although the value val of the decision information setting instruction SET is expressed in hexadecimal form, it may be expressed in another form.
- the first to third embodiments can be combined as desirable by one of ordinary skill in the art.
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Abstract
Description
V=MAX (5)
Claims (15)
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US14/564,865 US20150095392A1 (en) | 2011-08-10 | 2014-12-09 | Arithmetic circuit and arithmetic apparatus |
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JP2011174849A JP5763472B2 (en) | 2011-08-10 | 2011-08-10 | Arithmetic circuit and arithmetic unit |
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US14/564,865 Continuation US20150095392A1 (en) | 2011-08-10 | 2014-12-09 | Arithmetic circuit and arithmetic apparatus |
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US20130041929A1 US20130041929A1 (en) | 2013-02-14 |
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US13/546,683 Expired - Fee Related US8954483B2 (en) | 2011-08-10 | 2012-07-11 | Arithmetic circuit and arithmetic apparatus |
US14/564,865 Abandoned US20150095392A1 (en) | 2011-08-10 | 2014-12-09 | Arithmetic circuit and arithmetic apparatus |
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MX2020008289A (en) | 2018-02-08 | 2020-09-25 | Genentech Inc | Bispecific antigen-binding molecules and methods of use. |
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2011
- 2011-08-10 JP JP2011174849A patent/JP5763472B2/en not_active Expired - Fee Related
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2012
- 2012-07-11 US US13/546,683 patent/US8954483B2/en not_active Expired - Fee Related
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2014
- 2014-12-09 US US14/564,865 patent/US20150095392A1/en not_active Abandoned
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JPS60104942U (en) | 1983-12-19 | 1985-07-17 | 三菱電機株式会社 | Maximum or minimum value detection device |
JPH02186436A (en) | 1989-01-13 | 1990-07-20 | Koufu Nippon Denki Kk | N-input retrieve circuit |
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JP2004062401A (en) | 2002-07-26 | 2004-02-26 | Matsushita Electric Ind Co Ltd | Arithmetic processor and camera device using it |
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Also Published As
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JP5763472B2 (en) | 2015-08-12 |
US20150095392A1 (en) | 2015-04-02 |
JP2013037613A (en) | 2013-02-21 |
US20130041929A1 (en) | 2013-02-14 |
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